base.hh revision 3276
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Dave Greene 302665Ssaidi@eecs.umich.edu * Nathan Binkert 312SN/A */ 322SN/A 332623SN/A#ifndef __CPU_SIMPLE_BASE_HH__ 342623SN/A#define __CPU_SIMPLE_BASE_HH__ 352SN/A 361354SN/A#include "base/statistics.hh" 371858SN/A#include "config/full_system.hh" 381717SN/A#include "cpu/base.hh" 392683Sktlim@umich.edu#include "cpu/simple_thread.hh" 401354SN/A#include "cpu/pc_event.hh" 411354SN/A#include "cpu/static_inst.hh" 422387SN/A#include "mem/packet.hh" 432387SN/A#include "mem/port.hh" 442387SN/A#include "mem/request.hh" 4556SN/A#include "sim/eventq.hh" 462SN/A 472SN/A// forward declarations 481858SN/A#if FULL_SYSTEM 492SN/Aclass Processor; 50676SN/Aclass AlphaITB; 51676SN/Aclass AlphaDTB; 522462SN/Aclass MemObject; 532SN/A 542SN/Aclass RemoteGDB; 552SN/Aclass GDBListener; 56715SN/A 57715SN/A#else 58715SN/A 59715SN/Aclass Process; 60715SN/A 612SN/A#endif // FULL_SYSTEM 622SN/A 632680Sktlim@umich.educlass ThreadContext; 64237SN/Aclass Checkpoint; 652SN/A 662SN/Anamespace Trace { 672SN/A class InstRecord; 682SN/A} 692SN/A 702420SN/A 712623SN/Aclass BaseSimpleCPU : public BaseCPU 722SN/A{ 732107SN/A protected: 742107SN/A typedef TheISA::MachInst MachInst; 752159SN/A typedef TheISA::MiscReg MiscReg; 762455SN/A typedef TheISA::FloatReg FloatReg; 772455SN/A typedef TheISA::FloatRegBits FloatRegBits; 782386SN/A 792499SN/A MemObject *mem; 802386SN/A 812623SN/A protected: 822SN/A Trace::InstRecord *traceData; 831371SN/A 842SN/A public: 852SN/A void post_interrupt(int int_num, int index); 862SN/A 872SN/A void zero_fill_64(Addr addr) { 882SN/A static int warned = 0; 892SN/A if (!warned) { 902SN/A warn ("WH64 is not implemented"); 912SN/A warned = 1; 922SN/A } 932SN/A }; 942SN/A 951400SN/A public: 961400SN/A struct Params : public BaseCPU::Params 971400SN/A { 982542SN/A MemObject *mem; 991858SN/A#if FULL_SYSTEM 1001400SN/A AlphaITB *itb; 1011400SN/A AlphaDTB *dtb; 1022SN/A#else 1031400SN/A Process *process; 1042SN/A#endif 1051400SN/A }; 1062623SN/A BaseSimpleCPU(Params *params); 1072623SN/A virtual ~BaseSimpleCPU(); 1082SN/A 1091400SN/A public: 1102683Sktlim@umich.edu /** SimpleThread object, provides all the architectural state. */ 1112683Sktlim@umich.edu SimpleThread *thread; 1122190SN/A 1132683Sktlim@umich.edu /** ThreadContext object, provides an interface for external 1142683Sktlim@umich.edu * objects to modify this thread's state. 1152683Sktlim@umich.edu */ 1162680Sktlim@umich.edu ThreadContext *tc; 1172SN/A 1181858SN/A#if FULL_SYSTEM 1192SN/A Addr dbg_vtophys(Addr addr); 1202SN/A 1212SN/A bool interval_stats; 1222SN/A#endif 1232SN/A 1242SN/A // current instruction 1252SN/A MachInst inst; 1262SN/A 1272566SN/A // Static data storage 1282566SN/A TheISA::IntReg dataReg; 1292566SN/A 1302107SN/A StaticInstPtr curStaticInst; 1313276Sgblack@eecs.umich.edu StaticInstPtr curMacroStaticInst; 1321469SN/A 1332623SN/A void checkForInterrupts(); 1342662Sstever@eecs.umich.edu Fault setupFetchRequest(Request *req); 1352623SN/A void preExecute(); 1362623SN/A void postExecute(); 1372623SN/A void advancePC(Fault fault); 138180SN/A 139393SN/A virtual void deallocateContext(int thread_num); 140393SN/A virtual void haltContext(int thread_num); 1412SN/A 1422SN/A // statistics 143334SN/A virtual void regStats(); 144334SN/A virtual void resetStats(); 1452SN/A 1462SN/A // number of simulated instructions 1472SN/A Counter numInst; 148334SN/A Counter startNumInst; 149729SN/A Stats::Scalar<> numInsts; 150707SN/A 151707SN/A virtual Counter totalInstructions() const 152707SN/A { 153707SN/A return numInst - startNumInst; 154707SN/A } 1552SN/A 1562SN/A // number of simulated memory references 157729SN/A Stats::Scalar<> numMemRefs; 1582SN/A 159124SN/A // number of simulated loads 160124SN/A Counter numLoad; 161334SN/A Counter startNumLoad; 162124SN/A 1632SN/A // number of idle cycles 164729SN/A Stats::Average<> notIdleFraction; 165729SN/A Stats::Formula idleFraction; 1662SN/A 1672390SN/A // number of cycles stalled for I-cache responses 168729SN/A Stats::Scalar<> icacheStallCycles; 1692SN/A Counter lastIcacheStall; 1702SN/A 1712390SN/A // number of cycles stalled for I-cache retries 1722390SN/A Stats::Scalar<> icacheRetryCycles; 1732390SN/A Counter lastIcacheRetry; 1742390SN/A 1752390SN/A // number of cycles stalled for D-cache responses 176729SN/A Stats::Scalar<> dcacheStallCycles; 1772SN/A Counter lastDcacheStall; 1782SN/A 1792390SN/A // number of cycles stalled for D-cache retries 1802390SN/A Stats::Scalar<> dcacheRetryCycles; 1812390SN/A Counter lastDcacheRetry; 1822390SN/A 183217SN/A virtual void serialize(std::ostream &os); 184237SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 1852SN/A 1861371SN/A // These functions are only used in CPU models that split 1871371SN/A // effective address computation from the actual memory access. 1882623SN/A void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); } 1892623SN/A Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); } 1901371SN/A 191581SN/A void prefetch(Addr addr, unsigned flags) 1922SN/A { 1932SN/A // need to do this... 1942SN/A } 1952SN/A 196753SN/A void writeHint(Addr addr, int size, unsigned flags) 1972SN/A { 1982SN/A // need to do this... 1992SN/A } 200594SN/A 201595SN/A Fault copySrcTranslate(Addr src); 202594SN/A 203595SN/A Fault copy(Addr dest); 204705SN/A 205726SN/A // The register accessor methods provide the index of the 206726SN/A // instruction's operand (e.g., 0 or 1), not the architectural 207726SN/A // register index, to simplify the implementation of register 208726SN/A // renaming. We find the architectural register index by indexing 209726SN/A // into the instruction's own operand index table. Note that a 210726SN/A // raw pointer to the StaticInst is provided instead of a 211726SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 212726SN/A // long as these methods don't copy the pointer into any long-term 213726SN/A // storage (which is pretty hard to imagine they would have reason 214726SN/A // to do). 215705SN/A 2162107SN/A uint64_t readIntReg(const StaticInst *si, int idx) 217726SN/A { 2182683Sktlim@umich.edu return thread->readIntReg(si->srcRegIdx(idx)); 219726SN/A } 220705SN/A 2212455SN/A FloatReg readFloatReg(const StaticInst *si, int idx, int width) 222726SN/A { 223726SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2242683Sktlim@umich.edu return thread->readFloatReg(reg_idx, width); 225726SN/A } 226705SN/A 2272455SN/A FloatReg readFloatReg(const StaticInst *si, int idx) 228726SN/A { 229726SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2302683Sktlim@umich.edu return thread->readFloatReg(reg_idx); 231726SN/A } 232705SN/A 2332455SN/A FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width) 234726SN/A { 235726SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2362683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx, width); 2372455SN/A } 2382455SN/A 2392455SN/A FloatRegBits readFloatRegBits(const StaticInst *si, int idx) 2402455SN/A { 2412455SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2422683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx); 243726SN/A } 244705SN/A 2452107SN/A void setIntReg(const StaticInst *si, int idx, uint64_t val) 246726SN/A { 2472683Sktlim@umich.edu thread->setIntReg(si->destRegIdx(idx), val); 248726SN/A } 249705SN/A 2502455SN/A void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width) 251726SN/A { 252726SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2532683Sktlim@umich.edu thread->setFloatReg(reg_idx, val, width); 254726SN/A } 255705SN/A 2562455SN/A void setFloatReg(const StaticInst *si, int idx, FloatReg val) 257726SN/A { 258726SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2592683Sktlim@umich.edu thread->setFloatReg(reg_idx, val); 260726SN/A } 261726SN/A 2622455SN/A void setFloatRegBits(const StaticInst *si, int idx, 2632577SN/A FloatRegBits val, int width) 264726SN/A { 265726SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2662683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val, width); 2672455SN/A } 2682455SN/A 2692455SN/A void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val) 2702455SN/A { 2712455SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2722683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val); 273726SN/A } 274705SN/A 2752683Sktlim@umich.edu uint64_t readPC() { return thread->readPC(); } 2762683Sktlim@umich.edu uint64_t readNextPC() { return thread->readNextPC(); } 2772683Sktlim@umich.edu uint64_t readNextNPC() { return thread->readNextNPC(); } 2782447SN/A 2792683Sktlim@umich.edu void setPC(uint64_t val) { thread->setPC(val); } 2802683Sktlim@umich.edu void setNextPC(uint64_t val) { thread->setNextPC(val); } 2812683Sktlim@umich.edu void setNextNPC(uint64_t val) { thread->setNextNPC(val); } 282705SN/A 2832159SN/A MiscReg readMiscReg(int misc_reg) 2842159SN/A { 2852683Sktlim@umich.edu return thread->readMiscReg(misc_reg); 2862159SN/A } 287705SN/A 2882159SN/A MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) 2892159SN/A { 2902683Sktlim@umich.edu return thread->readMiscRegWithEffect(misc_reg, fault); 2912159SN/A } 2922159SN/A 2932159SN/A Fault setMiscReg(int misc_reg, const MiscReg &val) 2942159SN/A { 2952683Sktlim@umich.edu return thread->setMiscReg(misc_reg, val); 2962159SN/A } 2972159SN/A 2982159SN/A Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) 2992159SN/A { 3002683Sktlim@umich.edu return thread->setMiscRegWithEffect(misc_reg, val); 3012159SN/A } 302705SN/A 3031858SN/A#if FULL_SYSTEM 3042683Sktlim@umich.edu Fault hwrei() { return thread->hwrei(); } 3052683Sktlim@umich.edu int readIntrFlag() { return thread->readIntrFlag(); } 3062683Sktlim@umich.edu void setIntrFlag(int val) { thread->setIntrFlag(val); } 3072683Sktlim@umich.edu bool inPalMode() { return thread->inPalMode(); } 3082680Sktlim@umich.edu void ev5_trap(Fault fault) { fault->invoke(tc); } 3092683Sktlim@umich.edu bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 310705SN/A#else 3112683Sktlim@umich.edu void syscall(int64_t callnum) { thread->syscall(callnum); } 312705SN/A#endif 313705SN/A 3142683Sktlim@umich.edu bool misspeculating() { return thread->misspeculating(); } 3152680Sktlim@umich.edu ThreadContext *tcBase() { return tc; } 3162SN/A}; 3172SN/A 3182623SN/A#endif // __CPU_SIMPLE_BASE_HH__ 319