base.hh revision 2683
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Dave Greene 302665Ssaidi@eecs.umich.edu * Nathan Binkert 312SN/A */ 322SN/A 332623SN/A#ifndef __CPU_SIMPLE_BASE_HH__ 342623SN/A#define __CPU_SIMPLE_BASE_HH__ 352SN/A 361354SN/A#include "base/statistics.hh" 371858SN/A#include "config/full_system.hh" 381717SN/A#include "cpu/base.hh" 392683Sktlim@umich.edu#include "cpu/simple_thread.hh" 401354SN/A#include "cpu/pc_event.hh" 411717SN/A#include "cpu/sampler/sampler.hh" 421354SN/A#include "cpu/static_inst.hh" 432387SN/A#include "mem/packet.hh" 442387SN/A#include "mem/port.hh" 452387SN/A#include "mem/request.hh" 4656SN/A#include "sim/eventq.hh" 472SN/A 482SN/A// forward declarations 491858SN/A#if FULL_SYSTEM 502SN/Aclass Processor; 51676SN/Aclass AlphaITB; 52676SN/Aclass AlphaDTB; 532462SN/Aclass MemObject; 542SN/A 552SN/Aclass RemoteGDB; 562SN/Aclass GDBListener; 57715SN/A 58715SN/A#else 59715SN/A 60715SN/Aclass Process; 61715SN/A 622SN/A#endif // FULL_SYSTEM 632SN/A 642680Sktlim@umich.educlass ThreadContext; 65237SN/Aclass Checkpoint; 662SN/A 672SN/Anamespace Trace { 682SN/A class InstRecord; 692SN/A} 702SN/A 712420SN/A 722623SN/Aclass BaseSimpleCPU : public BaseCPU 732SN/A{ 742107SN/A protected: 752107SN/A typedef TheISA::MachInst MachInst; 762159SN/A typedef TheISA::MiscReg MiscReg; 772455SN/A typedef TheISA::FloatReg FloatReg; 782455SN/A typedef TheISA::FloatRegBits FloatRegBits; 792386SN/A 802499SN/A MemObject *mem; 812386SN/A 822623SN/A protected: 832SN/A Trace::InstRecord *traceData; 841371SN/A 852SN/A public: 862SN/A void post_interrupt(int int_num, int index); 872SN/A 882SN/A void zero_fill_64(Addr addr) { 892SN/A static int warned = 0; 902SN/A if (!warned) { 912SN/A warn ("WH64 is not implemented"); 922SN/A warned = 1; 932SN/A } 942SN/A }; 952SN/A 961400SN/A public: 971400SN/A struct Params : public BaseCPU::Params 981400SN/A { 992542SN/A MemObject *mem; 1001858SN/A#if FULL_SYSTEM 1011400SN/A AlphaITB *itb; 1021400SN/A AlphaDTB *dtb; 1032SN/A#else 1041400SN/A Process *process; 1052SN/A#endif 1061400SN/A }; 1072623SN/A BaseSimpleCPU(Params *params); 1082623SN/A virtual ~BaseSimpleCPU(); 1092SN/A 1101400SN/A public: 1112683Sktlim@umich.edu /** SimpleThread object, provides all the architectural state. */ 1122683Sktlim@umich.edu SimpleThread *thread; 1132190SN/A 1142683Sktlim@umich.edu /** ThreadContext object, provides an interface for external 1152683Sktlim@umich.edu * objects to modify this thread's state. 1162683Sktlim@umich.edu */ 1172680Sktlim@umich.edu ThreadContext *tc; 1182SN/A 1191858SN/A#if FULL_SYSTEM 1202SN/A Addr dbg_vtophys(Addr addr); 1212SN/A 1222SN/A bool interval_stats; 1232SN/A#endif 1242SN/A 1252SN/A // current instruction 1262SN/A MachInst inst; 1272SN/A 1282566SN/A // Static data storage 1292566SN/A TheISA::IntReg dataReg; 1302566SN/A 1311492SN/A // Pointer to the sampler that is telling us to switchover. 1321492SN/A // Used to signal the completion of the pipe drain and schedule 1331492SN/A // the next switchover 1341752SN/A Sampler *sampler; 1351492SN/A 1362107SN/A StaticInstPtr curStaticInst; 1371469SN/A 1382623SN/A void checkForInterrupts(); 1392662Sstever@eecs.umich.edu Fault setupFetchRequest(Request *req); 1402623SN/A void preExecute(); 1412623SN/A void postExecute(); 1422623SN/A void advancePC(Fault fault); 143180SN/A 144393SN/A virtual void deallocateContext(int thread_num); 145393SN/A virtual void haltContext(int thread_num); 1462SN/A 1472SN/A // statistics 148334SN/A virtual void regStats(); 149334SN/A virtual void resetStats(); 1502SN/A 1512SN/A // number of simulated instructions 1522SN/A Counter numInst; 153334SN/A Counter startNumInst; 154729SN/A Stats::Scalar<> numInsts; 155707SN/A 156707SN/A virtual Counter totalInstructions() const 157707SN/A { 158707SN/A return numInst - startNumInst; 159707SN/A } 1602SN/A 1612SN/A // number of simulated memory references 162729SN/A Stats::Scalar<> numMemRefs; 1632SN/A 164124SN/A // number of simulated loads 165124SN/A Counter numLoad; 166334SN/A Counter startNumLoad; 167124SN/A 1682SN/A // number of idle cycles 169729SN/A Stats::Average<> notIdleFraction; 170729SN/A Stats::Formula idleFraction; 1712SN/A 1722390SN/A // number of cycles stalled for I-cache responses 173729SN/A Stats::Scalar<> icacheStallCycles; 1742SN/A Counter lastIcacheStall; 1752SN/A 1762390SN/A // number of cycles stalled for I-cache retries 1772390SN/A Stats::Scalar<> icacheRetryCycles; 1782390SN/A Counter lastIcacheRetry; 1792390SN/A 1802390SN/A // number of cycles stalled for D-cache responses 181729SN/A Stats::Scalar<> dcacheStallCycles; 1822SN/A Counter lastDcacheStall; 1832SN/A 1842390SN/A // number of cycles stalled for D-cache retries 1852390SN/A Stats::Scalar<> dcacheRetryCycles; 1862390SN/A Counter lastDcacheRetry; 1872390SN/A 188217SN/A virtual void serialize(std::ostream &os); 189237SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 1902SN/A 1911371SN/A // These functions are only used in CPU models that split 1921371SN/A // effective address computation from the actual memory access. 1932623SN/A void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); } 1942623SN/A Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); } 1951371SN/A 196581SN/A void prefetch(Addr addr, unsigned flags) 1972SN/A { 1982SN/A // need to do this... 1992SN/A } 2002SN/A 201753SN/A void writeHint(Addr addr, int size, unsigned flags) 2022SN/A { 2032SN/A // need to do this... 2042SN/A } 205594SN/A 206595SN/A Fault copySrcTranslate(Addr src); 207594SN/A 208595SN/A Fault copy(Addr dest); 209705SN/A 210726SN/A // The register accessor methods provide the index of the 211726SN/A // instruction's operand (e.g., 0 or 1), not the architectural 212726SN/A // register index, to simplify the implementation of register 213726SN/A // renaming. We find the architectural register index by indexing 214726SN/A // into the instruction's own operand index table. Note that a 215726SN/A // raw pointer to the StaticInst is provided instead of a 216726SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 217726SN/A // long as these methods don't copy the pointer into any long-term 218726SN/A // storage (which is pretty hard to imagine they would have reason 219726SN/A // to do). 220705SN/A 2212107SN/A uint64_t readIntReg(const StaticInst *si, int idx) 222726SN/A { 2232683Sktlim@umich.edu return thread->readIntReg(si->srcRegIdx(idx)); 224726SN/A } 225705SN/A 2262455SN/A FloatReg readFloatReg(const StaticInst *si, int idx, int width) 227726SN/A { 228726SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2292683Sktlim@umich.edu return thread->readFloatReg(reg_idx, width); 230726SN/A } 231705SN/A 2322455SN/A FloatReg readFloatReg(const StaticInst *si, int idx) 233726SN/A { 234726SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2352683Sktlim@umich.edu return thread->readFloatReg(reg_idx); 236726SN/A } 237705SN/A 2382455SN/A FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width) 239726SN/A { 240726SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2412683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx, width); 2422455SN/A } 2432455SN/A 2442455SN/A FloatRegBits readFloatRegBits(const StaticInst *si, int idx) 2452455SN/A { 2462455SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2472683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx); 248726SN/A } 249705SN/A 2502107SN/A void setIntReg(const StaticInst *si, int idx, uint64_t val) 251726SN/A { 2522683Sktlim@umich.edu thread->setIntReg(si->destRegIdx(idx), val); 253726SN/A } 254705SN/A 2552455SN/A void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width) 256726SN/A { 257726SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2582683Sktlim@umich.edu thread->setFloatReg(reg_idx, val, width); 259726SN/A } 260705SN/A 2612455SN/A void setFloatReg(const StaticInst *si, int idx, FloatReg val) 262726SN/A { 263726SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2642683Sktlim@umich.edu thread->setFloatReg(reg_idx, val); 265726SN/A } 266726SN/A 2672455SN/A void setFloatRegBits(const StaticInst *si, int idx, 2682577SN/A FloatRegBits val, int width) 269726SN/A { 270726SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2712683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val, width); 2722455SN/A } 2732455SN/A 2742455SN/A void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val) 2752455SN/A { 2762455SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2772683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val); 278726SN/A } 279705SN/A 2802683Sktlim@umich.edu uint64_t readPC() { return thread->readPC(); } 2812683Sktlim@umich.edu uint64_t readNextPC() { return thread->readNextPC(); } 2822683Sktlim@umich.edu uint64_t readNextNPC() { return thread->readNextNPC(); } 2832447SN/A 2842683Sktlim@umich.edu void setPC(uint64_t val) { thread->setPC(val); } 2852683Sktlim@umich.edu void setNextPC(uint64_t val) { thread->setNextPC(val); } 2862683Sktlim@umich.edu void setNextNPC(uint64_t val) { thread->setNextNPC(val); } 287705SN/A 2882159SN/A MiscReg readMiscReg(int misc_reg) 2892159SN/A { 2902683Sktlim@umich.edu return thread->readMiscReg(misc_reg); 2912159SN/A } 292705SN/A 2932159SN/A MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) 2942159SN/A { 2952683Sktlim@umich.edu return thread->readMiscRegWithEffect(misc_reg, fault); 2962159SN/A } 2972159SN/A 2982159SN/A Fault setMiscReg(int misc_reg, const MiscReg &val) 2992159SN/A { 3002683Sktlim@umich.edu return thread->setMiscReg(misc_reg, val); 3012159SN/A } 3022159SN/A 3032159SN/A Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) 3042159SN/A { 3052683Sktlim@umich.edu return thread->setMiscRegWithEffect(misc_reg, val); 3062159SN/A } 307705SN/A 3081858SN/A#if FULL_SYSTEM 3092683Sktlim@umich.edu Fault hwrei() { return thread->hwrei(); } 3102683Sktlim@umich.edu int readIntrFlag() { return thread->readIntrFlag(); } 3112683Sktlim@umich.edu void setIntrFlag(int val) { thread->setIntrFlag(val); } 3122683Sktlim@umich.edu bool inPalMode() { return thread->inPalMode(); } 3132680Sktlim@umich.edu void ev5_trap(Fault fault) { fault->invoke(tc); } 3142683Sktlim@umich.edu bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 315705SN/A#else 3162683Sktlim@umich.edu void syscall(int64_t callnum) { thread->syscall(callnum); } 317705SN/A#endif 318705SN/A 3192683Sktlim@umich.edu bool misspeculating() { return thread->misspeculating(); } 3202680Sktlim@umich.edu ThreadContext *tcBase() { return tc; } 3212SN/A}; 3222SN/A 3232623SN/A#endif // __CPU_SIMPLE_BASE_HH__ 324