base.hh revision 2662
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272SN/A */ 282SN/A 292623SN/A#ifndef __CPU_SIMPLE_BASE_HH__ 302623SN/A#define __CPU_SIMPLE_BASE_HH__ 312SN/A 321354SN/A#include "base/statistics.hh" 331858SN/A#include "config/full_system.hh" 341717SN/A#include "cpu/base.hh" 352190SN/A#include "cpu/cpu_exec_context.hh" 361354SN/A#include "cpu/pc_event.hh" 371717SN/A#include "cpu/sampler/sampler.hh" 381354SN/A#include "cpu/static_inst.hh" 392387SN/A#include "mem/packet.hh" 402387SN/A#include "mem/port.hh" 412387SN/A#include "mem/request.hh" 4256SN/A#include "sim/eventq.hh" 432SN/A 442SN/A// forward declarations 451858SN/A#if FULL_SYSTEM 462SN/Aclass Processor; 47676SN/Aclass AlphaITB; 48676SN/Aclass AlphaDTB; 492462SN/Aclass MemObject; 502SN/A 512SN/Aclass RemoteGDB; 522SN/Aclass GDBListener; 53715SN/A 54715SN/A#else 55715SN/A 56715SN/Aclass Process; 57715SN/A 582SN/A#endif // FULL_SYSTEM 592SN/A 602190SN/Aclass ExecContext; 61237SN/Aclass Checkpoint; 622SN/A 632SN/Anamespace Trace { 642SN/A class InstRecord; 652SN/A} 662SN/A 672420SN/A 682623SN/Aclass BaseSimpleCPU : public BaseCPU 692SN/A{ 702107SN/A protected: 712107SN/A typedef TheISA::MachInst MachInst; 722159SN/A typedef TheISA::MiscReg MiscReg; 732455SN/A typedef TheISA::FloatReg FloatReg; 742455SN/A typedef TheISA::FloatRegBits FloatRegBits; 752386SN/A 762499SN/A MemObject *mem; 772386SN/A 782623SN/A protected: 792SN/A Trace::InstRecord *traceData; 801371SN/A 812SN/A public: 822SN/A void post_interrupt(int int_num, int index); 832SN/A 842SN/A void zero_fill_64(Addr addr) { 852SN/A static int warned = 0; 862SN/A if (!warned) { 872SN/A warn ("WH64 is not implemented"); 882SN/A warned = 1; 892SN/A } 902SN/A }; 912SN/A 921400SN/A public: 931400SN/A struct Params : public BaseCPU::Params 941400SN/A { 952542SN/A MemObject *mem; 961858SN/A#if FULL_SYSTEM 971400SN/A AlphaITB *itb; 981400SN/A AlphaDTB *dtb; 992SN/A#else 1001400SN/A Process *process; 1012SN/A#endif 1021400SN/A }; 1032623SN/A BaseSimpleCPU(Params *params); 1042623SN/A virtual ~BaseSimpleCPU(); 1052SN/A 1061400SN/A public: 1072SN/A // execution context 1082190SN/A CPUExecContext *cpuXC; 1092190SN/A 1102190SN/A ExecContext *xcProxy; 1112SN/A 1121858SN/A#if FULL_SYSTEM 1132SN/A Addr dbg_vtophys(Addr addr); 1142SN/A 1152SN/A bool interval_stats; 1162SN/A#endif 1172SN/A 1182SN/A // current instruction 1192SN/A MachInst inst; 1202SN/A 1212566SN/A // Static data storage 1222566SN/A TheISA::IntReg dataReg; 1232566SN/A 1241492SN/A // Pointer to the sampler that is telling us to switchover. 1251492SN/A // Used to signal the completion of the pipe drain and schedule 1261492SN/A // the next switchover 1271752SN/A Sampler *sampler; 1281492SN/A 1292107SN/A StaticInstPtr curStaticInst; 1301469SN/A 1312623SN/A void checkForInterrupts(); 1322662Sstever@eecs.umich.edu Fault setupFetchRequest(Request *req); 1332623SN/A void preExecute(); 1342623SN/A void postExecute(); 1352623SN/A void advancePC(Fault fault); 136180SN/A 137393SN/A virtual void deallocateContext(int thread_num); 138393SN/A virtual void haltContext(int thread_num); 1392SN/A 1402SN/A // statistics 141334SN/A virtual void regStats(); 142334SN/A virtual void resetStats(); 1432SN/A 1442SN/A // number of simulated instructions 1452SN/A Counter numInst; 146334SN/A Counter startNumInst; 147729SN/A Stats::Scalar<> numInsts; 148707SN/A 149707SN/A virtual Counter totalInstructions() const 150707SN/A { 151707SN/A return numInst - startNumInst; 152707SN/A } 1532SN/A 1542SN/A // number of simulated memory references 155729SN/A Stats::Scalar<> numMemRefs; 1562SN/A 157124SN/A // number of simulated loads 158124SN/A Counter numLoad; 159334SN/A Counter startNumLoad; 160124SN/A 1612SN/A // number of idle cycles 162729SN/A Stats::Average<> notIdleFraction; 163729SN/A Stats::Formula idleFraction; 1642SN/A 1652390SN/A // number of cycles stalled for I-cache responses 166729SN/A Stats::Scalar<> icacheStallCycles; 1672SN/A Counter lastIcacheStall; 1682SN/A 1692390SN/A // number of cycles stalled for I-cache retries 1702390SN/A Stats::Scalar<> icacheRetryCycles; 1712390SN/A Counter lastIcacheRetry; 1722390SN/A 1732390SN/A // number of cycles stalled for D-cache responses 174729SN/A Stats::Scalar<> dcacheStallCycles; 1752SN/A Counter lastDcacheStall; 1762SN/A 1772390SN/A // number of cycles stalled for D-cache retries 1782390SN/A Stats::Scalar<> dcacheRetryCycles; 1792390SN/A Counter lastDcacheRetry; 1802390SN/A 181217SN/A virtual void serialize(std::ostream &os); 182237SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 1832SN/A 1841371SN/A // These functions are only used in CPU models that split 1851371SN/A // effective address computation from the actual memory access. 1862623SN/A void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); } 1872623SN/A Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); } 1881371SN/A 189581SN/A void prefetch(Addr addr, unsigned flags) 1902SN/A { 1912SN/A // need to do this... 1922SN/A } 1932SN/A 194753SN/A void writeHint(Addr addr, int size, unsigned flags) 1952SN/A { 1962SN/A // need to do this... 1972SN/A } 198594SN/A 199595SN/A Fault copySrcTranslate(Addr src); 200594SN/A 201595SN/A Fault copy(Addr dest); 202705SN/A 203726SN/A // The register accessor methods provide the index of the 204726SN/A // instruction's operand (e.g., 0 or 1), not the architectural 205726SN/A // register index, to simplify the implementation of register 206726SN/A // renaming. We find the architectural register index by indexing 207726SN/A // into the instruction's own operand index table. Note that a 208726SN/A // raw pointer to the StaticInst is provided instead of a 209726SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 210726SN/A // long as these methods don't copy the pointer into any long-term 211726SN/A // storage (which is pretty hard to imagine they would have reason 212726SN/A // to do). 213705SN/A 2142107SN/A uint64_t readIntReg(const StaticInst *si, int idx) 215726SN/A { 2162190SN/A return cpuXC->readIntReg(si->srcRegIdx(idx)); 217726SN/A } 218705SN/A 2192455SN/A FloatReg readFloatReg(const StaticInst *si, int idx, int width) 220726SN/A { 221726SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2222455SN/A return cpuXC->readFloatReg(reg_idx, width); 223726SN/A } 224705SN/A 2252455SN/A FloatReg readFloatReg(const StaticInst *si, int idx) 226726SN/A { 227726SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2282455SN/A return cpuXC->readFloatReg(reg_idx); 229726SN/A } 230705SN/A 2312455SN/A FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width) 232726SN/A { 233726SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2342455SN/A return cpuXC->readFloatRegBits(reg_idx, width); 2352455SN/A } 2362455SN/A 2372455SN/A FloatRegBits readFloatRegBits(const StaticInst *si, int idx) 2382455SN/A { 2392455SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2402455SN/A return cpuXC->readFloatRegBits(reg_idx); 241726SN/A } 242705SN/A 2432107SN/A void setIntReg(const StaticInst *si, int idx, uint64_t val) 244726SN/A { 2452190SN/A cpuXC->setIntReg(si->destRegIdx(idx), val); 246726SN/A } 247705SN/A 2482455SN/A void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width) 249726SN/A { 250726SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2512455SN/A cpuXC->setFloatReg(reg_idx, val, width); 252726SN/A } 253705SN/A 2542455SN/A void setFloatReg(const StaticInst *si, int idx, FloatReg val) 255726SN/A { 256726SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2572455SN/A cpuXC->setFloatReg(reg_idx, val); 258726SN/A } 259726SN/A 2602455SN/A void setFloatRegBits(const StaticInst *si, int idx, 2612577SN/A FloatRegBits val, int width) 262726SN/A { 263726SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2642455SN/A cpuXC->setFloatRegBits(reg_idx, val, width); 2652455SN/A } 2662455SN/A 2672455SN/A void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val) 2682455SN/A { 2692455SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2702455SN/A cpuXC->setFloatRegBits(reg_idx, val); 271726SN/A } 272705SN/A 2732190SN/A uint64_t readPC() { return cpuXC->readPC(); } 2742447SN/A uint64_t readNextPC() { return cpuXC->readNextPC(); } 2752447SN/A uint64_t readNextNPC() { return cpuXC->readNextNPC(); } 2762447SN/A 2772447SN/A void setPC(uint64_t val) { cpuXC->setPC(val); } 2782190SN/A void setNextPC(uint64_t val) { cpuXC->setNextPC(val); } 2792447SN/A void setNextNPC(uint64_t val) { cpuXC->setNextNPC(val); } 280705SN/A 2812159SN/A MiscReg readMiscReg(int misc_reg) 2822159SN/A { 2832190SN/A return cpuXC->readMiscReg(misc_reg); 2842159SN/A } 285705SN/A 2862159SN/A MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) 2872159SN/A { 2882190SN/A return cpuXC->readMiscRegWithEffect(misc_reg, fault); 2892159SN/A } 2902159SN/A 2912159SN/A Fault setMiscReg(int misc_reg, const MiscReg &val) 2922159SN/A { 2932190SN/A return cpuXC->setMiscReg(misc_reg, val); 2942159SN/A } 2952159SN/A 2962159SN/A Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) 2972159SN/A { 2982190SN/A return cpuXC->setMiscRegWithEffect(misc_reg, val); 2992159SN/A } 300705SN/A 3011858SN/A#if FULL_SYSTEM 3022190SN/A Fault hwrei() { return cpuXC->hwrei(); } 3032190SN/A int readIntrFlag() { return cpuXC->readIntrFlag(); } 3042190SN/A void setIntrFlag(int val) { cpuXC->setIntrFlag(val); } 3052190SN/A bool inPalMode() { return cpuXC->inPalMode(); } 3062234SN/A void ev5_trap(Fault fault) { fault->invoke(xcProxy); } 3072190SN/A bool simPalCheck(int palFunc) { return cpuXC->simPalCheck(palFunc); } 308705SN/A#else 3092561SN/A void syscall(int64_t callnum) { cpuXC->syscall(callnum); } 310705SN/A#endif 311705SN/A 3122190SN/A bool misspeculating() { return cpuXC->misspeculating(); } 3132190SN/A ExecContext *xcBase() { return xcProxy; } 3142SN/A}; 3152SN/A 3162623SN/A#endif // __CPU_SIMPLE_BASE_HH__ 317