base.hh revision 2577
12SN/A/* 211147Smitch.hayenga@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 39920Syasuko.eckert@amd.com * All rights reserved. 47338SAli.Saidi@ARM.com * 57338SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 67338SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 77338SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 87338SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 97338SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 107338SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 117338SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 127338SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 137338SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 147338SAli.Saidi@ARM.com * this software without specific prior written permission. 151762SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272SN/A */ 282SN/A 292SN/A#ifndef __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__ 302SN/A#define __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__ 312SN/A 322SN/A#include "base/statistics.hh" 332SN/A#include "config/full_system.hh" 342SN/A#include "cpu/base.hh" 352SN/A#include "cpu/cpu_exec_context.hh" 362SN/A#include "cpu/pc_event.hh" 372SN/A#include "cpu/sampler/sampler.hh" 382SN/A#include "cpu/static_inst.hh" 392SN/A#include "mem/packet.hh" 402665Ssaidi@eecs.umich.edu#include "mem/port.hh" 412665Ssaidi@eecs.umich.edu#include "mem/request.hh" 422SN/A#include "sim/eventq.hh" 432SN/A 448779Sgblack@eecs.umich.edu// forward declarations 458779Sgblack@eecs.umich.edu#if FULL_SYSTEM 468779Sgblack@eecs.umich.educlass Processor; 472439SN/Aclass AlphaITB; 488779Sgblack@eecs.umich.educlass AlphaDTB; 498229Snate@binkert.orgclass MemObject; 506216Snate@binkert.org 51146SN/Aclass RemoteGDB; 52146SN/Aclass GDBListener; 53146SN/A 54146SN/A#else 55146SN/A 566216Snate@binkert.orgclass Process; 576658Snate@binkert.org 588229Snate@binkert.org#endif // FULL_SYSTEM 591717SN/A 608887Sgeoffrey.blake@arm.comclass ExecContext; 618887Sgeoffrey.blake@arm.comclass Checkpoint; 62146SN/A 6310061Sandreas@sandberg.pp.senamespace Trace { 641977SN/A class InstRecord; 6511147Smitch.hayenga@arm.com} 662683Sktlim@umich.edu 671717SN/A 68146SN/A// Set exactly one of these symbols to 1 to set the memory access 692683Sktlim@umich.edu// model. Probably should make these template parameters, or even 708232Snate@binkert.org// just fork the CPU models. 718232Snate@binkert.org// 728232Snate@binkert.org#define SIMPLE_CPU_MEM_TIMING 0 738779Sgblack@eecs.umich.edu#define SIMPLE_CPU_MEM_ATOMIC 0 743348Sbinkertn@umich.edu#define SIMPLE_CPU_MEM_IMMEDIATE 1 756105Ssteve.reinhardt@amd.com 766216Snate@binkert.org 772036SN/Aclass SimpleCPU : public BaseCPU 78146SN/A{ 798817Sgblack@eecs.umich.edu protected: 808793Sgblack@eecs.umich.edu typedef TheISA::MachInst MachInst; 8156SN/A typedef TheISA::MiscReg MiscReg; 8256SN/A typedef TheISA::FloatReg FloatReg; 83695SN/A typedef TheISA::FloatRegBits FloatRegBits; 842901Ssaidi@eecs.umich.edu class CpuPort : public Port 852SN/A { 862SN/A 872449SN/A SimpleCPU *cpu; 881355SN/A 895529Snate@binkert.org public: 9010061Sandreas@sandberg.pp.se 9111147Smitch.hayenga@arm.com CpuPort(SimpleCPU *_cpu) 9210061Sandreas@sandberg.pp.se : cpu(_cpu) 9311147Smitch.hayenga@arm.com { } 9411147Smitch.hayenga@arm.com 9511147Smitch.hayenga@arm.com protected: 96224SN/A 9711147Smitch.hayenga@arm.com virtual bool recvTiming(Packet &pkt); 982SN/A 9911147Smitch.hayenga@arm.com virtual Tick recvAtomic(Packet &pkt); 10011147Smitch.hayenga@arm.com 10111147Smitch.hayenga@arm.com virtual void recvFunctional(Packet &pkt); 10211147Smitch.hayenga@arm.com 10311147Smitch.hayenga@arm.com virtual void recvStatusChange(Status status); 10411147Smitch.hayenga@arm.com 10511147Smitch.hayenga@arm.com virtual Packet *recvRetry(); 10611147Smitch.hayenga@arm.com }; 10711147Smitch.hayenga@arm.com 10811147Smitch.hayenga@arm.com MemObject *mem; 10911147Smitch.hayenga@arm.com CpuPort icachePort; 11011147Smitch.hayenga@arm.com CpuPort dcachePort; 1112SN/A 1128733Sgeoffrey.blake@arm.com public: 11311147Smitch.hayenga@arm.com // main simulation loop (one cycle) 11411147Smitch.hayenga@arm.com void tick(); 11511147Smitch.hayenga@arm.com virtual void init(); 1168733Sgeoffrey.blake@arm.com 1178733Sgeoffrey.blake@arm.com private: 1188733Sgeoffrey.blake@arm.com struct TickEvent : public Event 1198733Sgeoffrey.blake@arm.com { 12011147Smitch.hayenga@arm.com SimpleCPU *cpu; 12111147Smitch.hayenga@arm.com int width; 1228733Sgeoffrey.blake@arm.com 1238733Sgeoffrey.blake@arm.com TickEvent(SimpleCPU *c, int w); 1248733Sgeoffrey.blake@arm.com void process(); 12511147Smitch.hayenga@arm.com const char *description(); 1268733Sgeoffrey.blake@arm.com }; 12711147Smitch.hayenga@arm.com 12811147Smitch.hayenga@arm.com TickEvent tickEvent; 12911147Smitch.hayenga@arm.com 13011147Smitch.hayenga@arm.com /// Schedule tick event, regardless of its current state. 1312SN/A void scheduleTickEvent(int numCycles) 13211147Smitch.hayenga@arm.com { 13311147Smitch.hayenga@arm.com if (tickEvent.squashed()) 13411147Smitch.hayenga@arm.com tickEvent.reschedule(curTick + cycles(numCycles)); 1354377Sgblack@eecs.umich.edu else if (!tickEvent.scheduled()) 13611147Smitch.hayenga@arm.com tickEvent.schedule(curTick + cycles(numCycles)); 13711147Smitch.hayenga@arm.com } 13811147Smitch.hayenga@arm.com 13911147Smitch.hayenga@arm.com /// Unschedule tick event, regardless of its current state. 14011147Smitch.hayenga@arm.com void unscheduleTickEvent() 14111147Smitch.hayenga@arm.com { 1425169Ssaidi@eecs.umich.edu if (tickEvent.scheduled()) 14311147Smitch.hayenga@arm.com tickEvent.squash(); 14411147Smitch.hayenga@arm.com } 14511147Smitch.hayenga@arm.com 14611147Smitch.hayenga@arm.com private: 14711147Smitch.hayenga@arm.com Trace::InstRecord *traceData; 14811147Smitch.hayenga@arm.com 14911147Smitch.hayenga@arm.com public: 15011147Smitch.hayenga@arm.com // 15111147Smitch.hayenga@arm.com enum Status { 15211147Smitch.hayenga@arm.com Running, 15311147Smitch.hayenga@arm.com Idle, 15411147Smitch.hayenga@arm.com IcacheRetry, 15511147Smitch.hayenga@arm.com IcacheWaitResponse, 15611147Smitch.hayenga@arm.com IcacheAccessComplete, 15711147Smitch.hayenga@arm.com DcacheRetry, 15811147Smitch.hayenga@arm.com DcacheWaitResponse, 15911147Smitch.hayenga@arm.com DcacheWaitSwitch, 16011147Smitch.hayenga@arm.com SwitchedOut 16111147Smitch.hayenga@arm.com }; 16211147Smitch.hayenga@arm.com 16311147Smitch.hayenga@arm.com private: 16411147Smitch.hayenga@arm.com Status _status; 16511147Smitch.hayenga@arm.com 16611147Smitch.hayenga@arm.com public: 16711147Smitch.hayenga@arm.com void post_interrupt(int int_num, int index); 16811147Smitch.hayenga@arm.com 16911147Smitch.hayenga@arm.com void zero_fill_64(Addr addr) { 17011147Smitch.hayenga@arm.com static int warned = 0; 17111147Smitch.hayenga@arm.com if (!warned) { 17211147Smitch.hayenga@arm.com warn ("WH64 is not implemented"); 17311147Smitch.hayenga@arm.com warned = 1; 17411147Smitch.hayenga@arm.com } 17511147Smitch.hayenga@arm.com }; 17611147Smitch.hayenga@arm.com 17711147Smitch.hayenga@arm.com public: 17811147Smitch.hayenga@arm.com struct Params : public BaseCPU::Params 17911147Smitch.hayenga@arm.com { 18011147Smitch.hayenga@arm.com int width; 18111147Smitch.hayenga@arm.com MemObject *mem; 18211147Smitch.hayenga@arm.com#if FULL_SYSTEM 18311147Smitch.hayenga@arm.com AlphaITB *itb; 18411147Smitch.hayenga@arm.com AlphaDTB *dtb; 18511147Smitch.hayenga@arm.com#else 18611147Smitch.hayenga@arm.com Process *process; 18711147Smitch.hayenga@arm.com#endif 18811147Smitch.hayenga@arm.com }; 18911147Smitch.hayenga@arm.com SimpleCPU(Params *params); 19011147Smitch.hayenga@arm.com virtual ~SimpleCPU(); 19111147Smitch.hayenga@arm.com 19211147Smitch.hayenga@arm.com public: 19311147Smitch.hayenga@arm.com // execution context 19411147Smitch.hayenga@arm.com CPUExecContext *cpuXC; 19511147Smitch.hayenga@arm.com 19611147Smitch.hayenga@arm.com ExecContext *xcProxy; 19711147Smitch.hayenga@arm.com 19811147Smitch.hayenga@arm.com void switchOut(Sampler *s); 19911147Smitch.hayenga@arm.com void takeOverFrom(BaseCPU *oldCPU); 20011147Smitch.hayenga@arm.com 20111147Smitch.hayenga@arm.com#if FULL_SYSTEM 20211147Smitch.hayenga@arm.com Addr dbg_vtophys(Addr addr); 20311147Smitch.hayenga@arm.com 20411147Smitch.hayenga@arm.com bool interval_stats; 20511147Smitch.hayenga@arm.com#endif 2062SN/A 2072SN/A // current instruction 2082623SN/A MachInst inst; 2092SN/A 2102SN/A // Static data storage 2112SN/A TheISA::IntReg dataReg; 212180SN/A 2138737Skoansin.tan@gmail.com#if SIMPLE_CPU_MEM_TIMING 214393SN/A Packet *retry_pkt; 215393SN/A#elif SIMPLE_CPU_MEM_ATOMIC || SIMPLE_CPU_MEM_IMMEDIATE 216393SN/A Request *ifetch_req; 217393SN/A Packet *ifetch_pkt; 218384SN/A Request *data_read_req; 219189SN/A Packet *data_read_pkt; 220189SN/A Request *data_write_req; 2212623SN/A Packet *data_write_pkt; 2222SN/A#endif 223729SN/A 224334SN/A // Pointer to the sampler that is telling us to switchover. 2252SN/A // Used to signal the completion of the pipe drain and schedule 2262SN/A // the next switchover 22711147Smitch.hayenga@arm.com Sampler *sampler; 22811147Smitch.hayenga@arm.com 2298834Satgutier@umich.edu StaticInstPtr curStaticInst; 23011147Smitch.hayenga@arm.com 23111147Smitch.hayenga@arm.com Status status() const { return _status; } 23211147Smitch.hayenga@arm.com 2332SN/A virtual void activateContext(int thread_num, int delay); 23411147Smitch.hayenga@arm.com virtual void suspendContext(int thread_num); 23511147Smitch.hayenga@arm.com virtual void deallocateContext(int thread_num); 23611147Smitch.hayenga@arm.com virtual void haltContext(int thread_num); 23711147Smitch.hayenga@arm.com 2387897Shestness@cs.utexas.edu // statistics 23911147Smitch.hayenga@arm.com virtual void regStats(); 24011147Smitch.hayenga@arm.com virtual void resetStats(); 24111147Smitch.hayenga@arm.com 24211147Smitch.hayenga@arm.com // number of simulated instructions 2437897Shestness@cs.utexas.edu Counter numInst; 24411147Smitch.hayenga@arm.com Counter startNumInst; 24511147Smitch.hayenga@arm.com Stats::Scalar<> numInsts; 24611147Smitch.hayenga@arm.com 24711147Smitch.hayenga@arm.com virtual Counter totalInstructions() const 2487897Shestness@cs.utexas.edu { 24911147Smitch.hayenga@arm.com return numInst - startNumInst; 25011147Smitch.hayenga@arm.com } 25111147Smitch.hayenga@arm.com 25211147Smitch.hayenga@arm.com // number of simulated memory references 2537897Shestness@cs.utexas.edu Stats::Scalar<> numMemRefs; 25411147Smitch.hayenga@arm.com 25511147Smitch.hayenga@arm.com // number of simulated loads 25611147Smitch.hayenga@arm.com Counter numLoad; 25711147Smitch.hayenga@arm.com Counter startNumLoad; 2587897Shestness@cs.utexas.edu 25911147Smitch.hayenga@arm.com // number of idle cycles 26011147Smitch.hayenga@arm.com Stats::Average<> notIdleFraction; 26111147Smitch.hayenga@arm.com Stats::Formula idleFraction; 26211147Smitch.hayenga@arm.com 2637897Shestness@cs.utexas.edu // number of cycles stalled for I-cache responses 26411147Smitch.hayenga@arm.com Stats::Scalar<> icacheStallCycles; 26511147Smitch.hayenga@arm.com Counter lastIcacheStall; 26611147Smitch.hayenga@arm.com 26711147Smitch.hayenga@arm.com // number of cycles stalled for I-cache retries 2687897Shestness@cs.utexas.edu Stats::Scalar<> icacheRetryCycles; 26911147Smitch.hayenga@arm.com Counter lastIcacheRetry; 27011147Smitch.hayenga@arm.com 27111147Smitch.hayenga@arm.com // number of cycles stalled for D-cache responses 27211147Smitch.hayenga@arm.com Stats::Scalar<> dcacheStallCycles; 2737897Shestness@cs.utexas.edu Counter lastDcacheStall; 27411147Smitch.hayenga@arm.com 27511147Smitch.hayenga@arm.com // number of cycles stalled for D-cache retries 27611147Smitch.hayenga@arm.com Stats::Scalar<> dcacheRetryCycles; 27711147Smitch.hayenga@arm.com Counter lastDcacheRetry; 2787897Shestness@cs.utexas.edu 27911147Smitch.hayenga@arm.com void sendIcacheRequest(Packet *pkt); 28011147Smitch.hayenga@arm.com void sendDcacheRequest(Packet *pkt); 28111147Smitch.hayenga@arm.com void processResponse(Packet &response); 28211147Smitch.hayenga@arm.com 2837897Shestness@cs.utexas.edu Packet * processRetry(); 28411147Smitch.hayenga@arm.com void recvStatusChange(Port::Status status) {} 28511147Smitch.hayenga@arm.com 28611147Smitch.hayenga@arm.com virtual void serialize(std::ostream &os); 28711147Smitch.hayenga@arm.com virtual void unserialize(Checkpoint *cp, const std::string §ion); 2889920Syasuko.eckert@amd.com 28911147Smitch.hayenga@arm.com template <class T> 29011147Smitch.hayenga@arm.com Fault read(Addr addr, T &data, unsigned flags); 29111147Smitch.hayenga@arm.com 29211147Smitch.hayenga@arm.com template <class T> 2939920Syasuko.eckert@amd.com Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 29411147Smitch.hayenga@arm.com 29511147Smitch.hayenga@arm.com // These functions are only used in CPU models that split 29611147Smitch.hayenga@arm.com // effective address computation from the actual memory access. 29711147Smitch.hayenga@arm.com void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); } 29811147Smitch.hayenga@arm.com Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); } 2997897Shestness@cs.utexas.edu 30011147Smitch.hayenga@arm.com void prefetch(Addr addr, unsigned flags) 30111147Smitch.hayenga@arm.com { 30211147Smitch.hayenga@arm.com // need to do this... 30311147Smitch.hayenga@arm.com } 30411147Smitch.hayenga@arm.com 3057897Shestness@cs.utexas.edu void writeHint(Addr addr, int size, unsigned flags) 30611147Smitch.hayenga@arm.com { 30711147Smitch.hayenga@arm.com // need to do this... 30811147Smitch.hayenga@arm.com } 30911147Smitch.hayenga@arm.com 3102SN/A Fault copySrcTranslate(Addr src); 31111147Smitch.hayenga@arm.com 31211147Smitch.hayenga@arm.com Fault copy(Addr dest); 31311147Smitch.hayenga@arm.com 31411147Smitch.hayenga@arm.com // The register accessor methods provide the index of the 3151001SN/A // instruction's operand (e.g., 0 or 1), not the architectural 31611147Smitch.hayenga@arm.com // register index, to simplify the implementation of register 31711147Smitch.hayenga@arm.com // renaming. We find the architectural register index by indexing 31811147Smitch.hayenga@arm.com // into the instruction's own operand index table. Note that a 31911147Smitch.hayenga@arm.com // raw pointer to the StaticInst is provided instead of a 3202SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 32111147Smitch.hayenga@arm.com // long as these methods don't copy the pointer into any long-term 32211147Smitch.hayenga@arm.com // storage (which is pretty hard to imagine they would have reason 32311147Smitch.hayenga@arm.com // to do). 32411147Smitch.hayenga@arm.com 3257897Shestness@cs.utexas.edu uint64_t readIntReg(const StaticInst *si, int idx) 32611147Smitch.hayenga@arm.com { 32711147Smitch.hayenga@arm.com return cpuXC->readIntReg(si->srcRegIdx(idx)); 32811147Smitch.hayenga@arm.com } 32911147Smitch.hayenga@arm.com 3307897Shestness@cs.utexas.edu FloatReg readFloatReg(const StaticInst *si, int idx, int width) 33111147Smitch.hayenga@arm.com { 33211147Smitch.hayenga@arm.com int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 33311147Smitch.hayenga@arm.com return cpuXC->readFloatReg(reg_idx, width); 33411147Smitch.hayenga@arm.com } 3352SN/A 33611147Smitch.hayenga@arm.com FloatReg readFloatReg(const StaticInst *si, int idx) 33711147Smitch.hayenga@arm.com { 33811147Smitch.hayenga@arm.com int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 33911147Smitch.hayenga@arm.com return cpuXC->readFloatReg(reg_idx); 3402SN/A } 34111147Smitch.hayenga@arm.com 34211147Smitch.hayenga@arm.com FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width) 34311147Smitch.hayenga@arm.com { 34411147Smitch.hayenga@arm.com int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 34511147Smitch.hayenga@arm.com return cpuXC->readFloatRegBits(reg_idx, width); 34611147Smitch.hayenga@arm.com } 34711147Smitch.hayenga@arm.com 34811147Smitch.hayenga@arm.com FloatRegBits readFloatRegBits(const StaticInst *si, int idx) 34911147Smitch.hayenga@arm.com { 35011147Smitch.hayenga@arm.com int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 35111147Smitch.hayenga@arm.com return cpuXC->readFloatRegBits(reg_idx); 35211147Smitch.hayenga@arm.com } 35311147Smitch.hayenga@arm.com 35411147Smitch.hayenga@arm.com void setIntReg(const StaticInst *si, int idx, uint64_t val) 35511147Smitch.hayenga@arm.com { 35611147Smitch.hayenga@arm.com cpuXC->setIntReg(si->destRegIdx(idx), val); 35711147Smitch.hayenga@arm.com } 35811147Smitch.hayenga@arm.com 35911147Smitch.hayenga@arm.com void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width) 36011147Smitch.hayenga@arm.com { 36111147Smitch.hayenga@arm.com int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 36211147Smitch.hayenga@arm.com cpuXC->setFloatReg(reg_idx, val, width); 36311147Smitch.hayenga@arm.com } 36411147Smitch.hayenga@arm.com 36511147Smitch.hayenga@arm.com void setFloatReg(const StaticInst *si, int idx, FloatReg val) 36611147Smitch.hayenga@arm.com { 36711147Smitch.hayenga@arm.com int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 36811147Smitch.hayenga@arm.com cpuXC->setFloatReg(reg_idx, val); 36911147Smitch.hayenga@arm.com } 37011147Smitch.hayenga@arm.com 37111147Smitch.hayenga@arm.com void setFloatRegBits(const StaticInst *si, int idx, 37211147Smitch.hayenga@arm.com FloatRegBits val, int width) 37311147Smitch.hayenga@arm.com { 37411147Smitch.hayenga@arm.com int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 37511147Smitch.hayenga@arm.com cpuXC->setFloatRegBits(reg_idx, val, width); 37611147Smitch.hayenga@arm.com } 37711147Smitch.hayenga@arm.com 37811147Smitch.hayenga@arm.com void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val) 37911147Smitch.hayenga@arm.com { 38011147Smitch.hayenga@arm.com int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 38111147Smitch.hayenga@arm.com cpuXC->setFloatRegBits(reg_idx, val); 38210193SCurtis.Dunham@arm.com } 3832SN/A 3842SN/A uint64_t readPC() { return cpuXC->readPC(); } 3852SN/A uint64_t readNextPC() { return cpuXC->readNextPC(); } 3862623SN/A uint64_t readNextNPC() { return cpuXC->readNextNPC(); } 387334SN/A 38811147Smitch.hayenga@arm.com void setPC(uint64_t val) { cpuXC->setPC(val); } 38911147Smitch.hayenga@arm.com void setNextPC(uint64_t val) { cpuXC->setNextPC(val); } 39011147Smitch.hayenga@arm.com void setNextNPC(uint64_t val) { cpuXC->setNextNPC(val); } 391334SN/A 392334SN/A MiscReg readMiscReg(int misc_reg) 393334SN/A { 39410905Sandreas.sandberg@arm.com return cpuXC->readMiscReg(misc_reg); 3952SN/A } 3969448SAndreas.Sandberg@ARM.com 3979448SAndreas.Sandberg@ARM.com MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) 39811147Smitch.hayenga@arm.com { 3992SN/A return cpuXC->readMiscRegWithEffect(misc_reg, fault); 4002SN/A } 4012SN/A 40210905Sandreas.sandberg@arm.com Fault setMiscReg(int misc_reg, const MiscReg &val) 4032SN/A { 40411147Smitch.hayenga@arm.com return cpuXC->setMiscReg(misc_reg, val); 4052SN/A } 4062SN/A 4072SN/A Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) 4086221Snate@binkert.org { 4092SN/A return cpuXC->setMiscRegWithEffect(misc_reg, val); 4102SN/A } 4112SN/A 4122SN/A#if FULL_SYSTEM 4132623SN/A Fault hwrei() { return cpuXC->hwrei(); } 4142SN/A int readIntrFlag() { return cpuXC->readIntrFlag(); } 41511147Smitch.hayenga@arm.com void setIntrFlag(int val) { cpuXC->setIntrFlag(val); } 4162SN/A bool inPalMode() { return cpuXC->inPalMode(); } 4172SN/A void ev5_trap(Fault fault) { fault->invoke(xcProxy); } 4182SN/A bool simPalCheck(int palFunc) { return cpuXC->simPalCheck(palFunc); } 41911151Smitch.hayenga@arm.com#else 4202SN/A void syscall(int64_t callnum) { cpuXC->syscall(callnum); } 42111151Smitch.hayenga@arm.com#endif 42211151Smitch.hayenga@arm.com 42311151Smitch.hayenga@arm.com bool misspeculating() { return cpuXC->misspeculating(); } 42411151Smitch.hayenga@arm.com ExecContext *xcBase() { return xcProxy; } 42511151Smitch.hayenga@arm.com}; 42611147Smitch.hayenga@arm.com 4272SN/A#endif // __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__ 4282SN/A