base.hh revision 2386
110614Skanishk.sugand@arm.com/* 210995Sandreas.sandberg@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 310614Skanishk.sugand@arm.com * All rights reserved. 410614Skanishk.sugand@arm.com * 510614Skanishk.sugand@arm.com * Redistribution and use in source and binary forms, with or without 610614Skanishk.sugand@arm.com * modification, are permitted provided that the following conditions are 710614Skanishk.sugand@arm.com * met: redistributions of source code must retain the above copyright 810614Skanishk.sugand@arm.com * notice, this list of conditions and the following disclaimer; 910614Skanishk.sugand@arm.com * redistributions in binary form must reproduce the above copyright 1010614Skanishk.sugand@arm.com * notice, this list of conditions and the following disclaimer in the 1110614Skanishk.sugand@arm.com * documentation and/or other materials provided with the distribution; 1210614Skanishk.sugand@arm.com * neither the name of the copyright holders nor the names of its 1310614Skanishk.sugand@arm.com * contributors may be used to endorse or promote products derived from 1410614Skanishk.sugand@arm.com * this software without specific prior written permission. 1510614Skanishk.sugand@arm.com * 1610614Skanishk.sugand@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710614Skanishk.sugand@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810614Skanishk.sugand@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910614Skanishk.sugand@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010614Skanishk.sugand@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110614Skanishk.sugand@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210614Skanishk.sugand@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310614Skanishk.sugand@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410614Skanishk.sugand@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510614Skanishk.sugand@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610614Skanishk.sugand@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710614Skanishk.sugand@arm.com */ 2810614Skanishk.sugand@arm.com 2910614Skanishk.sugand@arm.com#ifndef __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__ 3010614Skanishk.sugand@arm.com#define __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__ 3110614Skanishk.sugand@arm.com 3210614Skanishk.sugand@arm.com#include "base/statistics.hh" 3310614Skanishk.sugand@arm.com#include "config/full_system.hh" 3410614Skanishk.sugand@arm.com#include "cpu/base.hh" 3510614Skanishk.sugand@arm.com#include "cpu/exec_context.hh" 3610614Skanishk.sugand@arm.com#include "cpu/pc_event.hh" 3710614Skanishk.sugand@arm.com#include "cpu/sampler/sampler.hh" 3810614Skanishk.sugand@arm.com#include "cpu/static_inst.hh" 3910614Skanishk.sugand@arm.com#include "sim/eventq.hh" 4010995Sandreas.sandberg@arm.com 4110995Sandreas.sandberg@arm.com// forward declarations 4210995Sandreas.sandberg@arm.com#if FULL_SYSTEM 4310614Skanishk.sugand@arm.comclass Processor; 4410614Skanishk.sugand@arm.comclass AlphaITB; 4510614Skanishk.sugand@arm.comclass AlphaDTB; 4610614Skanishk.sugand@arm.comclass PhysicalMemory; 4710995Sandreas.sandberg@arm.com 4810995Sandreas.sandberg@arm.comclass RemoteGDB; 4910995Sandreas.sandberg@arm.comclass GDBListener; 5010614Skanishk.sugand@arm.com 5110614Skanishk.sugand@arm.com#else 5210614Skanishk.sugand@arm.com 5310614Skanishk.sugand@arm.comclass Process; 5410614Skanishk.sugand@arm.com 5510614Skanishk.sugand@arm.com#endif // FULL_SYSTEM 5610614Skanishk.sugand@arm.com 5710614Skanishk.sugand@arm.comclass MemInterface; 5810614Skanishk.sugand@arm.comclass Checkpoint; 5910614Skanishk.sugand@arm.com 6010614Skanishk.sugand@arm.comnamespace Trace { 6110614Skanishk.sugand@arm.com class InstRecord; 6210614Skanishk.sugand@arm.com} 6310614Skanishk.sugand@arm.com 6410614Skanishk.sugand@arm.comclass SimpleCPU : public BaseCPU 6510614Skanishk.sugand@arm.com{ 6610614Skanishk.sugand@arm.com class CpuPort : public Port 6710614Skanishk.sugand@arm.com { 6810614Skanishk.sugand@arm.com 6910614Skanishk.sugand@arm.com SimpleCPU *cpu; 7010614Skanishk.sugand@arm.com 7110614Skanishk.sugand@arm.com public: 7210614Skanishk.sugand@arm.com 7310614Skanishk.sugand@arm.com CpuPort(SimpleCPU *_cpu) 7410614Skanishk.sugand@arm.com : cpu(_cpu) 7510614Skanishk.sugand@arm.com { } 7610614Skanishk.sugand@arm.com 7710614Skanishk.sugand@arm.com protected: 7810614Skanishk.sugand@arm.com 7910614Skanishk.sugand@arm.com virtual bool recvTiming(Packet &pkt) 8010614Skanishk.sugand@arm.com { return cpu->recvTiming(pkt); } 8110614Skanishk.sugand@arm.com 8210614Skanishk.sugand@arm.com virtual Tick recvAtomic(Packet &pkt) 8310614Skanishk.sugand@arm.com { return cpu->recvAtomic(pkt); } 8410614Skanishk.sugand@arm.com 8510614Skanishk.sugand@arm.com virtual void recvFunctional(Packet &pkt) 8610614Skanishk.sugand@arm.com { cpu->recvFunctional(pkt); } 8710614Skanishk.sugand@arm.com 8810614Skanishk.sugand@arm.com virtual void recvStatusChange(Status status) 8910614Skanishk.sugand@arm.com { cpu->recvStatusChange(status); } 9010614Skanishk.sugand@arm.com 9110614Skanishk.sugand@arm.com }; 9210614Skanishk.sugand@arm.com 9310614Skanishk.sugand@arm.com CpuPort icache_port; 9410614Skanishk.sugand@arm.com CpuPort dcache_port; 9510614Skanishk.sugand@arm.com 9610614Skanishk.sugand@arm.com bool recvTiming(Packet &pkt); 9710614Skanishk.sugand@arm.com Tick recvAtomic(Packet &pkt); 9810614Skanishk.sugand@arm.com void recvFunctional(Packet &pkt); 9910614Skanishk.sugand@arm.com 10010614Skanishk.sugand@arm.com public: 10110614Skanishk.sugand@arm.com // main simulation loop (one cycle) 10210614Skanishk.sugand@arm.com void tick(); 10310614Skanishk.sugand@arm.com 10410614Skanishk.sugand@arm.com private: 10510614Skanishk.sugand@arm.com struct TickEvent : public Event 10610614Skanishk.sugand@arm.com { 10710614Skanishk.sugand@arm.com SimpleCPU *cpu; 10810614Skanishk.sugand@arm.com int width; 10910614Skanishk.sugand@arm.com 11010614Skanishk.sugand@arm.com TickEvent(SimpleCPU *c, int w); 11110614Skanishk.sugand@arm.com void process(); 11210614Skanishk.sugand@arm.com const char *description(); 11310614Skanishk.sugand@arm.com }; 11410614Skanishk.sugand@arm.com 11510614Skanishk.sugand@arm.com TickEvent tickEvent; 11610614Skanishk.sugand@arm.com 11710614Skanishk.sugand@arm.com /// Schedule tick event, regardless of its current state. 11810614Skanishk.sugand@arm.com void scheduleTickEvent(int numCycles) 11910614Skanishk.sugand@arm.com { 12010614Skanishk.sugand@arm.com if (tickEvent.squashed()) 12110614Skanishk.sugand@arm.com tickEvent.reschedule(curTick + cycles(numCycles)); 12210614Skanishk.sugand@arm.com else if (!tickEvent.scheduled()) 12310614Skanishk.sugand@arm.com tickEvent.schedule(curTick + cycles(numCycles)); 12410614Skanishk.sugand@arm.com } 12510614Skanishk.sugand@arm.com 12610614Skanishk.sugand@arm.com /// Unschedule tick event, regardless of its current state. 12710614Skanishk.sugand@arm.com void unscheduleTickEvent() 12810614Skanishk.sugand@arm.com { 12910614Skanishk.sugand@arm.com if (tickEvent.scheduled()) 13010614Skanishk.sugand@arm.com tickEvent.squash(); 13110614Skanishk.sugand@arm.com } 13210614Skanishk.sugand@arm.com 13310614Skanishk.sugand@arm.com private: 13410614Skanishk.sugand@arm.com Trace::InstRecord *traceData; 13510614Skanishk.sugand@arm.com 13610614Skanishk.sugand@arm.com public: 13710614Skanishk.sugand@arm.com // 13810614Skanishk.sugand@arm.com enum Status { 13910614Skanishk.sugand@arm.com Running, 14010614Skanishk.sugand@arm.com Idle, 14110614Skanishk.sugand@arm.com IcacheMissStall, 14210614Skanishk.sugand@arm.com IcacheMissComplete, 14310614Skanishk.sugand@arm.com DcacheMissStall, 14410614Skanishk.sugand@arm.com DcacheMissSwitch, 14510614Skanishk.sugand@arm.com SwitchedOut 14610614Skanishk.sugand@arm.com }; 14710614Skanishk.sugand@arm.com 14810614Skanishk.sugand@arm.com private: 14910614Skanishk.sugand@arm.com Status _status; 15010614Skanishk.sugand@arm.com 15110614Skanishk.sugand@arm.com public: 15210614Skanishk.sugand@arm.com void post_interrupt(int int_num, int index); 15310614Skanishk.sugand@arm.com 15410614Skanishk.sugand@arm.com void zero_fill_64(Addr addr) { 15510614Skanishk.sugand@arm.com static int warned = 0; 15610614Skanishk.sugand@arm.com if (!warned) { 15710614Skanishk.sugand@arm.com warn ("WH64 is not implemented"); 15810614Skanishk.sugand@arm.com warned = 1; 15910614Skanishk.sugand@arm.com } 16010614Skanishk.sugand@arm.com }; 16110614Skanishk.sugand@arm.com 16210614Skanishk.sugand@arm.com public: 16310614Skanishk.sugand@arm.com struct Params : public BaseCPU::Params 16410614Skanishk.sugand@arm.com { 16510614Skanishk.sugand@arm.com MemInterface *icache_interface; 16610614Skanishk.sugand@arm.com MemInterface *dcache_interface; 16710614Skanishk.sugand@arm.com int width; 16810614Skanishk.sugand@arm.com#if FULL_SYSTEM 16910614Skanishk.sugand@arm.com AlphaITB *itb; 17010614Skanishk.sugand@arm.com AlphaDTB *dtb; 17110614Skanishk.sugand@arm.com FunctionalMemory *mem; 17210614Skanishk.sugand@arm.com#else 17310614Skanishk.sugand@arm.com Process *process; 17410614Skanishk.sugand@arm.com#endif 17510614Skanishk.sugand@arm.com }; 17610614Skanishk.sugand@arm.com SimpleCPU(Params *params); 17710614Skanishk.sugand@arm.com virtual ~SimpleCPU(); 17810614Skanishk.sugand@arm.com 17910614Skanishk.sugand@arm.com public: 18010614Skanishk.sugand@arm.com // execution context 18110614Skanishk.sugand@arm.com ExecContext *xc; 18210614Skanishk.sugand@arm.com 18310614Skanishk.sugand@arm.com void switchOut(Sampler *s); 18410614Skanishk.sugand@arm.com void takeOverFrom(BaseCPU *oldCPU); 18510614Skanishk.sugand@arm.com 18610614Skanishk.sugand@arm.com#if FULL_SYSTEM 18710614Skanishk.sugand@arm.com Addr dbg_vtophys(Addr addr); 18810614Skanishk.sugand@arm.com 18910614Skanishk.sugand@arm.com bool interval_stats; 19010614Skanishk.sugand@arm.com#endif 19110614Skanishk.sugand@arm.com 19210614Skanishk.sugand@arm.com // L1 instruction cache 19310614Skanishk.sugand@arm.com MemInterface *icacheInterface; 19410614Skanishk.sugand@arm.com 19510614Skanishk.sugand@arm.com // L1 data cache 19610614Skanishk.sugand@arm.com MemInterface *dcacheInterface; 19710614Skanishk.sugand@arm.com 19810614Skanishk.sugand@arm.com // current instruction 19910614Skanishk.sugand@arm.com MachInst inst; 20010614Skanishk.sugand@arm.com 20110614Skanishk.sugand@arm.com // Refcounted pointer to the one memory request. 20210614Skanishk.sugand@arm.com MemReqPtr memReq; 20310614Skanishk.sugand@arm.com 20410614Skanishk.sugand@arm.com // Pointer to the sampler that is telling us to switchover. 20510614Skanishk.sugand@arm.com // Used to signal the completion of the pipe drain and schedule 20610614Skanishk.sugand@arm.com // the next switchover 20710614Skanishk.sugand@arm.com Sampler *sampler; 20810614Skanishk.sugand@arm.com 20910614Skanishk.sugand@arm.com StaticInstPtr<TheISA> curStaticInst; 21010614Skanishk.sugand@arm.com 21110614Skanishk.sugand@arm.com class CacheCompletionEvent : public Event 21210614Skanishk.sugand@arm.com { 21310614Skanishk.sugand@arm.com private: 21410614Skanishk.sugand@arm.com SimpleCPU *cpu; 21510614Skanishk.sugand@arm.com 21610614Skanishk.sugand@arm.com public: 21710614Skanishk.sugand@arm.com CacheCompletionEvent(SimpleCPU *_cpu); 21810614Skanishk.sugand@arm.com 21911321Ssteve.reinhardt@amd.com virtual void process(); 22010614Skanishk.sugand@arm.com virtual const char *description(); 22110614Skanishk.sugand@arm.com }; 22210614Skanishk.sugand@arm.com 22310614Skanishk.sugand@arm.com CacheCompletionEvent cacheCompletionEvent; 22410614Skanishk.sugand@arm.com 22511321Ssteve.reinhardt@amd.com Status status() const { return _status; } 22610614Skanishk.sugand@arm.com 22710614Skanishk.sugand@arm.com virtual void activateContext(int thread_num, int delay); 22810614Skanishk.sugand@arm.com virtual void suspendContext(int thread_num); 22910614Skanishk.sugand@arm.com virtual void deallocateContext(int thread_num); 23010614Skanishk.sugand@arm.com virtual void haltContext(int thread_num); 23110614Skanishk.sugand@arm.com 23210614Skanishk.sugand@arm.com // statistics 23310614Skanishk.sugand@arm.com virtual void regStats(); 23410614Skanishk.sugand@arm.com virtual void resetStats(); 23510614Skanishk.sugand@arm.com 23610614Skanishk.sugand@arm.com // number of simulated instructions 23710614Skanishk.sugand@arm.com Counter numInst; 23810614Skanishk.sugand@arm.com Counter startNumInst; 23910614Skanishk.sugand@arm.com Stats::Scalar<> numInsts; 24010614Skanishk.sugand@arm.com 24110614Skanishk.sugand@arm.com virtual Counter totalInstructions() const 24210614Skanishk.sugand@arm.com { 24310614Skanishk.sugand@arm.com return numInst - startNumInst; 24410614Skanishk.sugand@arm.com } 24510614Skanishk.sugand@arm.com 24610614Skanishk.sugand@arm.com // number of simulated memory references 24710614Skanishk.sugand@arm.com Stats::Scalar<> numMemRefs; 24810614Skanishk.sugand@arm.com 24910614Skanishk.sugand@arm.com // number of simulated loads 25010614Skanishk.sugand@arm.com Counter numLoad; 25110614Skanishk.sugand@arm.com Counter startNumLoad; 25210614Skanishk.sugand@arm.com 25310614Skanishk.sugand@arm.com // number of idle cycles 25410614Skanishk.sugand@arm.com Stats::Average<> notIdleFraction; 25510614Skanishk.sugand@arm.com Stats::Formula idleFraction; 25610614Skanishk.sugand@arm.com 25710614Skanishk.sugand@arm.com // number of cycles stalled for I-cache misses 25810614Skanishk.sugand@arm.com Stats::Scalar<> icacheStallCycles; 25910614Skanishk.sugand@arm.com Counter lastIcacheStall; 26010614Skanishk.sugand@arm.com 26110614Skanishk.sugand@arm.com // number of cycles stalled for D-cache misses 26210614Skanishk.sugand@arm.com Stats::Scalar<> dcacheStallCycles; 26310614Skanishk.sugand@arm.com Counter lastDcacheStall; 26410614Skanishk.sugand@arm.com 26510614Skanishk.sugand@arm.com void processCacheCompletion(); 26610614Skanishk.sugand@arm.com 26710614Skanishk.sugand@arm.com virtual void serialize(std::ostream &os); 26810614Skanishk.sugand@arm.com virtual void unserialize(Checkpoint *cp, const std::string §ion); 26910614Skanishk.sugand@arm.com 27010614Skanishk.sugand@arm.com template <class T> 27110614Skanishk.sugand@arm.com Fault read(Addr addr, T &data, unsigned flags); 27210614Skanishk.sugand@arm.com 27310614Skanishk.sugand@arm.com template <class T> 27410614Skanishk.sugand@arm.com Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 27510614Skanishk.sugand@arm.com 27610614Skanishk.sugand@arm.com // These functions are only used in CPU models that split 27710614Skanishk.sugand@arm.com // effective address computation from the actual memory access. 27810614Skanishk.sugand@arm.com void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); } 27910614Skanishk.sugand@arm.com Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); } 28010614Skanishk.sugand@arm.com 28110614Skanishk.sugand@arm.com void prefetch(Addr addr, unsigned flags) 28210614Skanishk.sugand@arm.com { 28310614Skanishk.sugand@arm.com // need to do this... 28410614Skanishk.sugand@arm.com } 28510614Skanishk.sugand@arm.com 28610614Skanishk.sugand@arm.com void writeHint(Addr addr, int size, unsigned flags) 28710614Skanishk.sugand@arm.com { 28810614Skanishk.sugand@arm.com // need to do this... 28910614Skanishk.sugand@arm.com } 29010614Skanishk.sugand@arm.com 29110614Skanishk.sugand@arm.com Fault copySrcTranslate(Addr src); 29210614Skanishk.sugand@arm.com 29310614Skanishk.sugand@arm.com Fault copy(Addr dest); 29410614Skanishk.sugand@arm.com 29510614Skanishk.sugand@arm.com // The register accessor methods provide the index of the 29610614Skanishk.sugand@arm.com // instruction's operand (e.g., 0 or 1), not the architectural 29710614Skanishk.sugand@arm.com // register index, to simplify the implementation of register 29810614Skanishk.sugand@arm.com // renaming. We find the architectural register index by indexing 29910614Skanishk.sugand@arm.com // into the instruction's own operand index table. Note that a 30010614Skanishk.sugand@arm.com // raw pointer to the StaticInst is provided instead of a 30110614Skanishk.sugand@arm.com // ref-counted StaticInstPtr to redice overhead. This is fine as 30210614Skanishk.sugand@arm.com // long as these methods don't copy the pointer into any long-term 30310614Skanishk.sugand@arm.com // storage (which is pretty hard to imagine they would have reason 30410614Skanishk.sugand@arm.com // to do). 30510614Skanishk.sugand@arm.com 30610614Skanishk.sugand@arm.com uint64_t readIntReg(const StaticInst<TheISA> *si, int idx) 30710614Skanishk.sugand@arm.com { 30810614Skanishk.sugand@arm.com return xc->readIntReg(si->srcRegIdx(idx)); 30910614Skanishk.sugand@arm.com } 31010614Skanishk.sugand@arm.com 31110614Skanishk.sugand@arm.com float readFloatRegSingle(const StaticInst<TheISA> *si, int idx) 31210614Skanishk.sugand@arm.com { 31310614Skanishk.sugand@arm.com int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 31410614Skanishk.sugand@arm.com return xc->readFloatRegSingle(reg_idx); 31510614Skanishk.sugand@arm.com } 31610614Skanishk.sugand@arm.com 31710614Skanishk.sugand@arm.com double readFloatRegDouble(const StaticInst<TheISA> *si, int idx) 31810614Skanishk.sugand@arm.com { 31910614Skanishk.sugand@arm.com int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 32010614Skanishk.sugand@arm.com return xc->readFloatRegDouble(reg_idx); 32110614Skanishk.sugand@arm.com } 32210614Skanishk.sugand@arm.com 32310614Skanishk.sugand@arm.com uint64_t readFloatRegInt(const StaticInst<TheISA> *si, int idx) 32410614Skanishk.sugand@arm.com { 32510614Skanishk.sugand@arm.com int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 32610614Skanishk.sugand@arm.com return xc->readFloatRegInt(reg_idx); 32710614Skanishk.sugand@arm.com } 32810614Skanishk.sugand@arm.com 32910614Skanishk.sugand@arm.com void setIntReg(const StaticInst<TheISA> *si, int idx, uint64_t val) 33010614Skanishk.sugand@arm.com { 33110614Skanishk.sugand@arm.com xc->setIntReg(si->destRegIdx(idx), val); 33210614Skanishk.sugand@arm.com } 33310614Skanishk.sugand@arm.com 33410614Skanishk.sugand@arm.com void setFloatRegSingle(const StaticInst<TheISA> *si, int idx, float val) 33510614Skanishk.sugand@arm.com { 33610614Skanishk.sugand@arm.com int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 33710614Skanishk.sugand@arm.com xc->setFloatRegSingle(reg_idx, val); 33810614Skanishk.sugand@arm.com } 33910614Skanishk.sugand@arm.com 34010614Skanishk.sugand@arm.com void setFloatRegDouble(const StaticInst<TheISA> *si, int idx, double val) 34110614Skanishk.sugand@arm.com { 34210614Skanishk.sugand@arm.com int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 34310614Skanishk.sugand@arm.com xc->setFloatRegDouble(reg_idx, val); 34410614Skanishk.sugand@arm.com } 34510614Skanishk.sugand@arm.com 34610614Skanishk.sugand@arm.com void setFloatRegInt(const StaticInst<TheISA> *si, int idx, uint64_t val) 34710614Skanishk.sugand@arm.com { 34810614Skanishk.sugand@arm.com int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 34910614Skanishk.sugand@arm.com xc->setFloatRegInt(reg_idx, val); 35010614Skanishk.sugand@arm.com } 35110614Skanishk.sugand@arm.com 35210614Skanishk.sugand@arm.com uint64_t readPC() { return xc->readPC(); } 35310614Skanishk.sugand@arm.com void setNextPC(uint64_t val) { xc->setNextPC(val); } 35410614Skanishk.sugand@arm.com 35510614Skanishk.sugand@arm.com uint64_t readUniq() { return xc->readUniq(); } 35610614Skanishk.sugand@arm.com void setUniq(uint64_t val) { xc->setUniq(val); } 35710614Skanishk.sugand@arm.com 35810614Skanishk.sugand@arm.com uint64_t readFpcr() { return xc->readFpcr(); } 35910614Skanishk.sugand@arm.com void setFpcr(uint64_t val) { xc->setFpcr(val); } 36010614Skanishk.sugand@arm.com 36110614Skanishk.sugand@arm.com#if FULL_SYSTEM 36210614Skanishk.sugand@arm.com uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); } 36310614Skanishk.sugand@arm.com Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); } 36410614Skanishk.sugand@arm.com Fault hwrei() { return xc->hwrei(); } 36510614Skanishk.sugand@arm.com int readIntrFlag() { return xc->readIntrFlag(); } 36610614Skanishk.sugand@arm.com void setIntrFlag(int val) { xc->setIntrFlag(val); } 36710614Skanishk.sugand@arm.com bool inPalMode() { return xc->inPalMode(); } 36810614Skanishk.sugand@arm.com void ev5_trap(Fault fault) { xc->ev5_trap(fault); } 36910614Skanishk.sugand@arm.com bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); } 37010614Skanishk.sugand@arm.com#else 37110614Skanishk.sugand@arm.com void syscall() { xc->syscall(); } 37210614Skanishk.sugand@arm.com#endif 37310614Skanishk.sugand@arm.com 37410614Skanishk.sugand@arm.com bool misspeculating() { return xc->misspeculating(); } 37510614Skanishk.sugand@arm.com ExecContext *xcBase() { return xc; } 37610614Skanishk.sugand@arm.com}; 37710614Skanishk.sugand@arm.com 37810614Skanishk.sugand@arm.com#endif // __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__ 37910614Skanishk.sugand@arm.com