base.hh revision 2190
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu */ 282665Ssaidi@eecs.umich.edu 292665Ssaidi@eecs.umich.edu#ifndef __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__ 302665Ssaidi@eecs.umich.edu#define __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__ 312SN/A 322SN/A#include "base/statistics.hh" 332623SN/A#include "config/full_system.hh" 342623SN/A#include "cpu/base.hh" 352SN/A#include "cpu/cpu_exec_context.hh" 364182Sgblack@eecs.umich.edu#include "cpu/pc_event.hh" 371354SN/A#include "cpu/sampler/sampler.hh" 381858SN/A#include "cpu/static_inst.hh" 391717SN/A#include "sim/eventq.hh" 402683Sktlim@umich.edu 411354SN/A// forward declarations 421354SN/A#if FULL_SYSTEM 432387SN/Aclass Processor; 442387SN/Aclass AlphaITB; 452387SN/Aclass AlphaDTB; 4656SN/Aclass PhysicalMemory; 472SN/A 482SN/Aclass RemoteGDB; 491858SN/Aclass GDBListener; 502SN/A 513453Sgblack@eecs.umich.edu#else 523453Sgblack@eecs.umich.edu 533453Sgblack@eecs.umich.educlass Process; 543453Sgblack@eecs.umich.edu 553453Sgblack@eecs.umich.edu#endif // FULL_SYSTEM 562462SN/A 572SN/Aclass ExecContext; 58715SN/Aclass MemInterface; 59715SN/Aclass Checkpoint; 60715SN/A 61715SN/Anamespace Trace { 622SN/A class InstRecord; 632SN/A} 643960Sgblack@eecs.umich.edu 653960Sgblack@eecs.umich.educlass SimpleCPU : public BaseCPU 663960Sgblack@eecs.umich.edu{ 674182Sgblack@eecs.umich.edu protected: 684182Sgblack@eecs.umich.edu typedef TheISA::MachInst MachInst; 694182Sgblack@eecs.umich.edu typedef TheISA::MiscReg MiscReg; 704182Sgblack@eecs.umich.edu public: 712680Sktlim@umich.edu // main simulation loop (one cycle) 72237SN/A void tick(); 732SN/A virtual void init(); 742SN/A 752SN/A private: 762SN/A struct TickEvent : public Event 772SN/A { 782420SN/A SimpleCPU *cpu; 792623SN/A int width; 802SN/A 812107SN/A TickEvent(SimpleCPU *c, int w); 822159SN/A void process(); 832455SN/A const char *description(); 842455SN/A }; 852386SN/A 862623SN/A TickEvent tickEvent; 872SN/A 881371SN/A /// Schedule tick event, regardless of its current state. 892SN/A void scheduleTickEvent(int numCycles) 902SN/A { 912SN/A if (tickEvent.squashed()) 922SN/A tickEvent.reschedule(curTick + cycles(numCycles)); 932SN/A else if (!tickEvent.scheduled()) 942SN/A tickEvent.schedule(curTick + cycles(numCycles)); 952SN/A } 962SN/A 972SN/A /// Unschedule tick event, regardless of its current state. 982SN/A void unscheduleTickEvent() 992SN/A { 1001400SN/A if (tickEvent.scheduled()) 1011400SN/A tickEvent.squash(); 1021400SN/A } 1033453Sgblack@eecs.umich.edu 1043453Sgblack@eecs.umich.edu private: 1054997Sgblack@eecs.umich.edu Trace::InstRecord *traceData; 1061400SN/A 1072SN/A public: 1081400SN/A // 1092623SN/A enum Status { 1102623SN/A Running, 1112SN/A Idle, 1121400SN/A IcacheMissStall, 1132683Sktlim@umich.edu IcacheMissComplete, 1142683Sktlim@umich.edu DcacheMissStall, 1152190SN/A DcacheMissSwitch, 1162683Sktlim@umich.edu SwitchedOut 1172683Sktlim@umich.edu }; 1182683Sktlim@umich.edu 1192680Sktlim@umich.edu private: 1202SN/A Status _status; 1211858SN/A 1222SN/A public: 1232SN/A void post_interrupt(int int_num, int index); 1242SN/A 1252SN/A void zero_fill_64(Addr addr) { 1262SN/A static int warned = 0; 1272SN/A if (!warned) { 1284181Sgblack@eecs.umich.edu warn ("WH64 is not implemented"); 1294181Sgblack@eecs.umich.edu warned = 1; 1304182Sgblack@eecs.umich.edu } 1314182Sgblack@eecs.umich.edu }; 1322SN/A 1332107SN/A public: 1343276Sgblack@eecs.umich.edu struct Params : public BaseCPU::Params 1351469SN/A { 1364377Sgblack@eecs.umich.edu MemInterface *icache_interface; 1374377Sgblack@eecs.umich.edu MemInterface *dcache_interface; 1384377Sgblack@eecs.umich.edu int width; 1394377Sgblack@eecs.umich.edu#if FULL_SYSTEM 1404377Sgblack@eecs.umich.edu AlphaITB *itb; 1414377Sgblack@eecs.umich.edu AlphaDTB *dtb; 1422623SN/A FunctionalMemory *mem; 1432662Sstever@eecs.umich.edu#else 1442623SN/A Process *process; 1452623SN/A#endif 1462623SN/A }; 147180SN/A SimpleCPU(Params *params); 148393SN/A virtual ~SimpleCPU(); 149393SN/A 1502SN/A public: 1512SN/A // execution context 152334SN/A CPUExecContext *cpuXC; 153334SN/A 1542SN/A ExecContext *xcProxy; 1552SN/A 1562SN/A void switchOut(Sampler *s); 157334SN/A void takeOverFrom(BaseCPU *oldCPU); 158729SN/A 159707SN/A#if FULL_SYSTEM 1604998Sgblack@eecs.umich.edu Addr dbg_vtophys(Addr addr); 1614998Sgblack@eecs.umich.edu 1624998Sgblack@eecs.umich.edu bool interval_stats; 1634998Sgblack@eecs.umich.edu#endif 1644998Sgblack@eecs.umich.edu 1654998Sgblack@eecs.umich.edu // L1 instruction cache 1664998Sgblack@eecs.umich.edu MemInterface *icacheInterface; 1674998Sgblack@eecs.umich.edu 168707SN/A // L1 data cache 169707SN/A MemInterface *dcacheInterface; 170707SN/A 171707SN/A // current instruction 1722SN/A MachInst inst; 1734564Sgblack@eecs.umich.edu 1744564Sgblack@eecs.umich.edu // Refcounted pointer to the one memory request. 1754564Sgblack@eecs.umich.edu MemReqPtr memReq; 1762SN/A 177729SN/A // Pointer to the sampler that is telling us to switchover. 1782SN/A // Used to signal the completion of the pipe drain and schedule 179124SN/A // the next switchover 180124SN/A Sampler *sampler; 181334SN/A 182124SN/A StaticInstPtr curStaticInst; 1832SN/A 184729SN/A class CacheCompletionEvent : public Event 185729SN/A { 1862SN/A private: 1872390SN/A SimpleCPU *cpu; 188729SN/A 1892SN/A public: 1902SN/A CacheCompletionEvent(SimpleCPU *_cpu); 1912390SN/A 1922390SN/A virtual void process(); 1932390SN/A virtual const char *description(); 1942390SN/A }; 1952390SN/A 196729SN/A CacheCompletionEvent cacheCompletionEvent; 1972SN/A 1982SN/A Status status() const { return _status; } 1992390SN/A 2002390SN/A virtual void activateContext(int thread_num, int delay); 2012390SN/A virtual void suspendContext(int thread_num); 2022390SN/A virtual void deallocateContext(int thread_num); 203217SN/A virtual void haltContext(int thread_num); 204237SN/A 2052SN/A // statistics 2061371SN/A virtual void regStats(); 2071371SN/A virtual void resetStats(); 2082623SN/A 2093918Ssaidi@eecs.umich.edu // number of simulated instructions 2103918Ssaidi@eecs.umich.edu Counter numInst; 2111371SN/A Counter startNumInst; 212581SN/A Stats::Scalar<> numInsts; 2132SN/A 2142SN/A virtual Counter totalInstructions() const 2152SN/A { 2162SN/A return numInst - startNumInst; 217753SN/A } 2182SN/A 2192SN/A // number of simulated memory references 2202SN/A Stats::Scalar<> numMemRefs; 221594SN/A 2224661Sksewell@umich.edu // number of simulated loads 223595SN/A Counter numLoad; 224594SN/A Counter startNumLoad; 225595SN/A 226705SN/A // number of idle cycles 227726SN/A Stats::Average<> notIdleFraction; 228726SN/A Stats::Formula idleFraction; 229726SN/A 230726SN/A // number of cycles stalled for I-cache misses 231726SN/A Stats::Scalar<> icacheStallCycles; 232726SN/A Counter lastIcacheStall; 233726SN/A 234726SN/A // number of cycles stalled for D-cache misses 235726SN/A Stats::Scalar<> dcacheStallCycles; 236726SN/A Counter lastDcacheStall; 237705SN/A 2383735Sstever@eecs.umich.edu void processCacheCompletion(); 239726SN/A 2402683Sktlim@umich.edu virtual void serialize(std::ostream &os); 241726SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 242705SN/A 2433735Sstever@eecs.umich.edu template <class T> 244726SN/A Fault read(Addr addr, T &data, unsigned flags); 245726SN/A 2462683Sktlim@umich.edu template <class T> 247726SN/A Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 248705SN/A 2493735Sstever@eecs.umich.edu // These functions are only used in CPU models that split 250726SN/A // effective address computation from the actual memory access. 251726SN/A void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); } 2522683Sktlim@umich.edu Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); } 253726SN/A 254705SN/A void prefetch(Addr addr, unsigned flags) 2553735Sstever@eecs.umich.edu { 2563735Sstever@eecs.umich.edu // need to do this... 257726SN/A } 258726SN/A 2592683Sktlim@umich.edu void writeHint(Addr addr, int size, unsigned flags) 2602455SN/A { 2612455SN/A // need to do this... 2623735Sstever@eecs.umich.edu } 2632455SN/A 2642455SN/A Fault copySrcTranslate(Addr src); 2652683Sktlim@umich.edu 266726SN/A Fault copy(Addr dest); 267705SN/A 2683735Sstever@eecs.umich.edu // The register accessor methods provide the index of the 269726SN/A // instruction's operand (e.g., 0 or 1), not the architectural 2702683Sktlim@umich.edu // register index, to simplify the implementation of register 271726SN/A // renaming. We find the architectural register index by indexing 272705SN/A // into the instruction's own operand index table. Note that a 2733735Sstever@eecs.umich.edu // raw pointer to the StaticInst is provided instead of a 2743735Sstever@eecs.umich.edu // ref-counted StaticInstPtr to redice overhead. This is fine as 275726SN/A // long as these methods don't copy the pointer into any long-term 276726SN/A // storage (which is pretty hard to imagine they would have reason 2772683Sktlim@umich.edu // to do). 278726SN/A 279705SN/A uint64_t readIntReg(const StaticInst *si, int idx) 2803735Sstever@eecs.umich.edu { 281726SN/A return cpuXC->readIntReg(si->srcRegIdx(idx)); 282726SN/A } 2832683Sktlim@umich.edu 284726SN/A float readFloatRegSingle(const StaticInst *si, int idx) 285726SN/A { 2863735Sstever@eecs.umich.edu int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2873735Sstever@eecs.umich.edu return cpuXC->readFloatRegSingle(reg_idx); 288726SN/A } 289726SN/A 2902683Sktlim@umich.edu double readFloatRegDouble(const StaticInst *si, int idx) 2912455SN/A { 2922455SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2933735Sstever@eecs.umich.edu return cpuXC->readFloatRegDouble(reg_idx); 2943735Sstever@eecs.umich.edu } 2952455SN/A 2962455SN/A uint64_t readFloatRegInt(const StaticInst *si, int idx) 2972683Sktlim@umich.edu { 298726SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 299705SN/A return cpuXC->readFloatRegInt(reg_idx); 3002683Sktlim@umich.edu } 3014950Sgblack@eecs.umich.edu 3022683Sktlim@umich.edu void setIntReg(const StaticInst *si, int idx, uint64_t val) 3034950Sgblack@eecs.umich.edu { 3042683Sktlim@umich.edu cpuXC->setIntReg(si->destRegIdx(idx), val); 3052447SN/A } 3062683Sktlim@umich.edu 3074950Sgblack@eecs.umich.edu void setFloatRegSingle(const StaticInst *si, int idx, float val) 3082683Sktlim@umich.edu { 3094950Sgblack@eecs.umich.edu int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 3102683Sktlim@umich.edu cpuXC->setFloatRegSingle(reg_idx, val); 311705SN/A } 3124172Ssaidi@eecs.umich.edu 3134172Ssaidi@eecs.umich.edu void setFloatRegDouble(const StaticInst *si, int idx, double val) 3144172Ssaidi@eecs.umich.edu { 3154172Ssaidi@eecs.umich.edu int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 3164172Ssaidi@eecs.umich.edu cpuXC->setFloatRegDouble(reg_idx, val); 3172159SN/A } 3182159SN/A 3192683Sktlim@umich.edu void setFloatRegInt(const StaticInst *si, int idx, uint64_t val) 3202159SN/A { 321705SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 3224172Ssaidi@eecs.umich.edu cpuXC->setFloatRegInt(reg_idx, val); 3232159SN/A } 3244172Ssaidi@eecs.umich.edu 3252159SN/A uint64_t readPC() { return cpuXC->readPC(); } 3262159SN/A void setNextPC(uint64_t val) { cpuXC->setNextPC(val); } 3273468Sgblack@eecs.umich.edu 3282159SN/A MiscReg readMiscReg(int misc_reg) 3292683Sktlim@umich.edu { 3302159SN/A return cpuXC->readMiscReg(misc_reg); 3312159SN/A } 3324185Ssaidi@eecs.umich.edu 3332159SN/A MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) 3344172Ssaidi@eecs.umich.edu { 3354172Ssaidi@eecs.umich.edu return cpuXC->readMiscRegWithEffect(misc_reg, fault); 3362159SN/A } 337705SN/A 3384185Ssaidi@eecs.umich.edu Fault setMiscReg(int misc_reg, const MiscReg &val) 3393792Sgblack@eecs.umich.edu { 3403792Sgblack@eecs.umich.edu return cpuXC->setMiscReg(misc_reg, val); 3413792Sgblack@eecs.umich.edu } 3423792Sgblack@eecs.umich.edu 3433792Sgblack@eecs.umich.edu Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) 3444185Ssaidi@eecs.umich.edu { 3453792Sgblack@eecs.umich.edu return cpuXC->setMiscRegWithEffect(misc_reg, val); 3463792Sgblack@eecs.umich.edu } 3474172Ssaidi@eecs.umich.edu 3483792Sgblack@eecs.umich.edu#if FULL_SYSTEM 3493792Sgblack@eecs.umich.edu Fault hwrei() { return cpuXC->hwrei(); } 3504185Ssaidi@eecs.umich.edu int readIntrFlag() { return cpuXC->readIntrFlag(); } 3513792Sgblack@eecs.umich.edu void setIntrFlag(int val) { cpuXC->setIntrFlag(val); } 3523792Sgblack@eecs.umich.edu bool inPalMode() { return cpuXC->inPalMode(); } 3533792Sgblack@eecs.umich.edu void ev5_trap(Fault fault) { cpuXC->ev5_trap(fault); } 3544172Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc) { return cpuXC->simPalCheck(palFunc); } 3553792Sgblack@eecs.umich.edu#else 3563792Sgblack@eecs.umich.edu void syscall() { cpuXC->syscall(); } 3574027Sstever@eecs.umich.edu#endif 3584027Sstever@eecs.umich.edu 3594027Sstever@eecs.umich.edu bool misspeculating() { return cpuXC->misspeculating(); } 3604027Sstever@eecs.umich.edu ExecContext *xcBase() { return xcProxy; } 3614027Sstever@eecs.umich.edu}; 3624027Sstever@eecs.umich.edu 3634027Sstever@eecs.umich.edu#endif // __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__ 3644027Sstever@eecs.umich.edu