base.cc revision 9448
1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Steve Reinhardt 41 */ 42 43#include "arch/kernel_stats.hh" 44#include "arch/stacktrace.hh" 45#include "arch/tlb.hh" 46#include "arch/utility.hh" 47#include "arch/vtophys.hh" 48#include "base/loader/symtab.hh" 49#include "base/cp_annotate.hh" 50#include "base/cprintf.hh" 51#include "base/inifile.hh" 52#include "base/misc.hh" 53#include "base/pollevent.hh" 54#include "base/trace.hh" 55#include "base/types.hh" 56#include "config/the_isa.hh" 57#include "cpu/simple/base.hh" 58#include "cpu/base.hh" 59#include "cpu/checker/cpu.hh" 60#include "cpu/checker/thread_context.hh" 61#include "cpu/exetrace.hh" 62#include "cpu/profile.hh" 63#include "cpu/simple_thread.hh" 64#include "cpu/smt.hh" 65#include "cpu/static_inst.hh" 66#include "cpu/thread_context.hh" 67#include "debug/Decode.hh" 68#include "debug/Fetch.hh" 69#include "debug/Quiesce.hh" 70#include "mem/mem_object.hh" 71#include "mem/packet.hh" 72#include "mem/request.hh" 73#include "params/BaseSimpleCPU.hh" 74#include "sim/byteswap.hh" 75#include "sim/debug.hh" 76#include "sim/faults.hh" 77#include "sim/full_system.hh" 78#include "sim/sim_events.hh" 79#include "sim/sim_object.hh" 80#include "sim/stats.hh" 81#include "sim/system.hh" 82 83using namespace std; 84using namespace TheISA; 85 86BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p) 87 : BaseCPU(p), traceData(NULL), thread(NULL) 88{ 89 if (FullSystem) 90 thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb, 91 p->isa[0]); 92 else 93 thread = new SimpleThread(this, /* thread_num */ 0, p->system, 94 p->workload[0], p->itb, p->dtb, p->isa[0]); 95 96 thread->setStatus(ThreadContext::Halted); 97 98 tc = thread->getTC(); 99 100 if (p->checker) { 101 BaseCPU *temp_checker = p->checker; 102 checker = dynamic_cast<CheckerCPU *>(temp_checker); 103 checker->setSystem(p->system); 104 // Manipulate thread context 105 ThreadContext *cpu_tc = tc; 106 tc = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker); 107 } else { 108 checker = NULL; 109 } 110 111 numInst = 0; 112 startNumInst = 0; 113 numOp = 0; 114 startNumOp = 0; 115 numLoad = 0; 116 startNumLoad = 0; 117 lastIcacheStall = 0; 118 lastDcacheStall = 0; 119 120 threadContexts.push_back(tc); 121 122 123 fetchOffset = 0; 124 stayAtPC = false; 125} 126 127BaseSimpleCPU::~BaseSimpleCPU() 128{ 129} 130 131void 132BaseSimpleCPU::deallocateContext(ThreadID thread_num) 133{ 134 // for now, these are equivalent 135 suspendContext(thread_num); 136} 137 138 139void 140BaseSimpleCPU::haltContext(ThreadID thread_num) 141{ 142 // for now, these are equivalent 143 suspendContext(thread_num); 144} 145 146 147void 148BaseSimpleCPU::regStats() 149{ 150 using namespace Stats; 151 152 BaseCPU::regStats(); 153 154 numInsts 155 .name(name() + ".committedInsts") 156 .desc("Number of instructions committed") 157 ; 158 159 numOps 160 .name(name() + ".committedOps") 161 .desc("Number of ops (including micro ops) committed") 162 ; 163 164 numIntAluAccesses 165 .name(name() + ".num_int_alu_accesses") 166 .desc("Number of integer alu accesses") 167 ; 168 169 numFpAluAccesses 170 .name(name() + ".num_fp_alu_accesses") 171 .desc("Number of float alu accesses") 172 ; 173 174 numCallsReturns 175 .name(name() + ".num_func_calls") 176 .desc("number of times a function call or return occured") 177 ; 178 179 numCondCtrlInsts 180 .name(name() + ".num_conditional_control_insts") 181 .desc("number of instructions that are conditional controls") 182 ; 183 184 numIntInsts 185 .name(name() + ".num_int_insts") 186 .desc("number of integer instructions") 187 ; 188 189 numFpInsts 190 .name(name() + ".num_fp_insts") 191 .desc("number of float instructions") 192 ; 193 194 numIntRegReads 195 .name(name() + ".num_int_register_reads") 196 .desc("number of times the integer registers were read") 197 ; 198 199 numIntRegWrites 200 .name(name() + ".num_int_register_writes") 201 .desc("number of times the integer registers were written") 202 ; 203 204 numFpRegReads 205 .name(name() + ".num_fp_register_reads") 206 .desc("number of times the floating registers were read") 207 ; 208 209 numFpRegWrites 210 .name(name() + ".num_fp_register_writes") 211 .desc("number of times the floating registers were written") 212 ; 213 214 numMemRefs 215 .name(name()+".num_mem_refs") 216 .desc("number of memory refs") 217 ; 218 219 numStoreInsts 220 .name(name() + ".num_store_insts") 221 .desc("Number of store instructions") 222 ; 223 224 numLoadInsts 225 .name(name() + ".num_load_insts") 226 .desc("Number of load instructions") 227 ; 228 229 notIdleFraction 230 .name(name() + ".not_idle_fraction") 231 .desc("Percentage of non-idle cycles") 232 ; 233 234 idleFraction 235 .name(name() + ".idle_fraction") 236 .desc("Percentage of idle cycles") 237 ; 238 239 numBusyCycles 240 .name(name() + ".num_busy_cycles") 241 .desc("Number of busy cycles") 242 ; 243 244 numIdleCycles 245 .name(name()+".num_idle_cycles") 246 .desc("Number of idle cycles") 247 ; 248 249 icacheStallCycles 250 .name(name() + ".icache_stall_cycles") 251 .desc("ICache total stall cycles") 252 .prereq(icacheStallCycles) 253 ; 254 255 dcacheStallCycles 256 .name(name() + ".dcache_stall_cycles") 257 .desc("DCache total stall cycles") 258 .prereq(dcacheStallCycles) 259 ; 260 261 icacheRetryCycles 262 .name(name() + ".icache_retry_cycles") 263 .desc("ICache total retry cycles") 264 .prereq(icacheRetryCycles) 265 ; 266 267 dcacheRetryCycles 268 .name(name() + ".dcache_retry_cycles") 269 .desc("DCache total retry cycles") 270 .prereq(dcacheRetryCycles) 271 ; 272 273 idleFraction = constant(1.0) - notIdleFraction; 274 numIdleCycles = idleFraction * numCycles; 275 numBusyCycles = (notIdleFraction)*numCycles; 276} 277 278void 279BaseSimpleCPU::resetStats() 280{ 281// startNumInst = numInst; 282 notIdleFraction = (_status != Idle); 283} 284 285void 286BaseSimpleCPU::serializeThread(ostream &os, ThreadID tid) 287{ 288 assert(_status == Idle || _status == Running); 289 assert(tid == 0); 290 291 thread->serialize(os); 292} 293 294void 295BaseSimpleCPU::unserializeThread(Checkpoint *cp, const string §ion, 296 ThreadID tid) 297{ 298 if (tid != 0) 299 fatal("Trying to load more than one thread into a SimpleCPU\n"); 300 thread->unserialize(cp, section); 301} 302 303void 304change_thread_state(ThreadID tid, int activate, int priority) 305{ 306} 307 308Addr 309BaseSimpleCPU::dbg_vtophys(Addr addr) 310{ 311 return vtophys(tc, addr); 312} 313 314void 315BaseSimpleCPU::wakeup() 316{ 317 if (thread->status() != ThreadContext::Suspended) 318 return; 319 320 DPRINTF(Quiesce,"Suspended Processor awoke\n"); 321 thread->activate(); 322} 323 324void 325BaseSimpleCPU::checkForInterrupts() 326{ 327 if (checkInterrupts(tc)) { 328 Fault interrupt = interrupts->getInterrupt(tc); 329 330 if (interrupt != NoFault) { 331 fetchOffset = 0; 332 interrupts->updateIntrInfo(tc); 333 interrupt->invoke(tc); 334 thread->decoder.reset(); 335 } 336 } 337} 338 339 340void 341BaseSimpleCPU::setupFetchRequest(Request *req) 342{ 343 Addr instAddr = thread->instAddr(); 344 345 // set up memory request for instruction fetch 346 DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr); 347 348 Addr fetchPC = (instAddr & PCMask) + fetchOffset; 349 req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instMasterId(), 350 instAddr); 351} 352 353 354void 355BaseSimpleCPU::preExecute() 356{ 357 // maintain $r0 semantics 358 thread->setIntReg(ZeroReg, 0); 359#if THE_ISA == ALPHA_ISA 360 thread->setFloatReg(ZeroReg, 0.0); 361#endif // ALPHA_ISA 362 363 // check for instruction-count-based events 364 comInstEventQueue[0]->serviceEvents(numInst); 365 system->instEventQueue.serviceEvents(system->totalNumInsts); 366 367 // decode the instruction 368 inst = gtoh(inst); 369 370 TheISA::PCState pcState = thread->pcState(); 371 372 if (isRomMicroPC(pcState.microPC())) { 373 stayAtPC = false; 374 curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(), 375 curMacroStaticInst); 376 } else if (!curMacroStaticInst) { 377 //We're not in the middle of a macro instruction 378 StaticInstPtr instPtr = NULL; 379 380 TheISA::Decoder *decoder = &(thread->decoder); 381 382 //Predecode, ie bundle up an ExtMachInst 383 //If more fetch data is needed, pass it in. 384 Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset; 385 //if(decoder->needMoreBytes()) 386 decoder->moreBytes(pcState, fetchPC, inst); 387 //else 388 // decoder->process(); 389 390 //Decode an instruction if one is ready. Otherwise, we'll have to 391 //fetch beyond the MachInst at the current pc. 392 instPtr = decoder->decode(pcState); 393 if (instPtr) { 394 stayAtPC = false; 395 thread->pcState(pcState); 396 } else { 397 stayAtPC = true; 398 fetchOffset += sizeof(MachInst); 399 } 400 401 //If we decoded an instruction and it's microcoded, start pulling 402 //out micro ops 403 if (instPtr && instPtr->isMacroop()) { 404 curMacroStaticInst = instPtr; 405 curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 406 } else { 407 curStaticInst = instPtr; 408 } 409 } else { 410 //Read the next micro op from the macro op 411 curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 412 } 413 414 //If we decoded an instruction this "tick", record information about it. 415 if (curStaticInst) { 416#if TRACING_ON 417 traceData = tracer->getInstRecord(curTick(), tc, 418 curStaticInst, thread->pcState(), curMacroStaticInst); 419 420 DPRINTF(Decode,"Decode: Decoded %s instruction: %#x\n", 421 curStaticInst->getName(), curStaticInst->machInst); 422#endif // TRACING_ON 423 } 424} 425 426void 427BaseSimpleCPU::postExecute() 428{ 429 assert(curStaticInst); 430 431 TheISA::PCState pc = tc->pcState(); 432 Addr instAddr = pc.instAddr(); 433 if (FullSystem && thread->profile) { 434 bool usermode = TheISA::inUserMode(tc); 435 thread->profilePC = usermode ? 1 : instAddr; 436 ProfileNode *node = thread->profile->consume(tc, curStaticInst); 437 if (node) 438 thread->profileNode = node; 439 } 440 441 if (curStaticInst->isMemRef()) { 442 numMemRefs++; 443 } 444 445 if (curStaticInst->isLoad()) { 446 ++numLoad; 447 comLoadEventQueue[0]->serviceEvents(numLoad); 448 } 449 450 if (CPA::available()) { 451 CPA::cpa()->swAutoBegin(tc, pc.nextInstAddr()); 452 } 453 454 /* Power model statistics */ 455 //integer alu accesses 456 if (curStaticInst->isInteger()){ 457 numIntAluAccesses++; 458 numIntInsts++; 459 } 460 461 //float alu accesses 462 if (curStaticInst->isFloating()){ 463 numFpAluAccesses++; 464 numFpInsts++; 465 } 466 467 //number of function calls/returns to get window accesses 468 if (curStaticInst->isCall() || curStaticInst->isReturn()){ 469 numCallsReturns++; 470 } 471 472 //the number of branch predictions that will be made 473 if (curStaticInst->isCondCtrl()){ 474 numCondCtrlInsts++; 475 } 476 477 //result bus acceses 478 if (curStaticInst->isLoad()){ 479 numLoadInsts++; 480 } 481 482 if (curStaticInst->isStore()){ 483 numStoreInsts++; 484 } 485 /* End power model statistics */ 486 487 if (FullSystem) 488 traceFunctions(instAddr); 489 490 if (traceData) { 491 traceData->dump(); 492 delete traceData; 493 traceData = NULL; 494 } 495} 496 497 498void 499BaseSimpleCPU::advancePC(Fault fault) 500{ 501 //Since we're moving to a new pc, zero out the offset 502 fetchOffset = 0; 503 if (fault != NoFault) { 504 curMacroStaticInst = StaticInst::nullStaticInstPtr; 505 fault->invoke(tc, curStaticInst); 506 thread->decoder.reset(); 507 } else { 508 if (curStaticInst) { 509 if (curStaticInst->isLastMicroop()) 510 curMacroStaticInst = StaticInst::nullStaticInstPtr; 511 TheISA::PCState pcState = thread->pcState(); 512 TheISA::advancePC(pcState, curStaticInst); 513 thread->pcState(pcState); 514 } 515 } 516} 517 518/*Fault 519BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr) 520{ 521 // translate to physical address 522 Fault fault = NoFault; 523 int CacheID = Op & 0x3; // Lower 3 bits identify Cache 524 int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation 525 if(CacheID > 1) 526 { 527 warn("CacheOps not implemented for secondary/tertiary caches\n"); 528 } 529 else 530 { 531 switch(CacheOP) 532 { // Fill Packet Type 533 case 0: warn("Invalidate Cache Op\n"); 534 break; 535 case 1: warn("Index Load Tag Cache Op\n"); 536 break; 537 case 2: warn("Index Store Tag Cache Op\n"); 538 break; 539 case 4: warn("Hit Invalidate Cache Op\n"); 540 break; 541 case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n"); 542 break; 543 case 6: warn("Hit Writeback\n"); 544 break; 545 case 7: warn("Fetch & Lock Cache Op\n"); 546 break; 547 default: warn("Unimplemented Cache Op\n"); 548 } 549 } 550 return fault; 551}*/ 552