base.cc revision 8793:5f25086326ac
12330SN/A/* 22330SN/A * Copyright (c) 2010 ARM Limited 32330SN/A * All rights reserved 42330SN/A * 52330SN/A * The license below extends only to copyright in the software and shall 62330SN/A * not be construed as granting a license to any other intellectual 72330SN/A * property including but not limited to intellectual property relating 82330SN/A * to a hardware implementation of the functionality of the software 92330SN/A * licensed hereunder. You may use the software subject to the license 102330SN/A * terms below provided that you ensure that this notice is replicated 112330SN/A * unmodified and in its entirety in all distributions of the software, 122330SN/A * modified or unmodified, in source code or in binary form. 132330SN/A * 142330SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152330SN/A * All rights reserved. 162330SN/A * 172330SN/A * Redistribution and use in source and binary forms, with or without 182330SN/A * modification, are permitted provided that the following conditions are 192330SN/A * met: redistributions of source code must retain the above copyright 202330SN/A * notice, this list of conditions and the following disclaimer; 212330SN/A * redistributions in binary form must reproduce the above copyright 222330SN/A * notice, this list of conditions and the following disclaimer in the 232330SN/A * documentation and/or other materials provided with the distribution; 242330SN/A * neither the name of the copyright holders nor the names of its 252330SN/A * contributors may be used to endorse or promote products derived from 262330SN/A * this software without specific prior written permission. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292330SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342980Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356658Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 368229Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372362SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382680Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392683Sktlim@umich.edu * 402683Sktlim@umich.edu * Authors: Steve Reinhardt 412678Sktlim@umich.edu */ 422292SN/A 432292SN/A#include "arch/faults.hh" 442292SN/A#include "arch/kernel_stats.hh" 453548Sgblack@eecs.umich.edu#include "arch/stacktrace.hh" 463548Sgblack@eecs.umich.edu#include "arch/tlb.hh" 473548Sgblack@eecs.umich.edu#include "arch/utility.hh" 488902Sandreas.hansson@arm.com#include "arch/vtophys.hh" 498902Sandreas.hansson@arm.com#include "base/loader/symtab.hh" 502292SN/A#include "base/cp_annotate.hh" 512862Sktlim@umich.edu#include "base/cprintf.hh" 522862Sktlim@umich.edu#include "base/inifile.hh" 532330SN/A#include "base/misc.hh" 542330SN/A#include "base/pollevent.hh" 552330SN/A#include "base/range.hh" 562330SN/A#include "base/trace.hh" 572330SN/A#include "base/types.hh" 582330SN/A#include "config/the_isa.hh" 592292SN/A#include "cpu/simple/base.hh" 602683Sktlim@umich.edu#include "cpu/base.hh" 612683Sktlim@umich.edu#include "cpu/exetrace.hh" 626331Sgblack@eecs.umich.edu#include "cpu/profile.hh" 632683Sktlim@umich.edu#include "cpu/simple_thread.hh" 648735Sandreas.hanson@arm.com#include "cpu/smt.hh" 653486Sktlim@umich.edu#include "cpu/static_inst.hh" 662862Sktlim@umich.edu#include "cpu/thread_context.hh" 672862Sktlim@umich.edu#include "debug/Decode.hh" 682862Sktlim@umich.edu#include "debug/Fetch.hh" 692862Sktlim@umich.edu#include "debug/Quiesce.hh" 705712Shsul@eecs.umich.edu#include "mem/mem_object.hh" 712683Sktlim@umich.edu#include "mem/packet.hh" 725714Shsul@eecs.umich.edu#include "mem/request.hh" 735714Shsul@eecs.umich.edu#include "params/BaseSimpleCPU.hh" 745714Shsul@eecs.umich.edu#include "sim/byteswap.hh" 755714Shsul@eecs.umich.edu#include "sim/debug.hh" 766221Snate@binkert.org#include "sim/full_system.hh" 772683Sktlim@umich.edu#include "sim/sim_events.hh" 786221Snate@binkert.org#include "sim/sim_object.hh" 792683Sktlim@umich.edu#include "sim/stats.hh" 802683Sktlim@umich.edu#include "sim/system.hh" 812683Sktlim@umich.edu 822683Sktlim@umich.eduusing namespace std; 832683Sktlim@umich.eduusing namespace TheISA; 848706Sandreas.hansson@arm.com 858706Sandreas.hansson@arm.comBaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p) 868706Sandreas.hansson@arm.com : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL) 878706Sandreas.hansson@arm.com{ 888706Sandreas.hansson@arm.com if (FullSystem) 898706Sandreas.hansson@arm.com thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb); 908706Sandreas.hansson@arm.com else 913675Sktlim@umich.edu thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0], 922683Sktlim@umich.edu p->itb, p->dtb); 932683Sktlim@umich.edu 942683Sktlim@umich.edu thread->setStatus(ThreadContext::Halted); 952683Sktlim@umich.edu 962683Sktlim@umich.edu tc = thread->getTC(); 972683Sktlim@umich.edu 982683Sktlim@umich.edu numInst = 0; 992683Sktlim@umich.edu startNumInst = 0; 1003548Sgblack@eecs.umich.edu numLoad = 0; 1012683Sktlim@umich.edu startNumLoad = 0; 1028852Sandreas.hansson@arm.com lastIcacheStall = 0; 1032690Sktlim@umich.edu lastDcacheStall = 0; 1048852Sandreas.hansson@arm.com 1058799Sgblack@eecs.umich.edu threadContexts.push_back(tc); 1062683Sktlim@umich.edu 1072683Sktlim@umich.edu 1088852Sandreas.hansson@arm.com fetchOffset = 0; 1092292SN/A stayAtPC = false; 1102683Sktlim@umich.edu} 1112683Sktlim@umich.edu 1122683Sktlim@umich.eduBaseSimpleCPU::~BaseSimpleCPU() 1132683Sktlim@umich.edu{ 1142683Sktlim@umich.edu} 1152683Sktlim@umich.edu 1162683Sktlim@umich.eduvoid 1172683Sktlim@umich.eduBaseSimpleCPU::deallocateContext(int thread_num) 1182683Sktlim@umich.edu{ 1192683Sktlim@umich.edu // for now, these are equivalent 1202683Sktlim@umich.edu suspendContext(thread_num); 1212683Sktlim@umich.edu} 1222683Sktlim@umich.edu 1232683Sktlim@umich.edu 1242683Sktlim@umich.eduvoid 1252683Sktlim@umich.eduBaseSimpleCPU::haltContext(int thread_num) 1263673Srdreslin@umich.edu{ 1273486Sktlim@umich.edu // for now, these are equivalent 1282683Sktlim@umich.edu suspendContext(thread_num); 1292683Sktlim@umich.edu} 1302683Sktlim@umich.edu 1315999Snate@binkert.org 1328834Satgutier@umich.eduvoid 1338834Satgutier@umich.eduBaseSimpleCPU::regStats() 1348834Satgutier@umich.edu{ 1358834Satgutier@umich.edu using namespace Stats; 1362683Sktlim@umich.edu 1375999Snate@binkert.org BaseCPU::regStats(); 1382683Sktlim@umich.edu 1392683Sktlim@umich.edu numInsts 1402683Sktlim@umich.edu .name(name() + ".num_insts") 1412683Sktlim@umich.edu .desc("Number of instructions executed") 1422683Sktlim@umich.edu ; 1432683Sktlim@umich.edu 1442683Sktlim@umich.edu numIntAluAccesses 1452683Sktlim@umich.edu .name(name() + ".num_int_alu_accesses") 1462683Sktlim@umich.edu .desc("Number of integer alu accesses") 1472683Sktlim@umich.edu ; 1482683Sktlim@umich.edu 1492683Sktlim@umich.edu numFpAluAccesses 1503402Sktlim@umich.edu .name(name() + ".num_fp_alu_accesses") 1513402Sktlim@umich.edu .desc("Number of float alu accesses") 1523402Sktlim@umich.edu ; 1535714Shsul@eecs.umich.edu 1545714Shsul@eecs.umich.edu numCallsReturns 1555714Shsul@eecs.umich.edu .name(name() + ".num_func_calls") 1562292SN/A .desc("number of times a function call or return occured") 1576221Snate@binkert.org ; 1582292SN/A 1592690Sktlim@umich.edu numCondCtrlInsts 1602683Sktlim@umich.edu .name(name() + ".num_conditional_control_insts") 1612683Sktlim@umich.edu .desc("number of instructions that are conditional controls") 1622292SN/A ; 1632683Sktlim@umich.edu 1642683Sktlim@umich.edu numIntInsts 1652292SN/A .name(name() + ".num_int_insts") 1662683Sktlim@umich.edu .desc("number of integer instructions") 1672292SN/A ; 1682292SN/A 1692292SN/A numFpInsts 1702292SN/A .name(name() + ".num_fp_insts") 1712292SN/A .desc("number of float instructions") 1723548Sgblack@eecs.umich.edu ; 1738777Sgblack@eecs.umich.edu 1742683Sktlim@umich.edu numIntRegReads 1758229Snate@binkert.org .name(name() + ".num_int_register_reads") 1768229Snate@binkert.org .desc("number of times the integer registers were read") 1778706Sandreas.hansson@arm.com ; 1782683Sktlim@umich.edu 1798706Sandreas.hansson@arm.com numIntRegWrites 1802683Sktlim@umich.edu .name(name() + ".num_int_register_writes") 1818706Sandreas.hansson@arm.com .desc("number of times the integer registers were written") 1828706Sandreas.hansson@arm.com ; 1838852Sandreas.hansson@arm.com 1848852Sandreas.hansson@arm.com numFpRegReads 1852678Sktlim@umich.edu .name(name() + ".num_fp_register_reads") 1862690Sktlim@umich.edu .desc("number of times the floating registers were read") 1872292SN/A ; 1882292SN/A 1892292SN/A numFpRegWrites 1902292SN/A .name(name() + ".num_fp_register_writes") 1912292SN/A .desc("number of times the floating registers were written") 1922292SN/A ; 1932292SN/A 1942292SN/A numMemRefs 1952292SN/A .name(name()+".num_mem_refs") 1962292SN/A .desc("number of memory refs") 1972292SN/A ; 1982292SN/A 1992292SN/A numStoreInsts 200 .name(name() + ".num_store_insts") 201 .desc("Number of store instructions") 202 ; 203 204 numLoadInsts 205 .name(name() + ".num_load_insts") 206 .desc("Number of load instructions") 207 ; 208 209 notIdleFraction 210 .name(name() + ".not_idle_fraction") 211 .desc("Percentage of non-idle cycles") 212 ; 213 214 idleFraction 215 .name(name() + ".idle_fraction") 216 .desc("Percentage of idle cycles") 217 ; 218 219 numBusyCycles 220 .name(name() + ".num_busy_cycles") 221 .desc("Number of busy cycles") 222 ; 223 224 numIdleCycles 225 .name(name()+".num_idle_cycles") 226 .desc("Number of idle cycles") 227 ; 228 229 icacheStallCycles 230 .name(name() + ".icache_stall_cycles") 231 .desc("ICache total stall cycles") 232 .prereq(icacheStallCycles) 233 ; 234 235 dcacheStallCycles 236 .name(name() + ".dcache_stall_cycles") 237 .desc("DCache total stall cycles") 238 .prereq(dcacheStallCycles) 239 ; 240 241 icacheRetryCycles 242 .name(name() + ".icache_retry_cycles") 243 .desc("ICache total retry cycles") 244 .prereq(icacheRetryCycles) 245 ; 246 247 dcacheRetryCycles 248 .name(name() + ".dcache_retry_cycles") 249 .desc("DCache total retry cycles") 250 .prereq(dcacheRetryCycles) 251 ; 252 253 idleFraction = constant(1.0) - notIdleFraction; 254 numIdleCycles = idleFraction * numCycles; 255 numBusyCycles = (notIdleFraction)*numCycles; 256} 257 258void 259BaseSimpleCPU::resetStats() 260{ 261// startNumInst = numInst; 262 notIdleFraction = (_status != Idle); 263} 264 265void 266BaseSimpleCPU::serialize(ostream &os) 267{ 268 SERIALIZE_ENUM(_status); 269 BaseCPU::serialize(os); 270// SERIALIZE_SCALAR(inst); 271 nameOut(os, csprintf("%s.xc.0", name())); 272 thread->serialize(os); 273} 274 275void 276BaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 277{ 278 UNSERIALIZE_ENUM(_status); 279 BaseCPU::unserialize(cp, section); 280// UNSERIALIZE_SCALAR(inst); 281 thread->unserialize(cp, csprintf("%s.xc.0", section)); 282} 283 284void 285change_thread_state(ThreadID tid, int activate, int priority) 286{ 287} 288 289Addr 290BaseSimpleCPU::dbg_vtophys(Addr addr) 291{ 292 return vtophys(tc, addr); 293} 294 295void 296BaseSimpleCPU::wakeup() 297{ 298 if (thread->status() != ThreadContext::Suspended) 299 return; 300 301 DPRINTF(Quiesce,"Suspended Processor awoke\n"); 302 thread->activate(); 303} 304 305void 306BaseSimpleCPU::checkForInterrupts() 307{ 308 if (checkInterrupts(tc)) { 309 Fault interrupt = interrupts->getInterrupt(tc); 310 311 if (interrupt != NoFault) { 312 fetchOffset = 0; 313 interrupts->updateIntrInfo(tc); 314 interrupt->invoke(tc); 315 predecoder.reset(); 316 } 317 } 318} 319 320 321void 322BaseSimpleCPU::setupFetchRequest(Request *req) 323{ 324 Addr instAddr = thread->instAddr(); 325 326 // set up memory request for instruction fetch 327 DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr); 328 329 Addr fetchPC = (instAddr & PCMask) + fetchOffset; 330 req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instAddr); 331} 332 333 334void 335BaseSimpleCPU::preExecute() 336{ 337 // maintain $r0 semantics 338 thread->setIntReg(ZeroReg, 0); 339#if THE_ISA == ALPHA_ISA 340 thread->setFloatReg(ZeroReg, 0.0); 341#endif // ALPHA_ISA 342 343 // check for instruction-count-based events 344 comInstEventQueue[0]->serviceEvents(numInst); 345 system->instEventQueue.serviceEvents(system->totalNumInsts); 346 347 // decode the instruction 348 inst = gtoh(inst); 349 350 TheISA::PCState pcState = thread->pcState(); 351 352 if (isRomMicroPC(pcState.microPC())) { 353 stayAtPC = false; 354 curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(), 355 curMacroStaticInst); 356 } else if (!curMacroStaticInst) { 357 //We're not in the middle of a macro instruction 358 StaticInstPtr instPtr = NULL; 359 360 //Predecode, ie bundle up an ExtMachInst 361 //This should go away once the constructor can be set up properly 362 predecoder.setTC(thread->getTC()); 363 //If more fetch data is needed, pass it in. 364 Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset; 365 //if(predecoder.needMoreBytes()) 366 predecoder.moreBytes(pcState, fetchPC, inst); 367 //else 368 // predecoder.process(); 369 370 //If an instruction is ready, decode it. Otherwise, we'll have to 371 //fetch beyond the MachInst at the current pc. 372 if (predecoder.extMachInstReady()) { 373 stayAtPC = false; 374 ExtMachInst machInst = predecoder.getExtMachInst(pcState); 375 thread->pcState(pcState); 376 instPtr = thread->decoder.decode(machInst, pcState.instAddr()); 377 } else { 378 stayAtPC = true; 379 fetchOffset += sizeof(MachInst); 380 } 381 382 //If we decoded an instruction and it's microcoded, start pulling 383 //out micro ops 384 if (instPtr && instPtr->isMacroop()) { 385 curMacroStaticInst = instPtr; 386 curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 387 } else { 388 curStaticInst = instPtr; 389 } 390 } else { 391 //Read the next micro op from the macro op 392 curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 393 } 394 395 //If we decoded an instruction this "tick", record information about it. 396 if(curStaticInst) 397 { 398#if TRACING_ON 399 traceData = tracer->getInstRecord(curTick(), tc, 400 curStaticInst, thread->pcState(), curMacroStaticInst); 401 402 DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n", 403 curStaticInst->getName(), curStaticInst->machInst); 404#endif // TRACING_ON 405 } 406} 407 408void 409BaseSimpleCPU::postExecute() 410{ 411 assert(curStaticInst); 412 413 TheISA::PCState pc = tc->pcState(); 414 Addr instAddr = pc.instAddr(); 415 if (FullSystem && thread->profile) { 416 bool usermode = TheISA::inUserMode(tc); 417 thread->profilePC = usermode ? 1 : instAddr; 418 ProfileNode *node = thread->profile->consume(tc, curStaticInst); 419 if (node) 420 thread->profileNode = node; 421 } 422 423 if (curStaticInst->isMemRef()) { 424 numMemRefs++; 425 } 426 427 if (curStaticInst->isLoad()) { 428 ++numLoad; 429 comLoadEventQueue[0]->serviceEvents(numLoad); 430 } 431 432 if (CPA::available()) { 433 CPA::cpa()->swAutoBegin(tc, pc.nextInstAddr()); 434 } 435 436 /* Power model statistics */ 437 //integer alu accesses 438 if (curStaticInst->isInteger()){ 439 numIntAluAccesses++; 440 numIntInsts++; 441 } 442 443 //float alu accesses 444 if (curStaticInst->isFloating()){ 445 numFpAluAccesses++; 446 numFpInsts++; 447 } 448 449 //number of function calls/returns to get window accesses 450 if (curStaticInst->isCall() || curStaticInst->isReturn()){ 451 numCallsReturns++; 452 } 453 454 //the number of branch predictions that will be made 455 if (curStaticInst->isCondCtrl()){ 456 numCondCtrlInsts++; 457 } 458 459 //result bus acceses 460 if (curStaticInst->isLoad()){ 461 numLoadInsts++; 462 } 463 464 if (curStaticInst->isStore()){ 465 numStoreInsts++; 466 } 467 /* End power model statistics */ 468 469 if (FullSystem) 470 traceFunctions(instAddr); 471 472 if (traceData) { 473 traceData->dump(); 474 delete traceData; 475 traceData = NULL; 476 } 477} 478 479 480void 481BaseSimpleCPU::advancePC(Fault fault) 482{ 483 //Since we're moving to a new pc, zero out the offset 484 fetchOffset = 0; 485 if (fault != NoFault) { 486 curMacroStaticInst = StaticInst::nullStaticInstPtr; 487 fault->invoke(tc, curStaticInst); 488 predecoder.reset(); 489 } else { 490 if (curStaticInst) { 491 if (curStaticInst->isLastMicroop()) 492 curMacroStaticInst = StaticInst::nullStaticInstPtr; 493 TheISA::PCState pcState = thread->pcState(); 494 TheISA::advancePC(pcState, curStaticInst); 495 thread->pcState(pcState); 496 } 497 } 498} 499 500/*Fault 501BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr) 502{ 503 // translate to physical address 504 Fault fault = NoFault; 505 int CacheID = Op & 0x3; // Lower 3 bits identify Cache 506 int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation 507 if(CacheID > 1) 508 { 509 warn("CacheOps not implemented for secondary/tertiary caches\n"); 510 } 511 else 512 { 513 switch(CacheOP) 514 { // Fill Packet Type 515 case 0: warn("Invalidate Cache Op\n"); 516 break; 517 case 1: warn("Index Load Tag Cache Op\n"); 518 break; 519 case 2: warn("Index Store Tag Cache Op\n"); 520 break; 521 case 4: warn("Hit Invalidate Cache Op\n"); 522 break; 523 case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n"); 524 break; 525 case 6: warn("Hit Writeback\n"); 526 break; 527 case 7: warn("Fetch & Lock Cache Op\n"); 528 break; 529 default: warn("Unimplemented Cache Op\n"); 530 } 531 } 532 return fault; 533}*/ 534