base.cc revision 3280
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292SN/A */ 302SN/A 312439SN/A#include "arch/utility.hh" 322984Sgblack@eecs.umich.edu#include "arch/faults.hh" 33146SN/A#include "base/cprintf.hh" 34146SN/A#include "base/inifile.hh" 35146SN/A#include "base/loader/symtab.hh" 36146SN/A#include "base/misc.hh" 37146SN/A#include "base/pollevent.hh" 38146SN/A#include "base/range.hh" 391717SN/A#include "base/stats/events.hh" 40146SN/A#include "base/trace.hh" 411717SN/A#include "cpu/base.hh" 42146SN/A#include "cpu/exetrace.hh" 431977SN/A#include "cpu/profile.hh" 442623SN/A#include "cpu/simple/base.hh" 452683Sktlim@umich.edu#include "cpu/simple_thread.hh" 461717SN/A#include "cpu/smt.hh" 47146SN/A#include "cpu/static_inst.hh" 482683Sktlim@umich.edu#include "cpu/thread_context.hh" 493348Sbinkertn@umich.edu#include "kern/kernel_stats.hh" 502036SN/A#include "mem/packet_impl.hh" 51146SN/A#include "sim/builder.hh" 5256SN/A#include "sim/byteswap.hh" 5356SN/A#include "sim/debug.hh" 5456SN/A#include "sim/host.hh" 55695SN/A#include "sim/sim_events.hh" 562901Ssaidi@eecs.umich.edu#include "sim/sim_object.hh" 572SN/A#include "sim/stats.hh" 581858SN/A#include "sim/system.hh" 593565Sgblack@eecs.umich.edu 603565Sgblack@eecs.umich.edu#if FULL_SYSTEM 612171SN/A#include "base/remote_gdb.hh" 622170SN/A#include "arch/tlb.hh" 633562Sgblack@eecs.umich.edu#include "arch/stacktrace.hh" 64146SN/A#include "arch/vtophys.hh" 652462SN/A#else // !FULL_SYSTEM 66146SN/A#include "mem/mem_object.hh" 672SN/A#endif // FULL_SYSTEM 685529Snate@binkert.org 695529Snate@binkert.orgusing namespace std; 702SN/Ausing namespace TheISA; 712449SN/A 721355SN/ABaseSimpleCPU::BaseSimpleCPU(Params *p) 735529Snate@binkert.org : BaseCPU(p), mem(p->mem), thread(NULL) 744495Sacolyte@umich.edu{ 75224SN/A#if FULL_SYSTEM 761858SN/A thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb); 772683Sktlim@umich.edu#else 782420SN/A thread = new SimpleThread(this, /* thread_num */ 0, p->process, 795529Snate@binkert.org /* asid */ 0, mem); 804997Sgblack@eecs.umich.edu#endif // !FULL_SYSTEM 812420SN/A 822SN/A thread->setStatus(ThreadContext::Suspended); 834400Srdreslin@umich.edu 842672Sktlim@umich.edu tc = thread->getTC(); 852683Sktlim@umich.edu 862SN/A numInst = 0; 872SN/A startNumInst = 0; 88334SN/A numLoad = 0; 89140SN/A startNumLoad = 0; 90334SN/A lastIcacheStall = 0; 912SN/A lastDcacheStall = 0; 922SN/A 932SN/A threadContexts.push_back(tc); 942680Sktlim@umich.edu} 954377Sgblack@eecs.umich.edu 965169Ssaidi@eecs.umich.eduBaseSimpleCPU::~BaseSimpleCPU() 974377Sgblack@eecs.umich.edu{ 984377Sgblack@eecs.umich.edu} 992SN/A 1002SN/Avoid 1012623SN/ABaseSimpleCPU::deallocateContext(int thread_num) 1022SN/A{ 1032SN/A // for now, these are equivalent 1042SN/A suspendContext(thread_num); 105180SN/A} 1062623SN/A 107393SN/A 108393SN/Avoid 109393SN/ABaseSimpleCPU::haltContext(int thread_num) 110393SN/A{ 111384SN/A // for now, these are equivalent 112384SN/A suspendContext(thread_num); 113393SN/A} 1142623SN/A 115393SN/A 116393SN/Avoid 117393SN/ABaseSimpleCPU::regStats() 118393SN/A{ 119384SN/A using namespace Stats; 120189SN/A 121189SN/A BaseCPU::regStats(); 1222623SN/A 1232SN/A numInsts 124729SN/A .name(name() + ".num_insts") 125334SN/A .desc("Number of instructions executed") 1262SN/A ; 1272SN/A 1282SN/A numMemRefs 1292SN/A .name(name() + ".num_refs") 1302SN/A .desc("Number of memory references") 1312SN/A ; 1322SN/A 1332SN/A notIdleFraction 1342SN/A .name(name() + ".not_idle_fraction") 1352SN/A .desc("Percentage of non-idle cycles") 1362SN/A ; 1372SN/A 1381001SN/A idleFraction 1391001SN/A .name(name() + ".idle_fraction") 1401001SN/A .desc("Percentage of idle cycles") 1411001SN/A ; 1421001SN/A 1432SN/A icacheStallCycles 1442SN/A .name(name() + ".icache_stall_cycles") 1452SN/A .desc("ICache total stall cycles") 1462SN/A .prereq(icacheStallCycles) 1472SN/A ; 1482SN/A 1492SN/A dcacheStallCycles 1502SN/A .name(name() + ".dcache_stall_cycles") 1512SN/A .desc("DCache total stall cycles") 1522SN/A .prereq(dcacheStallCycles) 1532SN/A ; 1542SN/A 1552SN/A icacheRetryCycles 1562SN/A .name(name() + ".icache_retry_cycles") 1572SN/A .desc("ICache total retry cycles") 1582SN/A .prereq(icacheRetryCycles) 1592SN/A ; 1602390SN/A 1612390SN/A dcacheRetryCycles 1622390SN/A .name(name() + ".dcache_retry_cycles") 1632390SN/A .desc("DCache total retry cycles") 1642390SN/A .prereq(dcacheRetryCycles) 1652390SN/A ; 1662390SN/A 1672390SN/A idleFraction = constant(1.0) - notIdleFraction; 1682390SN/A} 1692390SN/A 1702390SN/Avoid 1712390SN/ABaseSimpleCPU::resetStats() 172385SN/A{ 1732SN/A// startNumInst = numInst; 1742SN/A // notIdleFraction = (_status != Idle); 1752SN/A} 1762623SN/A 177334SN/Avoid 1782361SN/ABaseSimpleCPU::serialize(ostream &os) 1795496Ssaidi@eecs.umich.edu{ 180334SN/A BaseCPU::serialize(os); 181334SN/A// SERIALIZE_SCALAR(inst); 182334SN/A nameOut(os, csprintf("%s.xc.0", name())); 1832623SN/A thread->serialize(os); 1842SN/A} 1855496Ssaidi@eecs.umich.edu 186921SN/Avoid 1872915Sktlim@umich.eduBaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1882915Sktlim@umich.edu{ 1892683Sktlim@umich.edu BaseCPU::unserialize(cp, section); 1902SN/A// UNSERIALIZE_SCALAR(inst); 1912SN/A thread->unserialize(cp, csprintf("%s.xc.0", section)); 1922SN/A} 1932623SN/A 1942SN/Avoid 1955496Ssaidi@eecs.umich.educhange_thread_state(int thread_number, int activate, int priority) 196921SN/A{ 1972915Sktlim@umich.edu} 1982915Sktlim@umich.edu 1992SN/AFault 2002SN/ABaseSimpleCPU::copySrcTranslate(Addr src) 2012SN/A{ 2022SN/A#if 0 2032SN/A static bool no_warn = true; 2042SN/A int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 2052SN/A // Only support block sizes of 64 atm. 206595SN/A assert(blk_size == 64); 2072623SN/A int offset = src & (blk_size - 1); 208595SN/A 2092390SN/A // Make sure block doesn't span page 2101080SN/A if (no_warn && 2111080SN/A (src & PageMask) != ((src + blk_size) & PageMask) && 2121080SN/A (src >> 40) != 0xfffffc) { 2131080SN/A warn("Copied block source spans pages %x.", src); 2141080SN/A no_warn = false; 2151080SN/A } 2161080SN/A 2171121SN/A memReq->reset(src & ~(blk_size - 1), blk_size); 2182107SN/A 2191089SN/A // translate to physical address 2201089SN/A Fault fault = thread->translateDataReadReq(req); 2211080SN/A 2221080SN/A if (fault == NoFault) { 2231080SN/A thread->copySrcAddr = src; 2241080SN/A thread->copySrcPhysAddr = memReq->paddr + offset; 225595SN/A } else { 2262623SN/A assert(!fault->isAlignmentFault()); 2272683Sktlim@umich.edu 228595SN/A thread->copySrcAddr = 0; 2292090SN/A thread->copySrcPhysAddr = 0; 2302683Sktlim@umich.edu } 2312683Sktlim@umich.edu return fault; 232595SN/A#else 2332205SN/A return NoFault; 2342205SN/A#endif 2352683Sktlim@umich.edu} 2362683Sktlim@umich.edu 237595SN/AFault 238595SN/ABaseSimpleCPU::copy(Addr dest) 2392390SN/A{ 2402423SN/A#if 0 2412390SN/A static bool no_warn = true; 242595SN/A int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 243595SN/A // Only support block sizes of 64 atm. 244595SN/A assert(blk_size == 64); 2452623SN/A uint8_t data[blk_size]; 246595SN/A //assert(thread->copySrcAddr); 2472390SN/A int offset = dest & (blk_size - 1); 2481080SN/A 249595SN/A // Make sure block doesn't span page 2501080SN/A if (no_warn && 2511080SN/A (dest & PageMask) != ((dest + blk_size) & PageMask) && 252595SN/A (dest >> 40) != 0xfffffc) { 2532683Sktlim@umich.edu no_warn = false; 2541080SN/A warn("Copied block destination spans pages %x. ", dest); 2551080SN/A } 2561080SN/A 2571121SN/A memReq->reset(dest & ~(blk_size -1), blk_size); 2582107SN/A // translate to physical address 2591089SN/A Fault fault = thread->translateDataWriteReq(req); 2601080SN/A 2611089SN/A if (fault == NoFault) { 2621080SN/A Addr dest_addr = memReq->paddr + offset; 2631080SN/A // Need to read straight from memory since we have more than 8 bytes. 2641080SN/A memReq->paddr = thread->copySrcPhysAddr; 265595SN/A thread->mem->read(memReq, data); 2662683Sktlim@umich.edu memReq->paddr = dest_addr; 2671080SN/A thread->mem->write(memReq, data); 2682090SN/A if (dcacheInterface) { 2691080SN/A memReq->cmd = Copy; 270595SN/A memReq->completionEvent = NULL; 2712683Sktlim@umich.edu memReq->paddr = thread->copySrcPhysAddr; 2722683Sktlim@umich.edu memReq->dest = dest_addr; 273595SN/A memReq->size = 64; 2742683Sktlim@umich.edu memReq->time = curTick; 2751098SN/A memReq->flags &= ~INST_READ; 2761098SN/A dcacheInterface->access(memReq); 2771098SN/A } 2782683Sktlim@umich.edu } 2791098SN/A else 2801098SN/A assert(!fault->isAlignmentFault()); 2811098SN/A 2822012SN/A return fault; 2831098SN/A#else 2841098SN/A panic("copy not implemented"); 285595SN/A return NoFault; 2862205SN/A#endif 2872205SN/A} 2882205SN/A 289595SN/A#if FULL_SYSTEM 2902390SN/AAddr 2912420SN/ABaseSimpleCPU::dbg_vtophys(Addr addr) 2922423SN/A{ 2932390SN/A return vtophys(tc, addr); 294595SN/A} 295595SN/A#endif // FULL_SYSTEM 2961858SN/A 2972SN/A#if FULL_SYSTEM 2982623SN/Avoid 2992SN/ABaseSimpleCPU::post_interrupt(int int_num, int index) 3002680Sktlim@umich.edu{ 3012SN/A BaseCPU::post_interrupt(int_num, index); 3022SN/A 3032SN/A if (thread->status() == ThreadContext::Suspended) { 3041858SN/A DPRINTF(IPI,"Suspended Processor awoke\n"); 3052SN/A thread->activate(); 3062623SN/A } 3072SN/A} 3082SN/A#endif // FULL_SYSTEM 3092SN/A 3102683Sktlim@umich.eduvoid 3114216Ssaidi@eecs.umich.eduBaseSimpleCPU::checkForInterrupts() 3122683Sktlim@umich.edu{ 3132SN/A#if FULL_SYSTEM 3142SN/A if (checkInterrupts && check_interrupts() && !thread->inPalMode()) { 3152SN/A int ipl = 0; 3162SN/A int summary = 0; 3172SN/A checkInterrupts = false; 3182623SN/A 3192SN/A if (thread->readMiscReg(IPR_SIRR)) { 3201858SN/A for (int i = INTLEVEL_SOFTWARE_MIN; 3213923Shsul@eecs.umich.edu i < INTLEVEL_SOFTWARE_MAX; i++) { 3225647Sgblack@eecs.umich.edu if (thread->readMiscReg(IPR_SIRR) & (ULL(1) << i)) { 3232SN/A // See table 4-19 of 21164 hardware reference 3243520Sgblack@eecs.umich.edu ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; 3255647Sgblack@eecs.umich.edu summary |= (ULL(1) << i); 3263520Sgblack@eecs.umich.edu } 3272SN/A } 3282SN/A } 3292SN/A 3302623SN/A uint64_t interrupts = thread->cpu->intr_status(); 3312SN/A for (int i = INTLEVEL_EXTERNAL_MIN; 3322623SN/A i < INTLEVEL_EXTERNAL_MAX; i++) { 3332623SN/A if (interrupts & (ULL(1) << i)) { 3342662Sstever@eecs.umich.edu // See table 4-19 of 21164 hardware reference 3352623SN/A ipl = i; 3364514Ssaidi@eecs.umich.edu summary |= (ULL(1) << i); 3374495Sacolyte@umich.edu } 3382623SN/A } 3393093Sksewell@umich.edu 3404495Sacolyte@umich.edu if (thread->readMiscReg(IPR_ASTRR)) 3413093Sksewell@umich.edu panic("asynchronous traps not implemented\n"); 3423093Sksewell@umich.edu 3434564Sgblack@eecs.umich.edu if (ipl && ipl > thread->readMiscReg(IPR_IPLR)) { 3442741Sksewell@umich.edu thread->setMiscReg(IPR_ISR, summary); 3452741Sksewell@umich.edu thread->setMiscReg(IPR_INTID, ipl); 3462623SN/A 3474564Sgblack@eecs.umich.edu Fault(new InterruptFault)->invoke(tc); 3484564Sgblack@eecs.umich.edu 3492623SN/A DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", 3502683Sktlim@umich.edu thread->readMiscReg(IPR_IPLR), ipl, summary); 3512623SN/A } 3522623SN/A } 3532623SN/A#endif 3542623SN/A} 3552623SN/A 3562623SN/A 3572623SN/AFault 3582623SN/ABaseSimpleCPU::setupFetchRequest(Request *req) 3592SN/A{ 3602683Sktlim@umich.edu // set up memory request for instruction fetch 3612427SN/A#if ISA_HAS_DELAY_SLOT 3622683Sktlim@umich.edu DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",thread->readPC(), 3632427SN/A thread->readNextPC(),thread->readNextNPC()); 3642SN/A#else 3652623SN/A DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",thread->readPC(), 3662623SN/A thread->readNextPC()); 3672SN/A#endif 3682623SN/A 3692623SN/A req->setVirt(0, thread->readPC() & ~3, sizeof(MachInst), 3704377Sgblack@eecs.umich.edu (FULL_SYSTEM && (thread->readPC() & 1)) ? PHYSICAL : 0, 3713276Sgblack@eecs.umich.edu thread->readPC()); 3723276Sgblack@eecs.umich.edu 3734377Sgblack@eecs.umich.edu Fault fault = thread->translateInstReq(req); 3744181Sgblack@eecs.umich.edu 3754181Sgblack@eecs.umich.edu return fault; 3764181Sgblack@eecs.umich.edu} 3774182Sgblack@eecs.umich.edu 3784182Sgblack@eecs.umich.edu 3794182Sgblack@eecs.umich.eduvoid 3804593Sgblack@eecs.umich.eduBaseSimpleCPU::preExecute() 3814593Sgblack@eecs.umich.edu{ 3824593Sgblack@eecs.umich.edu // maintain $r0 semantics 3834593Sgblack@eecs.umich.edu thread->setIntReg(ZeroReg, 0); 3844593Sgblack@eecs.umich.edu#if THE_ISA == ALPHA_ISA 3854377Sgblack@eecs.umich.edu thread->setFloatReg(ZeroReg, 0.0); 3864377Sgblack@eecs.umich.edu#endif // ALPHA_ISA 3874377Sgblack@eecs.umich.edu 3884377Sgblack@eecs.umich.edu // keep an instruction count 3894377Sgblack@eecs.umich.edu numInst++; 3904377Sgblack@eecs.umich.edu numInsts++; 3914377Sgblack@eecs.umich.edu 3924377Sgblack@eecs.umich.edu thread->funcExeInst++; 3934572Sacolyte@umich.edu 3944572Sacolyte@umich.edu // check for instruction-count-based events 3954377Sgblack@eecs.umich.edu comInstEventQueue[0]->serviceEvents(numInst); 3964377Sgblack@eecs.umich.edu 3974377Sgblack@eecs.umich.edu // decode the instruction 3984377Sgblack@eecs.umich.edu inst = gtoh(inst); 3994181Sgblack@eecs.umich.edu //If we're not in the middle of a macro instruction 4004181Sgblack@eecs.umich.edu if (!curMacroStaticInst) { 4014181Sgblack@eecs.umich.edu StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->getTC())); 4024539Sgblack@eecs.umich.edu if (instPtr->isMacroOp()) { 4033276Sgblack@eecs.umich.edu curMacroStaticInst = instPtr; 4043442Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst->fetchMicroOp(0); 4054539Sgblack@eecs.umich.edu } else { 4063280Sgblack@eecs.umich.edu curStaticInst = instPtr; 4073280Sgblack@eecs.umich.edu } 4083276Sgblack@eecs.umich.edu } else { 4093276Sgblack@eecs.umich.edu //Read the next micro op from the macro op 4103276Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst->fetchMicroOp(thread->readMicroPC()); 4113442Sgblack@eecs.umich.edu } 4124539Sgblack@eecs.umich.edu 4133276Sgblack@eecs.umich.edu 4143276Sgblack@eecs.umich.edu traceData = Trace::getInstRecord(curTick, tc, curStaticInst, 4154181Sgblack@eecs.umich.edu thread->readPC()); 4164181Sgblack@eecs.umich.edu 4174181Sgblack@eecs.umich.edu DPRINTF(Decode,"Decode: Decoded %s instruction (opcode: 0x%x): 0x%x\n", 4184522Ssaidi@eecs.umich.edu curStaticInst->getName(), curStaticInst->getOpcode(), 4194776Sgblack@eecs.umich.edu curStaticInst->machInst); 4204181Sgblack@eecs.umich.edu 4212470SN/A#if FULL_SYSTEM 4224181Sgblack@eecs.umich.edu thread->setInst(inst); 4234181Sgblack@eecs.umich.edu#endif // FULL_SYSTEM 4244522Ssaidi@eecs.umich.edu} 4252623SN/A 4262623SN/Avoid 4274181Sgblack@eecs.umich.eduBaseSimpleCPU::postExecute() 4282623SN/A{ 4294181Sgblack@eecs.umich.edu#if FULL_SYSTEM 4302623SN/A if (thread->profile) { 4312623SN/A bool usermode = 4322623SN/A (thread->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; 4332623SN/A thread->profilePC = usermode ? 1 : thread->readPC(); 4342623SN/A ProfileNode *node = thread->profile->consume(tc, inst); 4352623SN/A if (node) 4365086Sgblack@eecs.umich.edu thread->profileNode = node; 4373577Sgblack@eecs.umich.edu } 4382683Sktlim@umich.edu#endif 4395086Sgblack@eecs.umich.edu 4402623SN/A if (curStaticInst->isMemRef()) { 4412683Sktlim@umich.edu numMemRefs++; 4422623SN/A } 4432420SN/A 4442SN/A if (curStaticInst->isLoad()) { 4452623SN/A ++numLoad; 4462623SN/A comLoadEventQueue[0]->serviceEvents(numLoad); 4472SN/A } 4482SN/A 4492623SN/A traceFunctions(thread->readPC()); 4502623SN/A 4512623SN/A if (traceData) { 4522623SN/A traceData->finalize(); 4532SN/A } 4542683Sktlim@umich.edu} 4552644Sstever@eecs.umich.edu 4562644Sstever@eecs.umich.edu 4574046Sbinkertn@umich.eduvoid 4584046Sbinkertn@umich.eduBaseSimpleCPU::advancePC(Fault fault) 4594046Sbinkertn@umich.edu{ 4602644Sstever@eecs.umich.edu if (fault != NoFault) { 4612623SN/A fault->invoke(tc); 4622SN/A } else { 4632SN/A //If we're at the last micro op for this instruction 4642623SN/A if (curStaticInst->isLastMicroOp()) { 4652623SN/A //We should be working with a macro op 4662623SN/A assert(curMacroStaticInst); 4674377Sgblack@eecs.umich.edu //Close out this macro op, and clean up the 4684377Sgblack@eecs.umich.edu //microcode state 4692090SN/A curMacroStaticInst = StaticInst::nullStaticInstPtr; 4703905Ssaidi@eecs.umich.edu thread->setMicroPC(0); 4715120Sgblack@eecs.umich.edu thread->setNextMicroPC(1); 4723929Ssaidi@eecs.umich.edu } 4733929Ssaidi@eecs.umich.edu //If we're still in a macro op 4745281Sgblack@eecs.umich.edu if (curMacroStaticInst) { 4754377Sgblack@eecs.umich.edu //Advance the micro pc 4763276Sgblack@eecs.umich.edu thread->setMicroPC(thread->readNextMicroPC()); 4774539Sgblack@eecs.umich.edu //Advance the "next" micro pc. Note that there are no delay 4783276Sgblack@eecs.umich.edu //slots, and micro ops are "word" addressed. 4793276Sgblack@eecs.umich.edu thread->setNextMicroPC(thread->readNextMicroPC() + 1); 4803276Sgblack@eecs.umich.edu } else { 4813276Sgblack@eecs.umich.edu // go to the next instruction 4823280Sgblack@eecs.umich.edu thread->setPC(thread->readNextPC()); 4833276Sgblack@eecs.umich.edu#if ISA_HAS_DELAY_SLOT 4843280Sgblack@eecs.umich.edu thread->setNextPC(thread->readNextNPC()); 4853276Sgblack@eecs.umich.edu thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst)); 4863276Sgblack@eecs.umich.edu assert(thread->readNextPC() != thread->readNextNPC()); 4873276Sgblack@eecs.umich.edu#else 4883276Sgblack@eecs.umich.edu thread->setNextPC(thread->readNextPC() + sizeof(MachInst)); 4893280Sgblack@eecs.umich.edu#endif 4903276Sgblack@eecs.umich.edu } 4913276Sgblack@eecs.umich.edu } 4923280Sgblack@eecs.umich.edu 4933276Sgblack@eecs.umich.edu#if FULL_SYSTEM 4943276Sgblack@eecs.umich.edu Addr oldpc; 4953276Sgblack@eecs.umich.edu do { 4963276Sgblack@eecs.umich.edu oldpc = thread->readPC(); 4973276Sgblack@eecs.umich.edu system->pcEventQueue.service(tc); 4983276Sgblack@eecs.umich.edu } while (oldpc != thread->readPC()); 4993276Sgblack@eecs.umich.edu#endif 5002SN/A} 5012SN/A 5022SN/A