base.cc revision 2935:d1223a6c9156
19259SAli.Saidi@ARM.com/* 29259SAli.Saidi@ARM.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 39259SAli.Saidi@ARM.com * All rights reserved. 49259SAli.Saidi@ARM.com * 59259SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 69259SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 79259SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 89259SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 99259SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 109259SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 119259SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 129259SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 139259SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 149259SAli.Saidi@ARM.com * this software without specific prior written permission. 159259SAli.Saidi@ARM.com * 169259SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 179259SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 189259SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 199259SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 209259SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 219259SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 229259SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 239259SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 249259SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 259259SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 269259SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 279259SAli.Saidi@ARM.com * 289259SAli.Saidi@ARM.com * Authors: Steve Reinhardt 299259SAli.Saidi@ARM.com */ 309259SAli.Saidi@ARM.com 319259SAli.Saidi@ARM.com#include "arch/utility.hh" 329259SAli.Saidi@ARM.com#include "base/cprintf.hh" 339259SAli.Saidi@ARM.com#include "base/inifile.hh" 349259SAli.Saidi@ARM.com#include "base/loader/symtab.hh" 359259SAli.Saidi@ARM.com#include "base/misc.hh" 369259SAli.Saidi@ARM.com#include "base/pollevent.hh" 379259SAli.Saidi@ARM.com#include "base/range.hh" 389259SAli.Saidi@ARM.com#include "base/stats/events.hh" 399259SAli.Saidi@ARM.com#include "base/trace.hh" 409259SAli.Saidi@ARM.com#include "cpu/base.hh" 419259SAli.Saidi@ARM.com#include "cpu/exetrace.hh" 429259SAli.Saidi@ARM.com#include "cpu/profile.hh" 439259SAli.Saidi@ARM.com#include "cpu/simple/base.hh" 449259SAli.Saidi@ARM.com#include "cpu/simple_thread.hh" 459259SAli.Saidi@ARM.com#include "cpu/smt.hh" 469259SAli.Saidi@ARM.com#include "cpu/static_inst.hh" 479259SAli.Saidi@ARM.com#include "cpu/thread_context.hh" 489259SAli.Saidi@ARM.com#include "kern/kernel_stats.hh" 499259SAli.Saidi@ARM.com#include "mem/packet_impl.hh" 509259SAli.Saidi@ARM.com#include "sim/builder.hh" 519259SAli.Saidi@ARM.com#include "sim/byteswap.hh" 529259SAli.Saidi@ARM.com#include "sim/debug.hh" 539259SAli.Saidi@ARM.com#include "sim/host.hh" 549259SAli.Saidi@ARM.com#include "sim/sim_events.hh" 559259SAli.Saidi@ARM.com#include "sim/sim_object.hh" 569259SAli.Saidi@ARM.com#include "sim/stats.hh" 579259SAli.Saidi@ARM.com#include "sim/system.hh" 589259SAli.Saidi@ARM.com 599259SAli.Saidi@ARM.com#if FULL_SYSTEM 609259SAli.Saidi@ARM.com#include "base/remote_gdb.hh" 619259SAli.Saidi@ARM.com#include "arch/tlb.hh" 629259SAli.Saidi@ARM.com#include "arch/stacktrace.hh" 639259SAli.Saidi@ARM.com#include "arch/vtophys.hh" 649259SAli.Saidi@ARM.com#else // !FULL_SYSTEM 6513784Sgabeblack@google.com#include "mem/mem_object.hh" 6613784Sgabeblack@google.com#endif // FULL_SYSTEM 679259SAli.Saidi@ARM.com 689259SAli.Saidi@ARM.comusing namespace std; 699259SAli.Saidi@ARM.comusing namespace TheISA; 709259SAli.Saidi@ARM.com 719259SAli.Saidi@ARM.comBaseSimpleCPU::BaseSimpleCPU(Params *p) 729259SAli.Saidi@ARM.com : BaseCPU(p), mem(p->mem), thread(NULL) 739259SAli.Saidi@ARM.com{ 749259SAli.Saidi@ARM.com#if FULL_SYSTEM 759259SAli.Saidi@ARM.com thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb); 769259SAli.Saidi@ARM.com#else 779259SAli.Saidi@ARM.com thread = new SimpleThread(this, /* thread_num */ 0, p->process, 789259SAli.Saidi@ARM.com /* asid */ 0, mem); 799259SAli.Saidi@ARM.com#endif // !FULL_SYSTEM 809259SAli.Saidi@ARM.com 819259SAli.Saidi@ARM.com thread->setStatus(ThreadContext::Suspended); 829259SAli.Saidi@ARM.com 839259SAli.Saidi@ARM.com tc = thread->getTC(); 849259SAli.Saidi@ARM.com 859259SAli.Saidi@ARM.com numInst = 0; 869259SAli.Saidi@ARM.com startNumInst = 0; 879542Sandreas.hansson@arm.com numLoad = 0; 889259SAli.Saidi@ARM.com startNumLoad = 0; 899259SAli.Saidi@ARM.com lastIcacheStall = 0; 909259SAli.Saidi@ARM.com lastDcacheStall = 0; 919542Sandreas.hansson@arm.com 929259SAli.Saidi@ARM.com threadContexts.push_back(tc); 939259SAli.Saidi@ARM.com} 949259SAli.Saidi@ARM.com 959259SAli.Saidi@ARM.comBaseSimpleCPU::~BaseSimpleCPU() 969259SAli.Saidi@ARM.com{ 979259SAli.Saidi@ARM.com} 989259SAli.Saidi@ARM.com 999259SAli.Saidi@ARM.comvoid 1009259SAli.Saidi@ARM.comBaseSimpleCPU::deallocateContext(int thread_num) 1019259SAli.Saidi@ARM.com{ 1029259SAli.Saidi@ARM.com // for now, these are equivalent 1039259SAli.Saidi@ARM.com suspendContext(thread_num); 1049259SAli.Saidi@ARM.com} 1059259SAli.Saidi@ARM.com 1069259SAli.Saidi@ARM.com 1079259SAli.Saidi@ARM.comvoid 1089259SAli.Saidi@ARM.comBaseSimpleCPU::haltContext(int thread_num) 1099259SAli.Saidi@ARM.com{ 1109259SAli.Saidi@ARM.com // for now, these are equivalent 1119259SAli.Saidi@ARM.com suspendContext(thread_num); 1129259SAli.Saidi@ARM.com} 1139259SAli.Saidi@ARM.com 1149259SAli.Saidi@ARM.com 1159259SAli.Saidi@ARM.comvoid 1169259SAli.Saidi@ARM.comBaseSimpleCPU::regStats() 1179259SAli.Saidi@ARM.com{ 1189259SAli.Saidi@ARM.com using namespace Stats; 1199259SAli.Saidi@ARM.com 1209259SAli.Saidi@ARM.com BaseCPU::regStats(); 1219259SAli.Saidi@ARM.com 1229259SAli.Saidi@ARM.com numInsts 1239259SAli.Saidi@ARM.com .name(name() + ".num_insts") 1249259SAli.Saidi@ARM.com .desc("Number of instructions executed") 1259259SAli.Saidi@ARM.com ; 1269259SAli.Saidi@ARM.com 1279259SAli.Saidi@ARM.com numMemRefs 1289259SAli.Saidi@ARM.com .name(name() + ".num_refs") 1299259SAli.Saidi@ARM.com .desc("Number of memory references") 1309259SAli.Saidi@ARM.com ; 1319259SAli.Saidi@ARM.com 1329259SAli.Saidi@ARM.com notIdleFraction 1339259SAli.Saidi@ARM.com .name(name() + ".not_idle_fraction") 1349259SAli.Saidi@ARM.com .desc("Percentage of non-idle cycles") 1359259SAli.Saidi@ARM.com ; 1369259SAli.Saidi@ARM.com 1379259SAli.Saidi@ARM.com idleFraction 1389259SAli.Saidi@ARM.com .name(name() + ".idle_fraction") 1399259SAli.Saidi@ARM.com .desc("Percentage of idle cycles") 1409259SAli.Saidi@ARM.com ; 1419259SAli.Saidi@ARM.com 1429259SAli.Saidi@ARM.com icacheStallCycles 14310713Sandreas.hansson@arm.com .name(name() + ".icache_stall_cycles") 1449259SAli.Saidi@ARM.com .desc("ICache total stall cycles") 14510713Sandreas.hansson@arm.com .prereq(icacheStallCycles) 1469259SAli.Saidi@ARM.com ; 1479259SAli.Saidi@ARM.com 1489259SAli.Saidi@ARM.com dcacheStallCycles 1499259SAli.Saidi@ARM.com .name(name() + ".dcache_stall_cycles") 1509259SAli.Saidi@ARM.com .desc("DCache total stall cycles") 1519259SAli.Saidi@ARM.com .prereq(dcacheStallCycles) 1529259SAli.Saidi@ARM.com ; 1539259SAli.Saidi@ARM.com 1549259SAli.Saidi@ARM.com icacheRetryCycles 1559259SAli.Saidi@ARM.com .name(name() + ".icache_retry_cycles") 1569259SAli.Saidi@ARM.com .desc("ICache total retry cycles") 1579259SAli.Saidi@ARM.com .prereq(icacheRetryCycles) 1589259SAli.Saidi@ARM.com ; 1599259SAli.Saidi@ARM.com 1609259SAli.Saidi@ARM.com dcacheRetryCycles 1619259SAli.Saidi@ARM.com .name(name() + ".dcache_retry_cycles") 1629259SAli.Saidi@ARM.com .desc("DCache total retry cycles") 1639259SAli.Saidi@ARM.com .prereq(dcacheRetryCycles) 1649259SAli.Saidi@ARM.com ; 1659259SAli.Saidi@ARM.com 1669259SAli.Saidi@ARM.com idleFraction = constant(1.0) - notIdleFraction; 1679259SAli.Saidi@ARM.com} 1689259SAli.Saidi@ARM.com 1699259SAli.Saidi@ARM.comvoid 1709259SAli.Saidi@ARM.comBaseSimpleCPU::resetStats() 1719259SAli.Saidi@ARM.com{ 1729259SAli.Saidi@ARM.com startNumInst = numInst; 1739259SAli.Saidi@ARM.com // notIdleFraction = (_status != Idle); 1749259SAli.Saidi@ARM.com} 1759259SAli.Saidi@ARM.com 1769259SAli.Saidi@ARM.comvoid 1779259SAli.Saidi@ARM.comBaseSimpleCPU::serialize(ostream &os) 1789259SAli.Saidi@ARM.com{ 1799259SAli.Saidi@ARM.com BaseCPU::serialize(os); 1809259SAli.Saidi@ARM.com// SERIALIZE_SCALAR(inst); 1819259SAli.Saidi@ARM.com nameOut(os, csprintf("%s.xc.0", name())); 1829259SAli.Saidi@ARM.com thread->serialize(os); 1839259SAli.Saidi@ARM.com} 1849259SAli.Saidi@ARM.com 1859259SAli.Saidi@ARM.comvoid 1869259SAli.Saidi@ARM.comBaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1879259SAli.Saidi@ARM.com{ 1889259SAli.Saidi@ARM.com BaseCPU::unserialize(cp, section); 1899259SAli.Saidi@ARM.com// UNSERIALIZE_SCALAR(inst); 1909259SAli.Saidi@ARM.com thread->unserialize(cp, csprintf("%s.xc.0", section)); 1919259SAli.Saidi@ARM.com} 1929259SAli.Saidi@ARM.com 19310713Sandreas.hansson@arm.comvoid 1949259SAli.Saidi@ARM.comchange_thread_state(int thread_number, int activate, int priority) 19510713Sandreas.hansson@arm.com{ 1969259SAli.Saidi@ARM.com} 1979259SAli.Saidi@ARM.com 1989259SAli.Saidi@ARM.comFault 1999259SAli.Saidi@ARM.comBaseSimpleCPU::copySrcTranslate(Addr src) 2009259SAli.Saidi@ARM.com{ 2019259SAli.Saidi@ARM.com#if 0 2029259SAli.Saidi@ARM.com static bool no_warn = true; 2039259SAli.Saidi@ARM.com int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 2049259SAli.Saidi@ARM.com // Only support block sizes of 64 atm. 2059259SAli.Saidi@ARM.com assert(blk_size == 64); 2069259SAli.Saidi@ARM.com int offset = src & (blk_size - 1); 2079259SAli.Saidi@ARM.com 2089259SAli.Saidi@ARM.com // Make sure block doesn't span page 2099259SAli.Saidi@ARM.com if (no_warn && 2109259SAli.Saidi@ARM.com (src & PageMask) != ((src + blk_size) & PageMask) && 2119259SAli.Saidi@ARM.com (src >> 40) != 0xfffffc) { 2129259SAli.Saidi@ARM.com warn("Copied block source spans pages %x.", src); 2139259SAli.Saidi@ARM.com no_warn = false; 2149259SAli.Saidi@ARM.com } 2159259SAli.Saidi@ARM.com 2169259SAli.Saidi@ARM.com memReq->reset(src & ~(blk_size - 1), blk_size); 2179259SAli.Saidi@ARM.com 2189259SAli.Saidi@ARM.com // translate to physical address 2199259SAli.Saidi@ARM.com Fault fault = thread->translateDataReadReq(req); 2209259SAli.Saidi@ARM.com 2219259SAli.Saidi@ARM.com if (fault == NoFault) { 2229259SAli.Saidi@ARM.com thread->copySrcAddr = src; 2239259SAli.Saidi@ARM.com thread->copySrcPhysAddr = memReq->paddr + offset; 2249259SAli.Saidi@ARM.com } else { 2259259SAli.Saidi@ARM.com assert(!fault->isAlignmentFault()); 2269259SAli.Saidi@ARM.com 22710713Sandreas.hansson@arm.com thread->copySrcAddr = 0; 2289259SAli.Saidi@ARM.com thread->copySrcPhysAddr = 0; 22910713Sandreas.hansson@arm.com } 2309259SAli.Saidi@ARM.com return fault; 2319259SAli.Saidi@ARM.com#else 2329259SAli.Saidi@ARM.com return NoFault; 2339259SAli.Saidi@ARM.com#endif 2349259SAli.Saidi@ARM.com} 2359259SAli.Saidi@ARM.com 2369259SAli.Saidi@ARM.comFault 2379259SAli.Saidi@ARM.comBaseSimpleCPU::copy(Addr dest) 2389259SAli.Saidi@ARM.com{ 2399259SAli.Saidi@ARM.com#if 0 2409259SAli.Saidi@ARM.com static bool no_warn = true; 2419259SAli.Saidi@ARM.com int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 2429259SAli.Saidi@ARM.com // Only support block sizes of 64 atm. 2439259SAli.Saidi@ARM.com assert(blk_size == 64); 2449259SAli.Saidi@ARM.com uint8_t data[blk_size]; 2459259SAli.Saidi@ARM.com //assert(thread->copySrcAddr); 2469259SAli.Saidi@ARM.com int offset = dest & (blk_size - 1); 2479259SAli.Saidi@ARM.com 2489259SAli.Saidi@ARM.com // Make sure block doesn't span page 2499259SAli.Saidi@ARM.com if (no_warn && 2509259SAli.Saidi@ARM.com (dest & PageMask) != ((dest + blk_size) & PageMask) && 2519259SAli.Saidi@ARM.com (dest >> 40) != 0xfffffc) { 2529259SAli.Saidi@ARM.com no_warn = false; 2539259SAli.Saidi@ARM.com warn("Copied block destination spans pages %x. ", dest); 2549259SAli.Saidi@ARM.com } 2559259SAli.Saidi@ARM.com 2569259SAli.Saidi@ARM.com memReq->reset(dest & ~(blk_size -1), blk_size); 2579259SAli.Saidi@ARM.com // translate to physical address 2589259SAli.Saidi@ARM.com Fault fault = thread->translateDataWriteReq(req); 2599259SAli.Saidi@ARM.com 2609259SAli.Saidi@ARM.com if (fault == NoFault) { 2619259SAli.Saidi@ARM.com Addr dest_addr = memReq->paddr + offset; 2629259SAli.Saidi@ARM.com // Need to read straight from memory since we have more than 8 bytes. 2639259SAli.Saidi@ARM.com memReq->paddr = thread->copySrcPhysAddr; 2649259SAli.Saidi@ARM.com thread->mem->read(memReq, data); 2659259SAli.Saidi@ARM.com memReq->paddr = dest_addr; 2669259SAli.Saidi@ARM.com thread->mem->write(memReq, data); 2679259SAli.Saidi@ARM.com if (dcacheInterface) { 2689259SAli.Saidi@ARM.com memReq->cmd = Copy; 2699259SAli.Saidi@ARM.com memReq->completionEvent = NULL; 2709259SAli.Saidi@ARM.com memReq->paddr = thread->copySrcPhysAddr; 271 memReq->dest = dest_addr; 272 memReq->size = 64; 273 memReq->time = curTick; 274 memReq->flags &= ~INST_READ; 275 dcacheInterface->access(memReq); 276 } 277 } 278 else 279 assert(!fault->isAlignmentFault()); 280 281 return fault; 282#else 283 panic("copy not implemented"); 284 return NoFault; 285#endif 286} 287 288#if FULL_SYSTEM 289Addr 290BaseSimpleCPU::dbg_vtophys(Addr addr) 291{ 292 return vtophys(tc, addr); 293} 294#endif // FULL_SYSTEM 295 296#if FULL_SYSTEM 297void 298BaseSimpleCPU::post_interrupt(int int_num, int index) 299{ 300 BaseCPU::post_interrupt(int_num, index); 301 302 if (thread->status() == ThreadContext::Suspended) { 303 DPRINTF(IPI,"Suspended Processor awoke\n"); 304 thread->activate(); 305 } 306} 307#endif // FULL_SYSTEM 308 309void 310BaseSimpleCPU::checkForInterrupts() 311{ 312#if FULL_SYSTEM 313 if (checkInterrupts && check_interrupts() && !thread->inPalMode()) { 314 int ipl = 0; 315 int summary = 0; 316 checkInterrupts = false; 317 318 if (thread->readMiscReg(IPR_SIRR)) { 319 for (int i = INTLEVEL_SOFTWARE_MIN; 320 i < INTLEVEL_SOFTWARE_MAX; i++) { 321 if (thread->readMiscReg(IPR_SIRR) & (ULL(1) << i)) { 322 // See table 4-19 of 21164 hardware reference 323 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; 324 summary |= (ULL(1) << i); 325 } 326 } 327 } 328 329 uint64_t interrupts = thread->cpu->intr_status(); 330 for (int i = INTLEVEL_EXTERNAL_MIN; 331 i < INTLEVEL_EXTERNAL_MAX; i++) { 332 if (interrupts & (ULL(1) << i)) { 333 // See table 4-19 of 21164 hardware reference 334 ipl = i; 335 summary |= (ULL(1) << i); 336 } 337 } 338 339 if (thread->readMiscReg(IPR_ASTRR)) 340 panic("asynchronous traps not implemented\n"); 341 342 if (ipl && ipl > thread->readMiscReg(IPR_IPLR)) { 343 thread->setMiscReg(IPR_ISR, summary); 344 thread->setMiscReg(IPR_INTID, ipl); 345 346 Fault(new InterruptFault)->invoke(tc); 347 348 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", 349 thread->readMiscReg(IPR_IPLR), ipl, summary); 350 } 351 } 352#endif 353} 354 355 356Fault 357BaseSimpleCPU::setupFetchRequest(Request *req) 358{ 359 // set up memory request for instruction fetch 360#if THE_ISA == ALPHA_ISA 361 DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",thread->readPC(), 362 thread->readNextPC()); 363#else 364 DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",thread->readPC(), 365 thread->readNextPC(),thread->readNextNPC()); 366#endif 367 368 req->setVirt(0, thread->readPC() & ~3, sizeof(MachInst), 369 (FULL_SYSTEM && (thread->readPC() & 1)) ? PHYSICAL : 0, 370 thread->readPC()); 371 372 Fault fault = thread->translateInstReq(req); 373 374 return fault; 375} 376 377 378void 379BaseSimpleCPU::preExecute() 380{ 381 // maintain $r0 semantics 382 thread->setIntReg(ZeroReg, 0); 383#if THE_ISA == ALPHA_ISA 384 thread->setFloatReg(ZeroReg, 0.0); 385#endif // ALPHA_ISA 386 387 // keep an instruction count 388 numInst++; 389 numInsts++; 390 391 thread->funcExeInst++; 392 393 // check for instruction-count-based events 394 comInstEventQueue[0]->serviceEvents(numInst); 395 396 // decode the instruction 397 inst = gtoh(inst); 398 curStaticInst = StaticInst::decode(makeExtMI(inst, thread->readPC())); 399 400 traceData = Trace::getInstRecord(curTick, tc, this, curStaticInst, 401 thread->readPC()); 402 403 DPRINTF(Decode,"Decode: Decoded %s instruction (opcode: 0x%x): 0x%x\n", 404 curStaticInst->getName(), curStaticInst->getOpcode(), 405 curStaticInst->machInst); 406 407#if FULL_SYSTEM 408 thread->setInst(inst); 409#endif // FULL_SYSTEM 410} 411 412void 413BaseSimpleCPU::postExecute() 414{ 415#if FULL_SYSTEM 416 if (thread->profile) { 417 bool usermode = 418 (thread->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; 419 thread->profilePC = usermode ? 1 : thread->readPC(); 420 ProfileNode *node = thread->profile->consume(tc, inst); 421 if (node) 422 thread->profileNode = node; 423 } 424#endif 425 426 if (curStaticInst->isMemRef()) { 427 numMemRefs++; 428 } 429 430 if (curStaticInst->isLoad()) { 431 ++numLoad; 432 comLoadEventQueue[0]->serviceEvents(numLoad); 433 } 434 435 traceFunctions(thread->readPC()); 436 437 if (traceData) { 438 traceData->finalize(); 439 } 440} 441 442 443void 444BaseSimpleCPU::advancePC(Fault fault) 445{ 446 if (fault != NoFault) { 447 fault->invoke(tc); 448 } 449 else { 450 // go to the next instruction 451 thread->setPC(thread->readNextPC()); 452#if THE_ISA == ALPHA_ISA 453 thread->setNextPC(thread->readNextPC() + sizeof(MachInst)); 454#else 455 thread->setNextPC(thread->readNextNPC()); 456 thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst)); 457 assert(thread->readNextPC() != thread->readNextNPC()); 458#endif 459 460 } 461 462#if FULL_SYSTEM 463 Addr oldpc; 464 do { 465 oldpc = thread->readPC(); 466 system->pcEventQueue.service(tc); 467 } while (oldpc != thread->readPC()); 468#endif 469} 470 471