base.cc revision 2012
13931Ssaidi@eecs.umich.edu/* 23388Sgblack@eecs.umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 33388Sgblack@eecs.umich.edu * All rights reserved. 43388Sgblack@eecs.umich.edu * 53388Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63388Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 73388Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83388Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93388Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103388Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113388Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123388Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133388Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143388Sgblack@eecs.umich.edu * this software without specific prior written permission. 153388Sgblack@eecs.umich.edu * 163388Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173388Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183388Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193388Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203388Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213388Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223388Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233388Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243388Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253388Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263388Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273388Sgblack@eecs.umich.edu */ 283388Sgblack@eecs.umich.edu 293388Sgblack@eecs.umich.edu#include <cmath> 303388Sgblack@eecs.umich.edu#include <cstdio> 313388Sgblack@eecs.umich.edu#include <cstdlib> 323388Sgblack@eecs.umich.edu#include <iostream> 333388Sgblack@eecs.umich.edu#include <iomanip> 343388Sgblack@eecs.umich.edu#include <list> 353388Sgblack@eecs.umich.edu#include <sstream> 363441Sgblack@eecs.umich.edu#include <string> 373441Sgblack@eecs.umich.edu 383441Sgblack@eecs.umich.edu#include "base/cprintf.hh" 393441Sgblack@eecs.umich.edu#include "base/inifile.hh" 403441Sgblack@eecs.umich.edu#include "base/loader/symtab.hh" 413441Sgblack@eecs.umich.edu#include "base/misc.hh" 423441Sgblack@eecs.umich.edu#include "base/pollevent.hh" 433441Sgblack@eecs.umich.edu#include "base/range.hh" 443441Sgblack@eecs.umich.edu#include "base/stats/events.hh" 453441Sgblack@eecs.umich.edu#include "base/trace.hh" 463441Sgblack@eecs.umich.edu#include "cpu/base.hh" 473441Sgblack@eecs.umich.edu#include "cpu/exec_context.hh" 483441Sgblack@eecs.umich.edu#include "cpu/exetrace.hh" 493441Sgblack@eecs.umich.edu#include "cpu/profile.hh" 503441Sgblack@eecs.umich.edu#include "cpu/sampler/sampler.hh" 513441Sgblack@eecs.umich.edu#include "cpu/simple/cpu.hh" 523441Sgblack@eecs.umich.edu#include "cpu/smt.hh" 533441Sgblack@eecs.umich.edu#include "cpu/static_inst.hh" 543441Sgblack@eecs.umich.edu#include "kern/kernel_stats.hh" 553441Sgblack@eecs.umich.edu#include "mem/base_mem.hh" 563441Sgblack@eecs.umich.edu#include "mem/mem_interface.hh" 573441Sgblack@eecs.umich.edu#include "sim/builder.hh" 583441Sgblack@eecs.umich.edu#include "sim/debug.hh" 593441Sgblack@eecs.umich.edu#include "sim/host.hh" 603441Sgblack@eecs.umich.edu#include "sim/sim_events.hh" 613441Sgblack@eecs.umich.edu#include "sim/sim_object.hh" 623441Sgblack@eecs.umich.edu#include "sim/stats.hh" 633441Sgblack@eecs.umich.edu 643441Sgblack@eecs.umich.edu#if FULL_SYSTEM 653441Sgblack@eecs.umich.edu#include "base/remote_gdb.hh" 663441Sgblack@eecs.umich.edu#include "mem/functional/memory_control.hh" 673441Sgblack@eecs.umich.edu#include "mem/functional/physical.hh" 683441Sgblack@eecs.umich.edu#include "sim/system.hh" 693441Sgblack@eecs.umich.edu#include "targetarch/alpha_memory.hh" 703441Sgblack@eecs.umich.edu#include "targetarch/stacktrace.hh" 713441Sgblack@eecs.umich.edu#include "targetarch/vtophys.hh" 723441Sgblack@eecs.umich.edu#else // !FULL_SYSTEM 733441Sgblack@eecs.umich.edu#include "mem/functional/functional.hh" 743441Sgblack@eecs.umich.edu#endif // FULL_SYSTEM 753441Sgblack@eecs.umich.edu 763441Sgblack@eecs.umich.eduusing namespace std; 773441Sgblack@eecs.umich.edu 783441Sgblack@eecs.umich.edu 793627Sgblack@eecs.umich.eduSimpleCPU::TickEvent::TickEvent(SimpleCPU *c, int w) 803441Sgblack@eecs.umich.edu : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), width(w) 813441Sgblack@eecs.umich.edu{ 823627Sgblack@eecs.umich.edu} 833441Sgblack@eecs.umich.edu 843627Sgblack@eecs.umich.eduvoid 853441Sgblack@eecs.umich.eduSimpleCPU::TickEvent::process() 863441Sgblack@eecs.umich.edu{ 873627Sgblack@eecs.umich.edu int count = width; 883627Sgblack@eecs.umich.edu do { 893627Sgblack@eecs.umich.edu cpu->tick(); 903627Sgblack@eecs.umich.edu } while (--count > 0 && cpu->status() == Running); 913627Sgblack@eecs.umich.edu} 923627Sgblack@eecs.umich.edu 933627Sgblack@eecs.umich.educonst char * 943627Sgblack@eecs.umich.eduSimpleCPU::TickEvent::description() 953441Sgblack@eecs.umich.edu{ 963441Sgblack@eecs.umich.edu return "SimpleCPU tick event"; 973441Sgblack@eecs.umich.edu} 983627Sgblack@eecs.umich.edu 993441Sgblack@eecs.umich.edu 1003441Sgblack@eecs.umich.eduSimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu) 1013441Sgblack@eecs.umich.edu : Event(&mainEventQueue), cpu(_cpu) 1023441Sgblack@eecs.umich.edu{ 1033441Sgblack@eecs.umich.edu} 1043441Sgblack@eecs.umich.edu 1053441Sgblack@eecs.umich.eduvoid SimpleCPU::CacheCompletionEvent::process() 1063441Sgblack@eecs.umich.edu{ 1073441Sgblack@eecs.umich.edu cpu->processCacheCompletion(); 1083441Sgblack@eecs.umich.edu} 1093441Sgblack@eecs.umich.edu 1103441Sgblack@eecs.umich.educonst char * 1113441Sgblack@eecs.umich.eduSimpleCPU::CacheCompletionEvent::description() 1123441Sgblack@eecs.umich.edu{ 1133441Sgblack@eecs.umich.edu return "SimpleCPU cache completion event"; 1143627Sgblack@eecs.umich.edu} 1153441Sgblack@eecs.umich.edu 1163441Sgblack@eecs.umich.eduSimpleCPU::SimpleCPU(Params *p) 1173627Sgblack@eecs.umich.edu : BaseCPU(p), tickEvent(this, p->width), xc(NULL), 1183627Sgblack@eecs.umich.edu cacheCompletionEvent(this) 1193627Sgblack@eecs.umich.edu{ 1203627Sgblack@eecs.umich.edu _status = Idle; 1213627Sgblack@eecs.umich.edu#if FULL_SYSTEM 1223627Sgblack@eecs.umich.edu xc = new ExecContext(this, 0, p->system, p->itb, p->dtb, p->mem); 1233441Sgblack@eecs.umich.edu 1243627Sgblack@eecs.umich.edu // initialize CPU, including PC 1253441Sgblack@eecs.umich.edu TheISA::initCPU(&xc->regs); 1263627Sgblack@eecs.umich.edu#else 1273441Sgblack@eecs.umich.edu xc = new ExecContext(this, /* thread_num */ 0, p->process, /* asid */ 0); 1283441Sgblack@eecs.umich.edu#endif // !FULL_SYSTEM 1293441Sgblack@eecs.umich.edu 1303627Sgblack@eecs.umich.edu icacheInterface = p->icache_interface; 1313441Sgblack@eecs.umich.edu dcacheInterface = p->dcache_interface; 1323441Sgblack@eecs.umich.edu 1333441Sgblack@eecs.umich.edu memReq = new MemReq(); 1343441Sgblack@eecs.umich.edu memReq->xc = xc; 1353441Sgblack@eecs.umich.edu memReq->asid = 0; 1363441Sgblack@eecs.umich.edu memReq->data = new uint8_t[64]; 1373388Sgblack@eecs.umich.edu 1383388Sgblack@eecs.umich.edu numInst = 0; 1393388Sgblack@eecs.umich.edu startNumInst = 0; 1403388Sgblack@eecs.umich.edu numLoad = 0; 1413388Sgblack@eecs.umich.edu startNumLoad = 0; 1423388Sgblack@eecs.umich.edu lastIcacheStall = 0; 1433388Sgblack@eecs.umich.edu lastDcacheStall = 0; 1443931Ssaidi@eecs.umich.edu 1453388Sgblack@eecs.umich.edu execContexts.push_back(xc); 1463388Sgblack@eecs.umich.edu} 1473388Sgblack@eecs.umich.edu 1483766Sgblack@eecs.umich.eduSimpleCPU::~SimpleCPU() 1493391Sgblack@eecs.umich.edu{ 1503391Sgblack@eecs.umich.edu} 1513391Sgblack@eecs.umich.edu 1524648Sgblack@eecs.umich.eduvoid 1534040Ssaidi@eecs.umich.eduSimpleCPU::switchOut(Sampler *s) 1543391Sgblack@eecs.umich.edu{ 1553391Sgblack@eecs.umich.edu sampler = s; 1563391Sgblack@eecs.umich.edu if (status() == DcacheMissStall) { 1573391Sgblack@eecs.umich.edu DPRINTF(Sampler,"Outstanding dcache access, waiting for completion\n"); 1583391Sgblack@eecs.umich.edu _status = DcacheMissSwitch; 1593388Sgblack@eecs.umich.edu } 1603388Sgblack@eecs.umich.edu else { 1613616Sgblack@eecs.umich.edu _status = SwitchedOut; 1623616Sgblack@eecs.umich.edu 1633388Sgblack@eecs.umich.edu if (tickEvent.scheduled()) 1643388Sgblack@eecs.umich.edu tickEvent.squash(); 1653388Sgblack@eecs.umich.edu 1663388Sgblack@eecs.umich.edu sampler->signalSwitched(); 1673792Sgblack@eecs.umich.edu } 1683388Sgblack@eecs.umich.edu} 1693792Sgblack@eecs.umich.edu 1703388Sgblack@eecs.umich.edu 1713388Sgblack@eecs.umich.eduvoid 1723388Sgblack@eecs.umich.eduSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1733388Sgblack@eecs.umich.edu{ 1743388Sgblack@eecs.umich.edu BaseCPU::takeOverFrom(oldCPU); 1753931Ssaidi@eecs.umich.edu 1763792Sgblack@eecs.umich.edu assert(!tickEvent.scheduled()); 1773792Sgblack@eecs.umich.edu 1783388Sgblack@eecs.umich.edu // if any of this CPU's ExecContexts are active, mark the CPU as 1793766Sgblack@eecs.umich.edu // running and schedule its tick event. 1803391Sgblack@eecs.umich.edu for (int i = 0; i < execContexts.size(); ++i) { 1813391Sgblack@eecs.umich.edu ExecContext *xc = execContexts[i]; 1823391Sgblack@eecs.umich.edu if (xc->status() == ExecContext::Active && _status != Running) { 1834648Sgblack@eecs.umich.edu _status = Running; 1844040Ssaidi@eecs.umich.edu tickEvent.schedule(curTick); 1853391Sgblack@eecs.umich.edu } 1863388Sgblack@eecs.umich.edu } 1873388Sgblack@eecs.umich.edu} 1883792Sgblack@eecs.umich.edu 1893388Sgblack@eecs.umich.edu 1903792Sgblack@eecs.umich.eduvoid 1913388Sgblack@eecs.umich.eduSimpleCPU::activateContext(int thread_num, int delay) 1923388Sgblack@eecs.umich.edu{ 1933388Sgblack@eecs.umich.edu assert(thread_num == 0); 1943388Sgblack@eecs.umich.edu assert(xc); 1953792Sgblack@eecs.umich.edu 1963792Sgblack@eecs.umich.edu assert(_status == Idle); 1973388Sgblack@eecs.umich.edu notIdleFraction++; 1983388Sgblack@eecs.umich.edu scheduleTickEvent(delay); 1993388Sgblack@eecs.umich.edu _status = Running; 2003388Sgblack@eecs.umich.edu} 2013792Sgblack@eecs.umich.edu 2023388Sgblack@eecs.umich.edu 2033388Sgblack@eecs.umich.eduvoid 2043388Sgblack@eecs.umich.eduSimpleCPU::suspendContext(int thread_num) 2053388Sgblack@eecs.umich.edu{ 2063388Sgblack@eecs.umich.edu assert(thread_num == 0); 2073388Sgblack@eecs.umich.edu assert(xc); 2083388Sgblack@eecs.umich.edu 2093388Sgblack@eecs.umich.edu assert(_status == Running); 2103388Sgblack@eecs.umich.edu notIdleFraction--; 2113388Sgblack@eecs.umich.edu unscheduleTickEvent(); 2123388Sgblack@eecs.umich.edu _status = Idle; 2133439Sgblack@eecs.umich.edu} 2143439Sgblack@eecs.umich.edu 2153439Sgblack@eecs.umich.edu 2163388Sgblack@eecs.umich.eduvoid 2173931Ssaidi@eecs.umich.eduSimpleCPU::deallocateContext(int thread_num) 2183388Sgblack@eecs.umich.edu{ 2193388Sgblack@eecs.umich.edu // for now, these are equivalent 2203388Sgblack@eecs.umich.edu suspendContext(thread_num); 2213766Sgblack@eecs.umich.edu} 2223391Sgblack@eecs.umich.edu 2233391Sgblack@eecs.umich.edu 2243391Sgblack@eecs.umich.eduvoid 2253391Sgblack@eecs.umich.eduSimpleCPU::haltContext(int thread_num) 2263391Sgblack@eecs.umich.edu{ 2273439Sgblack@eecs.umich.edu // for now, these are equivalent 2283388Sgblack@eecs.umich.edu suspendContext(thread_num); 2294648Sgblack@eecs.umich.edu} 2304224Sgblack@eecs.umich.edu 2313810Sgblack@eecs.umich.edu 2323388Sgblack@eecs.umich.eduvoid 2333388Sgblack@eecs.umich.eduSimpleCPU::regStats() 2343388Sgblack@eecs.umich.edu{ 2353616Sgblack@eecs.umich.edu using namespace Stats; 2363616Sgblack@eecs.umich.edu 2373388Sgblack@eecs.umich.edu BaseCPU::regStats(); 2383388Sgblack@eecs.umich.edu 2393388Sgblack@eecs.umich.edu numInsts 2403388Sgblack@eecs.umich.edu .name(name() + ".num_insts") 2413792Sgblack@eecs.umich.edu .desc("Number of instructions executed") 2423388Sgblack@eecs.umich.edu ; 2433792Sgblack@eecs.umich.edu 2443388Sgblack@eecs.umich.edu numMemRefs 2453388Sgblack@eecs.umich.edu .name(name() + ".num_refs") 2463388Sgblack@eecs.umich.edu .desc("Number of memory references") 2473388Sgblack@eecs.umich.edu ; 2483439Sgblack@eecs.umich.edu 2493388Sgblack@eecs.umich.edu notIdleFraction 2503931Ssaidi@eecs.umich.edu .name(name() + ".not_idle_fraction") 2513388Sgblack@eecs.umich.edu .desc("Percentage of non-idle cycles") 2524040Ssaidi@eecs.umich.edu ; 2533388Sgblack@eecs.umich.edu 2543388Sgblack@eecs.umich.edu idleFraction 2553766Sgblack@eecs.umich.edu .name(name() + ".idle_fraction") 2563391Sgblack@eecs.umich.edu .desc("Percentage of idle cycles") 2573391Sgblack@eecs.umich.edu ; 2583391Sgblack@eecs.umich.edu 2593391Sgblack@eecs.umich.edu icacheStallCycles 2603391Sgblack@eecs.umich.edu .name(name() + ".icache_stall_cycles") 2613439Sgblack@eecs.umich.edu .desc("ICache total stall cycles") 2623388Sgblack@eecs.umich.edu .prereq(icacheStallCycles) 2634648Sgblack@eecs.umich.edu ; 2644224Sgblack@eecs.umich.edu 2653810Sgblack@eecs.umich.edu dcacheStallCycles 2663388Sgblack@eecs.umich.edu .name(name() + ".dcache_stall_cycles") 2673388Sgblack@eecs.umich.edu .desc("DCache total stall cycles") 2683388Sgblack@eecs.umich.edu .prereq(dcacheStallCycles) 2693616Sgblack@eecs.umich.edu ; 2703388Sgblack@eecs.umich.edu 2713388Sgblack@eecs.umich.edu idleFraction = constant(1.0) - notIdleFraction; 2723388Sgblack@eecs.umich.edu} 2733388Sgblack@eecs.umich.edu 2743792Sgblack@eecs.umich.eduvoid 2753388Sgblack@eecs.umich.eduSimpleCPU::resetStats() 2763792Sgblack@eecs.umich.edu{ 2773388Sgblack@eecs.umich.edu startNumInst = numInst; 2783388Sgblack@eecs.umich.edu notIdleFraction = (_status != Idle); 2793388Sgblack@eecs.umich.edu} 2803388Sgblack@eecs.umich.edu 2813388Sgblack@eecs.umich.eduvoid 2823388Sgblack@eecs.umich.eduSimpleCPU::serialize(ostream &os) 2833388Sgblack@eecs.umich.edu{ 2843388Sgblack@eecs.umich.edu BaseCPU::serialize(os); 2853388Sgblack@eecs.umich.edu SERIALIZE_ENUM(_status); 2863388Sgblack@eecs.umich.edu SERIALIZE_SCALAR(inst); 2873388Sgblack@eecs.umich.edu nameOut(os, csprintf("%s.xc", name())); 2883388Sgblack@eecs.umich.edu xc->serialize(os); 2893388Sgblack@eecs.umich.edu nameOut(os, csprintf("%s.tickEvent", name())); 2903388Sgblack@eecs.umich.edu tickEvent.serialize(os); 2913388Sgblack@eecs.umich.edu nameOut(os, csprintf("%s.cacheCompletionEvent", name())); 2923388Sgblack@eecs.umich.edu cacheCompletionEvent.serialize(os); 2933388Sgblack@eecs.umich.edu} 2943391Sgblack@eecs.umich.edu 2953391Sgblack@eecs.umich.eduvoid 2963792Sgblack@eecs.umich.eduSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 2973792Sgblack@eecs.umich.edu{ 2984040Ssaidi@eecs.umich.edu BaseCPU::unserialize(cp, section); 2993391Sgblack@eecs.umich.edu UNSERIALIZE_ENUM(_status); 3003391Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(inst); 3013391Sgblack@eecs.umich.edu xc->unserialize(cp, csprintf("%s.xc", section)); 3023391Sgblack@eecs.umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 3033391Sgblack@eecs.umich.edu cacheCompletionEvent 3043391Sgblack@eecs.umich.edu .unserialize(cp, csprintf("%s.cacheCompletionEvent", section)); 3053391Sgblack@eecs.umich.edu} 3063391Sgblack@eecs.umich.edu 3073835Sgblack@eecs.umich.eduvoid 3083863Ssaidi@eecs.umich.educhange_thread_state(int thread_number, int activate, int priority) 3093835Sgblack@eecs.umich.edu{ 3103863Ssaidi@eecs.umich.edu} 3113835Sgblack@eecs.umich.edu 3123835Sgblack@eecs.umich.eduFault 3133391Sgblack@eecs.umich.eduSimpleCPU::copySrcTranslate(Addr src) 3143391Sgblack@eecs.umich.edu{ 3153391Sgblack@eecs.umich.edu static bool no_warn = true; 3163391Sgblack@eecs.umich.edu int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 3173823Ssaidi@eecs.umich.edu // Only support block sizes of 64 atm. 3183823Ssaidi@eecs.umich.edu assert(blk_size == 64); 3193823Ssaidi@eecs.umich.edu int offset = src & (blk_size - 1); 3203391Sgblack@eecs.umich.edu 3213391Sgblack@eecs.umich.edu // Make sure block doesn't span page 3223391Sgblack@eecs.umich.edu if (no_warn && 3233391Sgblack@eecs.umich.edu (src & TheISA::PageMask) != ((src + blk_size) & TheISA::PageMask) && 3244648Sgblack@eecs.umich.edu (src >> 40) != 0xfffffc) { 3254648Sgblack@eecs.umich.edu warn("Copied block source spans pages %x.", src); 3264648Sgblack@eecs.umich.edu no_warn = false; 3274648Sgblack@eecs.umich.edu } 3284648Sgblack@eecs.umich.edu 3293391Sgblack@eecs.umich.edu memReq->reset(src & ~(blk_size - 1), blk_size); 3303391Sgblack@eecs.umich.edu 3313391Sgblack@eecs.umich.edu // translate to physical address 3323391Sgblack@eecs.umich.edu Fault fault = xc->translateDataReadReq(memReq); 3333391Sgblack@eecs.umich.edu 3343391Sgblack@eecs.umich.edu assert(fault != Alignment_Fault); 3353616Sgblack@eecs.umich.edu 3363391Sgblack@eecs.umich.edu if (fault == No_Fault) { 3373391Sgblack@eecs.umich.edu xc->copySrcAddr = src; 3383388Sgblack@eecs.umich.edu xc->copySrcPhysAddr = memReq->paddr + offset; 3393388Sgblack@eecs.umich.edu } else { 3403391Sgblack@eecs.umich.edu xc->copySrcAddr = 0; 3413388Sgblack@eecs.umich.edu xc->copySrcPhysAddr = 0; 3423388Sgblack@eecs.umich.edu } 3433388Sgblack@eecs.umich.edu return fault; 3443949Sgblack@eecs.umich.edu} 3453810Sgblack@eecs.umich.edu 3463792Sgblack@eecs.umich.eduFault 3473792Sgblack@eecs.umich.eduSimpleCPU::copy(Addr dest) 3483792Sgblack@eecs.umich.edu{ 3493439Sgblack@eecs.umich.edu static bool no_warn = true; 3503439Sgblack@eecs.umich.edu int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 3514040Ssaidi@eecs.umich.edu // Only support block sizes of 64 atm. 3523810Sgblack@eecs.umich.edu assert(blk_size == 64); 3533388Sgblack@eecs.umich.edu uint8_t data[blk_size]; 3543388Sgblack@eecs.umich.edu //assert(xc->copySrcAddr); 3553388Sgblack@eecs.umich.edu int offset = dest & (blk_size - 1); 3563388Sgblack@eecs.umich.edu 3574040Ssaidi@eecs.umich.edu // Make sure block doesn't span page 3584648Sgblack@eecs.umich.edu if (no_warn && 3594648Sgblack@eecs.umich.edu (dest & TheISA::PageMask) != ((dest + blk_size) & TheISA::PageMask) && 3603792Sgblack@eecs.umich.edu (dest >> 40) != 0xfffffc) { 3613810Sgblack@eecs.umich.edu no_warn = false; 3623388Sgblack@eecs.umich.edu warn("Copied block destination spans pages %x. ", dest); 3633388Sgblack@eecs.umich.edu } 364 365 memReq->reset(dest & ~(blk_size -1), blk_size); 366 // translate to physical address 367 Fault fault = xc->translateDataWriteReq(memReq); 368 369 assert(fault != Alignment_Fault); 370 371 if (fault == No_Fault) { 372 Addr dest_addr = memReq->paddr + offset; 373 // Need to read straight from memory since we have more than 8 bytes. 374 memReq->paddr = xc->copySrcPhysAddr; 375 xc->mem->read(memReq, data); 376 memReq->paddr = dest_addr; 377 xc->mem->write(memReq, data); 378 if (dcacheInterface) { 379 memReq->cmd = Copy; 380 memReq->completionEvent = NULL; 381 memReq->paddr = xc->copySrcPhysAddr; 382 memReq->dest = dest_addr; 383 memReq->size = 64; 384 memReq->time = curTick; 385 memReq->flags &= ~INST_READ; 386 dcacheInterface->access(memReq); 387 } 388 } 389 return fault; 390} 391 392// precise architected memory state accessor macros 393template <class T> 394Fault 395SimpleCPU::read(Addr addr, T &data, unsigned flags) 396{ 397 if (status() == DcacheMissStall || status() == DcacheMissSwitch) { 398 Fault fault = xc->read(memReq,data); 399 400 if (traceData) { 401 traceData->setAddr(addr); 402 } 403 return fault; 404 } 405 406 memReq->reset(addr, sizeof(T), flags); 407 408 // translate to physical address 409 Fault fault = xc->translateDataReadReq(memReq); 410 411 // if we have a cache, do cache access too 412 if (fault == No_Fault && dcacheInterface) { 413 memReq->cmd = Read; 414 memReq->completionEvent = NULL; 415 memReq->time = curTick; 416 memReq->flags &= ~INST_READ; 417 MemAccessResult result = dcacheInterface->access(memReq); 418 419 // Ugly hack to get an event scheduled *only* if the access is 420 // a miss. We really should add first-class support for this 421 // at some point. 422 if (result != MA_HIT && dcacheInterface->doEvents()) { 423 memReq->completionEvent = &cacheCompletionEvent; 424 lastDcacheStall = curTick; 425 unscheduleTickEvent(); 426 _status = DcacheMissStall; 427 } else { 428 // do functional access 429 fault = xc->read(memReq, data); 430 431 } 432 } else if(fault == No_Fault) { 433 // do functional access 434 fault = xc->read(memReq, data); 435 436 } 437 438 if (!dcacheInterface && (memReq->flags & UNCACHEABLE)) 439 recordEvent("Uncached Read"); 440 441 return fault; 442} 443 444#ifndef DOXYGEN_SHOULD_SKIP_THIS 445 446template 447Fault 448SimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 449 450template 451Fault 452SimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 453 454template 455Fault 456SimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 457 458template 459Fault 460SimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 461 462#endif //DOXYGEN_SHOULD_SKIP_THIS 463 464template<> 465Fault 466SimpleCPU::read(Addr addr, double &data, unsigned flags) 467{ 468 return read(addr, *(uint64_t*)&data, flags); 469} 470 471template<> 472Fault 473SimpleCPU::read(Addr addr, float &data, unsigned flags) 474{ 475 return read(addr, *(uint32_t*)&data, flags); 476} 477 478 479template<> 480Fault 481SimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 482{ 483 return read(addr, (uint32_t&)data, flags); 484} 485 486 487template <class T> 488Fault 489SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 490{ 491 memReq->reset(addr, sizeof(T), flags); 492 493 // translate to physical address 494 Fault fault = xc->translateDataWriteReq(memReq); 495 496 // do functional access 497 if (fault == No_Fault) 498 fault = xc->write(memReq, data); 499 500 if (fault == No_Fault && dcacheInterface) { 501 memReq->cmd = Write; 502 memcpy(memReq->data,(uint8_t *)&data,memReq->size); 503 memReq->completionEvent = NULL; 504 memReq->time = curTick; 505 memReq->flags &= ~INST_READ; 506 MemAccessResult result = dcacheInterface->access(memReq); 507 508 // Ugly hack to get an event scheduled *only* if the access is 509 // a miss. We really should add first-class support for this 510 // at some point. 511 if (result != MA_HIT && dcacheInterface->doEvents()) { 512 memReq->completionEvent = &cacheCompletionEvent; 513 lastDcacheStall = curTick; 514 unscheduleTickEvent(); 515 _status = DcacheMissStall; 516 } 517 } 518 519 if (res && (fault == No_Fault)) 520 *res = memReq->result; 521 522 if (!dcacheInterface && (memReq->flags & UNCACHEABLE)) 523 recordEvent("Uncached Write"); 524 525 return fault; 526} 527 528 529#ifndef DOXYGEN_SHOULD_SKIP_THIS 530template 531Fault 532SimpleCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res); 533 534template 535Fault 536SimpleCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res); 537 538template 539Fault 540SimpleCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res); 541 542template 543Fault 544SimpleCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res); 545 546#endif //DOXYGEN_SHOULD_SKIP_THIS 547 548template<> 549Fault 550SimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 551{ 552 return write(*(uint64_t*)&data, addr, flags, res); 553} 554 555template<> 556Fault 557SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 558{ 559 return write(*(uint32_t*)&data, addr, flags, res); 560} 561 562 563template<> 564Fault 565SimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 566{ 567 return write((uint32_t)data, addr, flags, res); 568} 569 570 571#if FULL_SYSTEM 572Addr 573SimpleCPU::dbg_vtophys(Addr addr) 574{ 575 return vtophys(xc, addr); 576} 577#endif // FULL_SYSTEM 578 579void 580SimpleCPU::processCacheCompletion() 581{ 582 switch (status()) { 583 case IcacheMissStall: 584 icacheStallCycles += curTick - lastIcacheStall; 585 _status = IcacheMissComplete; 586 scheduleTickEvent(1); 587 break; 588 case DcacheMissStall: 589 if (memReq->cmd.isRead()) { 590 curStaticInst->execute(this,traceData); 591 if (traceData) 592 traceData->finalize(); 593 } 594 dcacheStallCycles += curTick - lastDcacheStall; 595 _status = Running; 596 scheduleTickEvent(1); 597 break; 598 case DcacheMissSwitch: 599 if (memReq->cmd.isRead()) { 600 curStaticInst->execute(this,traceData); 601 if (traceData) 602 traceData->finalize(); 603 } 604 _status = SwitchedOut; 605 sampler->signalSwitched(); 606 case SwitchedOut: 607 // If this CPU has been switched out due to sampling/warm-up, 608 // ignore any further status changes (e.g., due to cache 609 // misses outstanding at the time of the switch). 610 return; 611 default: 612 panic("SimpleCPU::processCacheCompletion: bad state"); 613 break; 614 } 615} 616 617#if FULL_SYSTEM 618void 619SimpleCPU::post_interrupt(int int_num, int index) 620{ 621 BaseCPU::post_interrupt(int_num, index); 622 623 if (xc->status() == ExecContext::Suspended) { 624 DPRINTF(IPI,"Suspended Processor awoke\n"); 625 xc->activate(); 626 } 627} 628#endif // FULL_SYSTEM 629 630/* start simulation, program loaded, processor precise state initialized */ 631void 632SimpleCPU::tick() 633{ 634 numCycles++; 635 636 traceData = NULL; 637 638 Fault fault = No_Fault; 639 640#if FULL_SYSTEM 641 if (checkInterrupts && check_interrupts() && !xc->inPalMode() && 642 status() != IcacheMissComplete) { 643 int ipl = 0; 644 int summary = 0; 645 checkInterrupts = false; 646 IntReg *ipr = xc->regs.ipr; 647 648 if (xc->regs.ipr[TheISA::IPR_SIRR]) { 649 for (int i = TheISA::INTLEVEL_SOFTWARE_MIN; 650 i < TheISA::INTLEVEL_SOFTWARE_MAX; i++) { 651 if (ipr[TheISA::IPR_SIRR] & (ULL(1) << i)) { 652 // See table 4-19 of 21164 hardware reference 653 ipl = (i - TheISA::INTLEVEL_SOFTWARE_MIN) + 1; 654 summary |= (ULL(1) << i); 655 } 656 } 657 } 658 659 uint64_t interrupts = xc->cpu->intr_status(); 660 for (int i = TheISA::INTLEVEL_EXTERNAL_MIN; 661 i < TheISA::INTLEVEL_EXTERNAL_MAX; i++) { 662 if (interrupts & (ULL(1) << i)) { 663 // See table 4-19 of 21164 hardware reference 664 ipl = i; 665 summary |= (ULL(1) << i); 666 } 667 } 668 669 if (ipr[TheISA::IPR_ASTRR]) 670 panic("asynchronous traps not implemented\n"); 671 672 if (ipl && ipl > xc->regs.ipr[TheISA::IPR_IPLR]) { 673 ipr[TheISA::IPR_ISR] = summary; 674 ipr[TheISA::IPR_INTID] = ipl; 675 xc->ev5_trap(Interrupt_Fault); 676 677 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", 678 ipr[TheISA::IPR_IPLR], ipl, summary); 679 } 680 } 681#endif 682 683 // maintain $r0 semantics 684 xc->regs.intRegFile[ZeroReg] = 0; 685#ifdef TARGET_ALPHA 686 xc->regs.floatRegFile.d[ZeroReg] = 0.0; 687#endif // TARGET_ALPHA 688 689 if (status() == IcacheMissComplete) { 690 // We've already fetched an instruction and were stalled on an 691 // I-cache miss. No need to fetch it again. 692 693 // Set status to running; tick event will get rescheduled if 694 // necessary at end of tick() function. 695 _status = Running; 696 } 697 else { 698 // Try to fetch an instruction 699 700 // set up memory request for instruction fetch 701#if FULL_SYSTEM 702#define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0 703#else 704#define IFETCH_FLAGS(pc) 0 705#endif 706 707 memReq->cmd = Read; 708 memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t), 709 IFETCH_FLAGS(xc->regs.pc)); 710 711 fault = xc->translateInstReq(memReq); 712 713 if (fault == No_Fault) 714 fault = xc->mem->read(memReq, inst); 715 716 if (icacheInterface && fault == No_Fault) { 717 memReq->completionEvent = NULL; 718 719 memReq->time = curTick; 720 memReq->flags |= INST_READ; 721 MemAccessResult result = icacheInterface->access(memReq); 722 723 // Ugly hack to get an event scheduled *only* if the access is 724 // a miss. We really should add first-class support for this 725 // at some point. 726 if (result != MA_HIT && icacheInterface->doEvents()) { 727 memReq->completionEvent = &cacheCompletionEvent; 728 lastIcacheStall = curTick; 729 unscheduleTickEvent(); 730 _status = IcacheMissStall; 731 return; 732 } 733 } 734 } 735 736 // If we've got a valid instruction (i.e., no fault on instruction 737 // fetch), then execute it. 738 if (fault == No_Fault) { 739 740 // keep an instruction count 741 numInst++; 742 numInsts++; 743 744 // check for instruction-count-based events 745 comInstEventQueue[0]->serviceEvents(numInst); 746 747 // decode the instruction 748 inst = gtoh(inst); 749 curStaticInst = StaticInst<TheISA>::decode(inst); 750 751 traceData = Trace::getInstRecord(curTick, xc, this, curStaticInst, 752 xc->regs.pc); 753 754#if FULL_SYSTEM 755 xc->setInst(inst); 756#endif // FULL_SYSTEM 757 758 xc->func_exe_inst++; 759 760 fault = curStaticInst->execute(this, traceData); 761 762#if FULL_SYSTEM 763 if (xc->fnbin) { 764 assert(xc->kernelStats); 765 system->kernelBinning->execute(xc, inst); 766 } 767 768 if (xc->profile) { 769 bool usermode = (xc->regs.ipr[AlphaISA::IPR_DTB_CM] & 0x18) != 0; 770 xc->profilePC = usermode ? 1 : xc->regs.pc; 771 ProfileNode *node = xc->profile->consume(xc, inst); 772 if (node) 773 xc->profileNode = node; 774 } 775#endif 776 777 if (curStaticInst->isMemRef()) { 778 numMemRefs++; 779 } 780 781 if (curStaticInst->isLoad()) { 782 ++numLoad; 783 comLoadEventQueue[0]->serviceEvents(numLoad); 784 } 785 786 // If we have a dcache miss, then we can't finialize the instruction 787 // trace yet because we want to populate it with the data later 788 if (traceData && 789 !(status() == DcacheMissStall && memReq->cmd.isRead())) { 790 traceData->finalize(); 791 } 792 793 traceFunctions(xc->regs.pc); 794 795 } // if (fault == No_Fault) 796 797 if (fault != No_Fault) { 798#if FULL_SYSTEM 799 xc->ev5_trap(fault); 800#else // !FULL_SYSTEM 801 fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc); 802#endif // FULL_SYSTEM 803 } 804 else { 805 // go to the next instruction 806 xc->regs.pc = xc->regs.npc; 807 xc->regs.npc += sizeof(MachInst); 808 } 809 810#if FULL_SYSTEM 811 Addr oldpc; 812 do { 813 oldpc = xc->regs.pc; 814 system->pcEventQueue.service(xc); 815 } while (oldpc != xc->regs.pc); 816#endif 817 818 assert(status() == Running || 819 status() == Idle || 820 status() == DcacheMissStall); 821 822 if (status() == Running && !tickEvent.scheduled()) 823 tickEvent.schedule(curTick + cycles(1)); 824} 825 826//////////////////////////////////////////////////////////////////////// 827// 828// SimpleCPU Simulation Object 829// 830BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU) 831 832 Param<Counter> max_insts_any_thread; 833 Param<Counter> max_insts_all_threads; 834 Param<Counter> max_loads_any_thread; 835 Param<Counter> max_loads_all_threads; 836 837#if FULL_SYSTEM 838 SimObjectParam<AlphaITB *> itb; 839 SimObjectParam<AlphaDTB *> dtb; 840 SimObjectParam<FunctionalMemory *> mem; 841 SimObjectParam<System *> system; 842 Param<int> cpu_id; 843 Param<Tick> profile; 844#else 845 SimObjectParam<Process *> workload; 846#endif // FULL_SYSTEM 847 848 Param<int> clock; 849 SimObjectParam<BaseMem *> icache; 850 SimObjectParam<BaseMem *> dcache; 851 852 Param<bool> defer_registration; 853 Param<int> width; 854 Param<bool> function_trace; 855 Param<Tick> function_trace_start; 856 857END_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU) 858 859BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU) 860 861 INIT_PARAM(max_insts_any_thread, 862 "terminate when any thread reaches this inst count"), 863 INIT_PARAM(max_insts_all_threads, 864 "terminate when all threads have reached this inst count"), 865 INIT_PARAM(max_loads_any_thread, 866 "terminate when any thread reaches this load count"), 867 INIT_PARAM(max_loads_all_threads, 868 "terminate when all threads have reached this load count"), 869 870#if FULL_SYSTEM 871 INIT_PARAM(itb, "Instruction TLB"), 872 INIT_PARAM(dtb, "Data TLB"), 873 INIT_PARAM(mem, "memory"), 874 INIT_PARAM(system, "system object"), 875 INIT_PARAM(cpu_id, "processor ID"), 876 INIT_PARAM(profile, ""), 877#else 878 INIT_PARAM(workload, "processes to run"), 879#endif // FULL_SYSTEM 880 881 INIT_PARAM(clock, "clock speed"), 882 INIT_PARAM(icache, "L1 instruction cache object"), 883 INIT_PARAM(dcache, "L1 data cache object"), 884 INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 885 INIT_PARAM(width, "cpu width"), 886 INIT_PARAM(function_trace, "Enable function trace"), 887 INIT_PARAM(function_trace_start, "Cycle to start function trace") 888 889END_INIT_SIM_OBJECT_PARAMS(SimpleCPU) 890 891 892CREATE_SIM_OBJECT(SimpleCPU) 893{ 894 SimpleCPU::Params *params = new SimpleCPU::Params(); 895 params->name = getInstanceName(); 896 params->numberOfThreads = 1; 897 params->max_insts_any_thread = max_insts_any_thread; 898 params->max_insts_all_threads = max_insts_all_threads; 899 params->max_loads_any_thread = max_loads_any_thread; 900 params->max_loads_all_threads = max_loads_all_threads; 901 params->deferRegistration = defer_registration; 902 params->clock = clock; 903 params->functionTrace = function_trace; 904 params->functionTraceStart = function_trace_start; 905 params->icache_interface = (icache) ? icache->getInterface() : NULL; 906 params->dcache_interface = (dcache) ? dcache->getInterface() : NULL; 907 params->width = width; 908 909#if FULL_SYSTEM 910 params->itb = itb; 911 params->dtb = dtb; 912 params->mem = mem; 913 params->system = system; 914 params->cpu_id = cpu_id; 915 params->profile = profile; 916#else 917 params->process = workload; 918#endif 919 920 SimpleCPU *cpu = new SimpleCPU(params); 921 return cpu; 922} 923 924REGISTER_SIM_OBJECT("SimpleCPU", SimpleCPU) 925 926