base.cc revision 12110
1/* 2 * Copyright (c) 2010-2012,2015 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2002-2005 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 */ 43 44#include "cpu/simple/base.hh" 45 46#include "arch/kernel_stats.hh" 47#include "arch/stacktrace.hh" 48#include "arch/tlb.hh" 49#include "arch/utility.hh" 50#include "arch/vtophys.hh" 51#include "base/cp_annotate.hh" 52#include "base/cprintf.hh" 53#include "base/inifile.hh" 54#include "base/loader/symtab.hh" 55#include "base/misc.hh" 56#include "base/pollevent.hh" 57#include "base/trace.hh" 58#include "base/types.hh" 59#include "config/the_isa.hh" 60#include "cpu/base.hh" 61#include "cpu/checker/cpu.hh" 62#include "cpu/checker/thread_context.hh" 63#include "cpu/exetrace.hh" 64#include "cpu/pred/bpred_unit.hh" 65#include "cpu/profile.hh" 66#include "cpu/simple/exec_context.hh" 67#include "cpu/simple_thread.hh" 68#include "cpu/smt.hh" 69#include "cpu/static_inst.hh" 70#include "cpu/thread_context.hh" 71#include "debug/Decode.hh" 72#include "debug/Fetch.hh" 73#include "debug/Quiesce.hh" 74#include "mem/mem_object.hh" 75#include "mem/packet.hh" 76#include "mem/request.hh" 77#include "params/BaseSimpleCPU.hh" 78#include "sim/byteswap.hh" 79#include "sim/debug.hh" 80#include "sim/faults.hh" 81#include "sim/full_system.hh" 82#include "sim/sim_events.hh" 83#include "sim/sim_object.hh" 84#include "sim/stats.hh" 85#include "sim/system.hh" 86 87using namespace std; 88using namespace TheISA; 89 90BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p) 91 : BaseCPU(p), 92 curThread(0), 93 branchPred(p->branchPred), 94 traceData(NULL), 95 inst(), 96 _status(Idle) 97{ 98 SimpleThread *thread; 99 100 for (unsigned i = 0; i < numThreads; i++) { 101 if (FullSystem) { 102 thread = new SimpleThread(this, i, p->system, 103 p->itb, p->dtb, p->isa[i]); 104 } else { 105 thread = new SimpleThread(this, i, p->system, p->workload[i], 106 p->itb, p->dtb, p->isa[i]); 107 } 108 threadInfo.push_back(new SimpleExecContext(this, thread)); 109 ThreadContext *tc = thread->getTC(); 110 threadContexts.push_back(tc); 111 } 112 113 if (p->checker) { 114 if (numThreads != 1) 115 fatal("Checker currently does not support SMT"); 116 117 BaseCPU *temp_checker = p->checker; 118 checker = dynamic_cast<CheckerCPU *>(temp_checker); 119 checker->setSystem(p->system); 120 // Manipulate thread context 121 ThreadContext *cpu_tc = threadContexts[0]; 122 threadContexts[0] = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker); 123 } else { 124 checker = NULL; 125 } 126} 127 128void 129BaseSimpleCPU::init() 130{ 131 BaseCPU::init(); 132 133 for (auto tc : threadContexts) { 134 // Initialise the ThreadContext's memory proxies 135 tc->initMemProxies(tc); 136 137 if (FullSystem && !params()->switched_out) { 138 // initialize CPU, including PC 139 TheISA::initCPU(tc, tc->contextId()); 140 } 141 } 142} 143 144void 145BaseSimpleCPU::checkPcEventQueue() 146{ 147 Addr oldpc, pc = threadInfo[curThread]->thread->instAddr(); 148 do { 149 oldpc = pc; 150 system->pcEventQueue.service(threadContexts[curThread]); 151 pc = threadInfo[curThread]->thread->instAddr(); 152 } while (oldpc != pc); 153} 154 155void 156BaseSimpleCPU::swapActiveThread() 157{ 158 if (numThreads > 1) { 159 if ((!curStaticInst || !curStaticInst->isDelayedCommit()) && 160 !threadInfo[curThread]->stayAtPC) { 161 // Swap active threads 162 if (!activeThreads.empty()) { 163 curThread = activeThreads.front(); 164 activeThreads.pop_front(); 165 activeThreads.push_back(curThread); 166 } 167 } 168 } 169} 170 171void 172BaseSimpleCPU::countInst() 173{ 174 SimpleExecContext& t_info = *threadInfo[curThread]; 175 176 if (!curStaticInst->isMicroop() || curStaticInst->isLastMicroop()) { 177 t_info.numInst++; 178 t_info.numInsts++; 179 } 180 t_info.numOp++; 181 t_info.numOps++; 182 183 system->totalNumInsts++; 184 t_info.thread->funcExeInst++; 185} 186 187Counter 188BaseSimpleCPU::totalInsts() const 189{ 190 Counter total_inst = 0; 191 for (auto& t_info : threadInfo) { 192 total_inst += t_info->numInst; 193 } 194 195 return total_inst; 196} 197 198Counter 199BaseSimpleCPU::totalOps() const 200{ 201 Counter total_op = 0; 202 for (auto& t_info : threadInfo) { 203 total_op += t_info->numOp; 204 } 205 206 return total_op; 207} 208 209BaseSimpleCPU::~BaseSimpleCPU() 210{ 211} 212 213void 214BaseSimpleCPU::haltContext(ThreadID thread_num) 215{ 216 // for now, these are equivalent 217 suspendContext(thread_num); 218} 219 220 221void 222BaseSimpleCPU::regStats() 223{ 224 using namespace Stats; 225 226 BaseCPU::regStats(); 227 228 for (ThreadID tid = 0; tid < numThreads; tid++) { 229 SimpleExecContext& t_info = *threadInfo[tid]; 230 231 std::string thread_str = name(); 232 if (numThreads > 1) 233 thread_str += ".thread" + std::to_string(tid); 234 235 t_info.numInsts 236 .name(thread_str + ".committedInsts") 237 .desc("Number of instructions committed") 238 ; 239 240 t_info.numOps 241 .name(thread_str + ".committedOps") 242 .desc("Number of ops (including micro ops) committed") 243 ; 244 245 t_info.numIntAluAccesses 246 .name(thread_str + ".num_int_alu_accesses") 247 .desc("Number of integer alu accesses") 248 ; 249 250 t_info.numFpAluAccesses 251 .name(thread_str + ".num_fp_alu_accesses") 252 .desc("Number of float alu accesses") 253 ; 254 255 t_info.numVecAluAccesses 256 .name(thread_str + ".num_vec_alu_accesses") 257 .desc("Number of vector alu accesses") 258 ; 259 260 t_info.numCallsReturns 261 .name(thread_str + ".num_func_calls") 262 .desc("number of times a function call or return occured") 263 ; 264 265 t_info.numCondCtrlInsts 266 .name(thread_str + ".num_conditional_control_insts") 267 .desc("number of instructions that are conditional controls") 268 ; 269 270 t_info.numIntInsts 271 .name(thread_str + ".num_int_insts") 272 .desc("number of integer instructions") 273 ; 274 275 t_info.numFpInsts 276 .name(thread_str + ".num_fp_insts") 277 .desc("number of float instructions") 278 ; 279 280 t_info.numVecInsts 281 .name(thread_str + ".num_vec_insts") 282 .desc("number of vector instructions") 283 ; 284 285 t_info.numIntRegReads 286 .name(thread_str + ".num_int_register_reads") 287 .desc("number of times the integer registers were read") 288 ; 289 290 t_info.numIntRegWrites 291 .name(thread_str + ".num_int_register_writes") 292 .desc("number of times the integer registers were written") 293 ; 294 295 t_info.numFpRegReads 296 .name(thread_str + ".num_fp_register_reads") 297 .desc("number of times the floating registers were read") 298 ; 299 300 t_info.numFpRegWrites 301 .name(thread_str + ".num_fp_register_writes") 302 .desc("number of times the floating registers were written") 303 ; 304 305 t_info.numVecRegReads 306 .name(thread_str + ".num_vec_register_reads") 307 .desc("number of times the vector registers were read") 308 ; 309 310 t_info.numVecRegWrites 311 .name(thread_str + ".num_vec_register_writes") 312 .desc("number of times the vector registers were written") 313 ; 314 315 t_info.numCCRegReads 316 .name(thread_str + ".num_cc_register_reads") 317 .desc("number of times the CC registers were read") 318 .flags(nozero) 319 ; 320 321 t_info.numCCRegWrites 322 .name(thread_str + ".num_cc_register_writes") 323 .desc("number of times the CC registers were written") 324 .flags(nozero) 325 ; 326 327 t_info.numMemRefs 328 .name(thread_str + ".num_mem_refs") 329 .desc("number of memory refs") 330 ; 331 332 t_info.numStoreInsts 333 .name(thread_str + ".num_store_insts") 334 .desc("Number of store instructions") 335 ; 336 337 t_info.numLoadInsts 338 .name(thread_str + ".num_load_insts") 339 .desc("Number of load instructions") 340 ; 341 342 t_info.notIdleFraction 343 .name(thread_str + ".not_idle_fraction") 344 .desc("Percentage of non-idle cycles") 345 ; 346 347 t_info.idleFraction 348 .name(thread_str + ".idle_fraction") 349 .desc("Percentage of idle cycles") 350 ; 351 352 t_info.numBusyCycles 353 .name(thread_str + ".num_busy_cycles") 354 .desc("Number of busy cycles") 355 ; 356 357 t_info.numIdleCycles 358 .name(thread_str + ".num_idle_cycles") 359 .desc("Number of idle cycles") 360 ; 361 362 t_info.icacheStallCycles 363 .name(thread_str + ".icache_stall_cycles") 364 .desc("ICache total stall cycles") 365 .prereq(t_info.icacheStallCycles) 366 ; 367 368 t_info.dcacheStallCycles 369 .name(thread_str + ".dcache_stall_cycles") 370 .desc("DCache total stall cycles") 371 .prereq(t_info.dcacheStallCycles) 372 ; 373 374 t_info.statExecutedInstType 375 .init(Enums::Num_OpClass) 376 .name(thread_str + ".op_class") 377 .desc("Class of executed instruction") 378 .flags(total | pdf | dist) 379 ; 380 381 for (unsigned i = 0; i < Num_OpClasses; ++i) { 382 t_info.statExecutedInstType.subname(i, Enums::OpClassStrings[i]); 383 } 384 385 t_info.idleFraction = constant(1.0) - t_info.notIdleFraction; 386 t_info.numIdleCycles = t_info.idleFraction * numCycles; 387 t_info.numBusyCycles = t_info.notIdleFraction * numCycles; 388 389 t_info.numBranches 390 .name(thread_str + ".Branches") 391 .desc("Number of branches fetched") 392 .prereq(t_info.numBranches); 393 394 t_info.numPredictedBranches 395 .name(thread_str + ".predictedBranches") 396 .desc("Number of branches predicted as taken") 397 .prereq(t_info.numPredictedBranches); 398 399 t_info.numBranchMispred 400 .name(thread_str + ".BranchMispred") 401 .desc("Number of branch mispredictions") 402 .prereq(t_info.numBranchMispred); 403 } 404} 405 406void 407BaseSimpleCPU::resetStats() 408{ 409 for (auto &thread_info : threadInfo) { 410 thread_info->notIdleFraction = (_status != Idle); 411 } 412} 413 414void 415BaseSimpleCPU::serializeThread(CheckpointOut &cp, ThreadID tid) const 416{ 417 assert(_status == Idle || _status == Running); 418 419 threadInfo[tid]->thread->serialize(cp); 420} 421 422void 423BaseSimpleCPU::unserializeThread(CheckpointIn &cp, ThreadID tid) 424{ 425 threadInfo[tid]->thread->unserialize(cp); 426} 427 428void 429change_thread_state(ThreadID tid, int activate, int priority) 430{ 431} 432 433Addr 434BaseSimpleCPU::dbg_vtophys(Addr addr) 435{ 436 return vtophys(threadContexts[curThread], addr); 437} 438 439void 440BaseSimpleCPU::wakeup(ThreadID tid) 441{ 442 getCpuAddrMonitor(tid)->gotWakeup = true; 443 444 if (threadInfo[tid]->thread->status() == ThreadContext::Suspended) { 445 DPRINTF(Quiesce,"[tid:%d] Suspended Processor awoke\n", tid); 446 threadInfo[tid]->thread->activate(); 447 } 448} 449 450void 451BaseSimpleCPU::checkForInterrupts() 452{ 453 SimpleExecContext&t_info = *threadInfo[curThread]; 454 SimpleThread* thread = t_info.thread; 455 ThreadContext* tc = thread->getTC(); 456 457 if (checkInterrupts(tc)) { 458 Fault interrupt = interrupts[curThread]->getInterrupt(tc); 459 460 if (interrupt != NoFault) { 461 t_info.fetchOffset = 0; 462 interrupts[curThread]->updateIntrInfo(tc); 463 interrupt->invoke(tc); 464 thread->decoder.reset(); 465 } 466 } 467} 468 469 470void 471BaseSimpleCPU::setupFetchRequest(Request *req) 472{ 473 SimpleExecContext &t_info = *threadInfo[curThread]; 474 SimpleThread* thread = t_info.thread; 475 476 Addr instAddr = thread->instAddr(); 477 478 // set up memory request for instruction fetch 479 DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr); 480 481 Addr fetchPC = (instAddr & PCMask) + t_info.fetchOffset; 482 req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instMasterId(), 483 instAddr); 484} 485 486 487void 488BaseSimpleCPU::preExecute() 489{ 490 SimpleExecContext &t_info = *threadInfo[curThread]; 491 SimpleThread* thread = t_info.thread; 492 493 // maintain $r0 semantics 494 thread->setIntReg(ZeroReg, 0); 495#if THE_ISA == ALPHA_ISA 496 thread->setFloatReg(ZeroReg, 0.0); 497#endif // ALPHA_ISA 498 499 // check for instruction-count-based events 500 comInstEventQueue[curThread]->serviceEvents(t_info.numInst); 501 system->instEventQueue.serviceEvents(system->totalNumInsts); 502 503 // decode the instruction 504 inst = gtoh(inst); 505 506 TheISA::PCState pcState = thread->pcState(); 507 508 if (isRomMicroPC(pcState.microPC())) { 509 t_info.stayAtPC = false; 510 curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(), 511 curMacroStaticInst); 512 } else if (!curMacroStaticInst) { 513 //We're not in the middle of a macro instruction 514 StaticInstPtr instPtr = NULL; 515 516 TheISA::Decoder *decoder = &(thread->decoder); 517 518 //Predecode, ie bundle up an ExtMachInst 519 //If more fetch data is needed, pass it in. 520 Addr fetchPC = (pcState.instAddr() & PCMask) + t_info.fetchOffset; 521 //if (decoder->needMoreBytes()) 522 decoder->moreBytes(pcState, fetchPC, inst); 523 //else 524 // decoder->process(); 525 526 //Decode an instruction if one is ready. Otherwise, we'll have to 527 //fetch beyond the MachInst at the current pc. 528 instPtr = decoder->decode(pcState); 529 if (instPtr) { 530 t_info.stayAtPC = false; 531 thread->pcState(pcState); 532 } else { 533 t_info.stayAtPC = true; 534 t_info.fetchOffset += sizeof(MachInst); 535 } 536 537 //If we decoded an instruction and it's microcoded, start pulling 538 //out micro ops 539 if (instPtr && instPtr->isMacroop()) { 540 curMacroStaticInst = instPtr; 541 curStaticInst = 542 curMacroStaticInst->fetchMicroop(pcState.microPC()); 543 } else { 544 curStaticInst = instPtr; 545 } 546 } else { 547 //Read the next micro op from the macro op 548 curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 549 } 550 551 //If we decoded an instruction this "tick", record information about it. 552 if (curStaticInst) { 553#if TRACING_ON 554 traceData = tracer->getInstRecord(curTick(), thread->getTC(), 555 curStaticInst, thread->pcState(), curMacroStaticInst); 556 557 DPRINTF(Decode,"Decode: Decoded %s instruction: %#x\n", 558 curStaticInst->getName(), curStaticInst->machInst); 559#endif // TRACING_ON 560 } 561 562 if (branchPred && curStaticInst && 563 curStaticInst->isControl()) { 564 // Use a fake sequence number since we only have one 565 // instruction in flight at the same time. 566 const InstSeqNum cur_sn(0); 567 t_info.predPC = thread->pcState(); 568 const bool predict_taken( 569 branchPred->predict(curStaticInst, cur_sn, t_info.predPC, 570 curThread)); 571 572 if (predict_taken) 573 ++t_info.numPredictedBranches; 574 } 575} 576 577void 578BaseSimpleCPU::postExecute() 579{ 580 SimpleExecContext &t_info = *threadInfo[curThread]; 581 SimpleThread* thread = t_info.thread; 582 583 assert(curStaticInst); 584 585 TheISA::PCState pc = threadContexts[curThread]->pcState(); 586 Addr instAddr = pc.instAddr(); 587 if (FullSystem && thread->profile) { 588 bool usermode = TheISA::inUserMode(threadContexts[curThread]); 589 thread->profilePC = usermode ? 1 : instAddr; 590 ProfileNode *node = thread->profile->consume(threadContexts[curThread], 591 curStaticInst); 592 if (node) 593 thread->profileNode = node; 594 } 595 596 if (curStaticInst->isMemRef()) { 597 t_info.numMemRefs++; 598 } 599 600 if (curStaticInst->isLoad()) { 601 ++t_info.numLoad; 602 comLoadEventQueue[curThread]->serviceEvents(t_info.numLoad); 603 } 604 605 if (CPA::available()) { 606 CPA::cpa()->swAutoBegin(threadContexts[curThread], pc.nextInstAddr()); 607 } 608 609 if (curStaticInst->isControl()) { 610 ++t_info.numBranches; 611 } 612 613 /* Power model statistics */ 614 //integer alu accesses 615 if (curStaticInst->isInteger()){ 616 t_info.numIntAluAccesses++; 617 t_info.numIntInsts++; 618 } 619 620 //float alu accesses 621 if (curStaticInst->isFloating()){ 622 t_info.numFpAluAccesses++; 623 t_info.numFpInsts++; 624 } 625 626 //vector alu accesses 627 if (curStaticInst->isVector()){ 628 t_info.numVecAluAccesses++; 629 t_info.numVecInsts++; 630 } 631 632 //number of function calls/returns to get window accesses 633 if (curStaticInst->isCall() || curStaticInst->isReturn()){ 634 t_info.numCallsReturns++; 635 } 636 637 //the number of branch predictions that will be made 638 if (curStaticInst->isCondCtrl()){ 639 t_info.numCondCtrlInsts++; 640 } 641 642 //result bus acceses 643 if (curStaticInst->isLoad()){ 644 t_info.numLoadInsts++; 645 } 646 647 if (curStaticInst->isStore()){ 648 t_info.numStoreInsts++; 649 } 650 /* End power model statistics */ 651 652 t_info.statExecutedInstType[curStaticInst->opClass()]++; 653 654 if (FullSystem) 655 traceFunctions(instAddr); 656 657 if (traceData) { 658 traceData->dump(); 659 delete traceData; 660 traceData = NULL; 661 } 662 663 // Call CPU instruction commit probes 664 probeInstCommit(curStaticInst); 665} 666 667void 668BaseSimpleCPU::advancePC(const Fault &fault) 669{ 670 SimpleExecContext &t_info = *threadInfo[curThread]; 671 SimpleThread* thread = t_info.thread; 672 673 const bool branching(thread->pcState().branching()); 674 675 //Since we're moving to a new pc, zero out the offset 676 t_info.fetchOffset = 0; 677 if (fault != NoFault) { 678 curMacroStaticInst = StaticInst::nullStaticInstPtr; 679 fault->invoke(threadContexts[curThread], curStaticInst); 680 thread->decoder.reset(); 681 } else { 682 if (curStaticInst) { 683 if (curStaticInst->isLastMicroop()) 684 curMacroStaticInst = StaticInst::nullStaticInstPtr; 685 TheISA::PCState pcState = thread->pcState(); 686 TheISA::advancePC(pcState, curStaticInst); 687 thread->pcState(pcState); 688 } 689 } 690 691 if (branchPred && curStaticInst && curStaticInst->isControl()) { 692 // Use a fake sequence number since we only have one 693 // instruction in flight at the same time. 694 const InstSeqNum cur_sn(0); 695 696 if (t_info.predPC == thread->pcState()) { 697 // Correctly predicted branch 698 branchPred->update(cur_sn, curThread); 699 } else { 700 // Mis-predicted branch 701 branchPred->squash(cur_sn, thread->pcState(), branching, curThread); 702 ++t_info.numBranchMispred; 703 } 704 } 705} 706 707void 708BaseSimpleCPU::startup() 709{ 710 BaseCPU::startup(); 711 for (auto& t_info : threadInfo) 712 t_info->thread->startup(); 713} 714