base.cc revision 12084
1/* 2 * Copyright (c) 2010-2012,2015 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2002-2005 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 */ 43 44#include "cpu/simple/base.hh" 45 46#include "arch/kernel_stats.hh" 47#include "arch/stacktrace.hh" 48#include "arch/tlb.hh" 49#include "arch/utility.hh" 50#include "arch/vtophys.hh" 51#include "base/cp_annotate.hh" 52#include "base/cprintf.hh" 53#include "base/inifile.hh" 54#include "base/loader/symtab.hh" 55#include "base/misc.hh" 56#include "base/pollevent.hh" 57#include "base/trace.hh" 58#include "base/types.hh" 59#include "config/the_isa.hh" 60#include "cpu/base.hh" 61#include "cpu/checker/cpu.hh" 62#include "cpu/checker/thread_context.hh" 63#include "cpu/exetrace.hh" 64#include "cpu/pred/bpred_unit.hh" 65#include "cpu/profile.hh" 66#include "cpu/simple/exec_context.hh" 67#include "cpu/simple_thread.hh" 68#include "cpu/smt.hh" 69#include "cpu/static_inst.hh" 70#include "cpu/thread_context.hh" 71#include "debug/Decode.hh" 72#include "debug/Fetch.hh" 73#include "debug/Quiesce.hh" 74#include "mem/mem_object.hh" 75#include "mem/packet.hh" 76#include "mem/request.hh" 77#include "params/BaseSimpleCPU.hh" 78#include "sim/byteswap.hh" 79#include "sim/debug.hh" 80#include "sim/faults.hh" 81#include "sim/full_system.hh" 82#include "sim/sim_events.hh" 83#include "sim/sim_object.hh" 84#include "sim/stats.hh" 85#include "sim/system.hh" 86 87using namespace std; 88using namespace TheISA; 89 90BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p) 91 : BaseCPU(p), 92 curThread(0), 93 branchPred(p->branchPred), 94 traceData(NULL), 95 inst(), 96 _status(Idle) 97{ 98 SimpleThread *thread; 99 100 for (unsigned i = 0; i < numThreads; i++) { 101 if (FullSystem) { 102 thread = new SimpleThread(this, i, p->system, 103 p->itb, p->dtb, p->isa[i]); 104 } else { 105 thread = new SimpleThread(this, i, p->system, p->workload[i], 106 p->itb, p->dtb, p->isa[i]); 107 } 108 threadInfo.push_back(new SimpleExecContext(this, thread)); 109 ThreadContext *tc = thread->getTC(); 110 threadContexts.push_back(tc); 111 } 112 113 if (p->checker) { 114 if (numThreads != 1) 115 fatal("Checker currently does not support SMT"); 116 117 BaseCPU *temp_checker = p->checker; 118 checker = dynamic_cast<CheckerCPU *>(temp_checker); 119 checker->setSystem(p->system); 120 // Manipulate thread context 121 ThreadContext *cpu_tc = threadContexts[0]; 122 threadContexts[0] = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker); 123 } else { 124 checker = NULL; 125 } 126} 127 128void 129BaseSimpleCPU::init() 130{ 131 BaseCPU::init(); 132 133 for (auto tc : threadContexts) { 134 // Initialise the ThreadContext's memory proxies 135 tc->initMemProxies(tc); 136 137 if (FullSystem && !params()->switched_out) { 138 // initialize CPU, including PC 139 TheISA::initCPU(tc, tc->contextId()); 140 } 141 } 142} 143 144void 145BaseSimpleCPU::checkPcEventQueue() 146{ 147 Addr oldpc, pc = threadInfo[curThread]->thread->instAddr(); 148 do { 149 oldpc = pc; 150 system->pcEventQueue.service(threadContexts[curThread]); 151 pc = threadInfo[curThread]->thread->instAddr(); 152 } while (oldpc != pc); 153} 154 155void 156BaseSimpleCPU::swapActiveThread() 157{ 158 if (numThreads > 1) { 159 if ((!curStaticInst || !curStaticInst->isDelayedCommit()) && 160 !threadInfo[curThread]->stayAtPC) { 161 // Swap active threads 162 if (!activeThreads.empty()) { 163 curThread = activeThreads.front(); 164 activeThreads.pop_front(); 165 activeThreads.push_back(curThread); 166 } 167 } 168 } 169} 170 171void 172BaseSimpleCPU::countInst() 173{ 174 SimpleExecContext& t_info = *threadInfo[curThread]; 175 176 if (!curStaticInst->isMicroop() || curStaticInst->isLastMicroop()) { 177 t_info.numInst++; 178 t_info.numInsts++; 179 } 180 t_info.numOp++; 181 t_info.numOps++; 182 183 system->totalNumInsts++; 184 t_info.thread->funcExeInst++; 185} 186 187Counter 188BaseSimpleCPU::totalInsts() const 189{ 190 Counter total_inst = 0; 191 for (auto& t_info : threadInfo) { 192 total_inst += t_info->numInst; 193 } 194 195 return total_inst; 196} 197 198Counter 199BaseSimpleCPU::totalOps() const 200{ 201 Counter total_op = 0; 202 for (auto& t_info : threadInfo) { 203 total_op += t_info->numOp; 204 } 205 206 return total_op; 207} 208 209BaseSimpleCPU::~BaseSimpleCPU() 210{ 211} 212 213void 214BaseSimpleCPU::haltContext(ThreadID thread_num) 215{ 216 // for now, these are equivalent 217 suspendContext(thread_num); 218} 219 220 221void 222BaseSimpleCPU::regStats() 223{ 224 using namespace Stats; 225 226 BaseCPU::regStats(); 227 228 for (ThreadID tid = 0; tid < numThreads; tid++) { 229 SimpleExecContext& t_info = *threadInfo[tid]; 230 231 std::string thread_str = name(); 232 if (numThreads > 1) 233 thread_str += ".thread" + std::to_string(tid); 234 235 t_info.numInsts 236 .name(thread_str + ".committedInsts") 237 .desc("Number of instructions committed") 238 ; 239 240 t_info.numOps 241 .name(thread_str + ".committedOps") 242 .desc("Number of ops (including micro ops) committed") 243 ; 244 245 t_info.numIntAluAccesses 246 .name(thread_str + ".num_int_alu_accesses") 247 .desc("Number of integer alu accesses") 248 ; 249 250 t_info.numFpAluAccesses 251 .name(thread_str + ".num_fp_alu_accesses") 252 .desc("Number of float alu accesses") 253 ; 254 255 t_info.numCallsReturns 256 .name(thread_str + ".num_func_calls") 257 .desc("number of times a function call or return occured") 258 ; 259 260 t_info.numCondCtrlInsts 261 .name(thread_str + ".num_conditional_control_insts") 262 .desc("number of instructions that are conditional controls") 263 ; 264 265 t_info.numIntInsts 266 .name(thread_str + ".num_int_insts") 267 .desc("number of integer instructions") 268 ; 269 270 t_info.numFpInsts 271 .name(thread_str + ".num_fp_insts") 272 .desc("number of float instructions") 273 ; 274 275 t_info.numIntRegReads 276 .name(thread_str + ".num_int_register_reads") 277 .desc("number of times the integer registers were read") 278 ; 279 280 t_info.numIntRegWrites 281 .name(thread_str + ".num_int_register_writes") 282 .desc("number of times the integer registers were written") 283 ; 284 285 t_info.numFpRegReads 286 .name(thread_str + ".num_fp_register_reads") 287 .desc("number of times the floating registers were read") 288 ; 289 290 t_info.numFpRegWrites 291 .name(thread_str + ".num_fp_register_writes") 292 .desc("number of times the floating registers were written") 293 ; 294 295 t_info.numCCRegReads 296 .name(thread_str + ".num_cc_register_reads") 297 .desc("number of times the CC registers were read") 298 .flags(nozero) 299 ; 300 301 t_info.numCCRegWrites 302 .name(thread_str + ".num_cc_register_writes") 303 .desc("number of times the CC registers were written") 304 .flags(nozero) 305 ; 306 307 t_info.numMemRefs 308 .name(thread_str + ".num_mem_refs") 309 .desc("number of memory refs") 310 ; 311 312 t_info.numStoreInsts 313 .name(thread_str + ".num_store_insts") 314 .desc("Number of store instructions") 315 ; 316 317 t_info.numLoadInsts 318 .name(thread_str + ".num_load_insts") 319 .desc("Number of load instructions") 320 ; 321 322 t_info.notIdleFraction 323 .name(thread_str + ".not_idle_fraction") 324 .desc("Percentage of non-idle cycles") 325 ; 326 327 t_info.idleFraction 328 .name(thread_str + ".idle_fraction") 329 .desc("Percentage of idle cycles") 330 ; 331 332 t_info.numBusyCycles 333 .name(thread_str + ".num_busy_cycles") 334 .desc("Number of busy cycles") 335 ; 336 337 t_info.numIdleCycles 338 .name(thread_str + ".num_idle_cycles") 339 .desc("Number of idle cycles") 340 ; 341 342 t_info.icacheStallCycles 343 .name(thread_str + ".icache_stall_cycles") 344 .desc("ICache total stall cycles") 345 .prereq(t_info.icacheStallCycles) 346 ; 347 348 t_info.dcacheStallCycles 349 .name(thread_str + ".dcache_stall_cycles") 350 .desc("DCache total stall cycles") 351 .prereq(t_info.dcacheStallCycles) 352 ; 353 354 t_info.statExecutedInstType 355 .init(Enums::Num_OpClass) 356 .name(thread_str + ".op_class") 357 .desc("Class of executed instruction") 358 .flags(total | pdf | dist) 359 ; 360 361 for (unsigned i = 0; i < Num_OpClasses; ++i) { 362 t_info.statExecutedInstType.subname(i, Enums::OpClassStrings[i]); 363 } 364 365 t_info.idleFraction = constant(1.0) - t_info.notIdleFraction; 366 t_info.numIdleCycles = t_info.idleFraction * numCycles; 367 t_info.numBusyCycles = t_info.notIdleFraction * numCycles; 368 369 t_info.numBranches 370 .name(thread_str + ".Branches") 371 .desc("Number of branches fetched") 372 .prereq(t_info.numBranches); 373 374 t_info.numPredictedBranches 375 .name(thread_str + ".predictedBranches") 376 .desc("Number of branches predicted as taken") 377 .prereq(t_info.numPredictedBranches); 378 379 t_info.numBranchMispred 380 .name(thread_str + ".BranchMispred") 381 .desc("Number of branch mispredictions") 382 .prereq(t_info.numBranchMispred); 383 } 384} 385 386void 387BaseSimpleCPU::resetStats() 388{ 389 for (auto &thread_info : threadInfo) { 390 thread_info->notIdleFraction = (_status != Idle); 391 } 392} 393 394void 395BaseSimpleCPU::serializeThread(CheckpointOut &cp, ThreadID tid) const 396{ 397 assert(_status == Idle || _status == Running); 398 399 threadInfo[tid]->thread->serialize(cp); 400} 401 402void 403BaseSimpleCPU::unserializeThread(CheckpointIn &cp, ThreadID tid) 404{ 405 threadInfo[tid]->thread->unserialize(cp); 406} 407 408void 409change_thread_state(ThreadID tid, int activate, int priority) 410{ 411} 412 413Addr 414BaseSimpleCPU::dbg_vtophys(Addr addr) 415{ 416 return vtophys(threadContexts[curThread], addr); 417} 418 419void 420BaseSimpleCPU::wakeup(ThreadID tid) 421{ 422 getCpuAddrMonitor(tid)->gotWakeup = true; 423 424 if (threadInfo[tid]->thread->status() == ThreadContext::Suspended) { 425 DPRINTF(Quiesce,"[tid:%d] Suspended Processor awoke\n", tid); 426 threadInfo[tid]->thread->activate(); 427 } 428} 429 430void 431BaseSimpleCPU::checkForInterrupts() 432{ 433 SimpleExecContext&t_info = *threadInfo[curThread]; 434 SimpleThread* thread = t_info.thread; 435 ThreadContext* tc = thread->getTC(); 436 437 if (checkInterrupts(tc)) { 438 Fault interrupt = interrupts[curThread]->getInterrupt(tc); 439 440 if (interrupt != NoFault) { 441 t_info.fetchOffset = 0; 442 interrupts[curThread]->updateIntrInfo(tc); 443 interrupt->invoke(tc); 444 thread->decoder.reset(); 445 } 446 } 447} 448 449 450void 451BaseSimpleCPU::setupFetchRequest(Request *req) 452{ 453 SimpleExecContext &t_info = *threadInfo[curThread]; 454 SimpleThread* thread = t_info.thread; 455 456 Addr instAddr = thread->instAddr(); 457 458 // set up memory request for instruction fetch 459 DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr); 460 461 Addr fetchPC = (instAddr & PCMask) + t_info.fetchOffset; 462 req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instMasterId(), 463 instAddr); 464} 465 466 467void 468BaseSimpleCPU::preExecute() 469{ 470 SimpleExecContext &t_info = *threadInfo[curThread]; 471 SimpleThread* thread = t_info.thread; 472 473 // maintain $r0 semantics 474 thread->setIntReg(ZeroReg, 0); 475#if THE_ISA == ALPHA_ISA 476 thread->setFloatReg(ZeroReg, 0.0); 477#endif // ALPHA_ISA 478 479 // check for instruction-count-based events 480 comInstEventQueue[curThread]->serviceEvents(t_info.numInst); 481 system->instEventQueue.serviceEvents(system->totalNumInsts); 482 483 // decode the instruction 484 inst = gtoh(inst); 485 486 TheISA::PCState pcState = thread->pcState(); 487 488 if (isRomMicroPC(pcState.microPC())) { 489 t_info.stayAtPC = false; 490 curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(), 491 curMacroStaticInst); 492 } else if (!curMacroStaticInst) { 493 //We're not in the middle of a macro instruction 494 StaticInstPtr instPtr = NULL; 495 496 TheISA::Decoder *decoder = &(thread->decoder); 497 498 //Predecode, ie bundle up an ExtMachInst 499 //If more fetch data is needed, pass it in. 500 Addr fetchPC = (pcState.instAddr() & PCMask) + t_info.fetchOffset; 501 //if (decoder->needMoreBytes()) 502 decoder->moreBytes(pcState, fetchPC, inst); 503 //else 504 // decoder->process(); 505 506 //Decode an instruction if one is ready. Otherwise, we'll have to 507 //fetch beyond the MachInst at the current pc. 508 instPtr = decoder->decode(pcState); 509 if (instPtr) { 510 t_info.stayAtPC = false; 511 thread->pcState(pcState); 512 } else { 513 t_info.stayAtPC = true; 514 t_info.fetchOffset += sizeof(MachInst); 515 } 516 517 //If we decoded an instruction and it's microcoded, start pulling 518 //out micro ops 519 if (instPtr && instPtr->isMacroop()) { 520 curMacroStaticInst = instPtr; 521 curStaticInst = 522 curMacroStaticInst->fetchMicroop(pcState.microPC()); 523 } else { 524 curStaticInst = instPtr; 525 } 526 } else { 527 //Read the next micro op from the macro op 528 curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 529 } 530 531 //If we decoded an instruction this "tick", record information about it. 532 if (curStaticInst) { 533#if TRACING_ON 534 traceData = tracer->getInstRecord(curTick(), thread->getTC(), 535 curStaticInst, thread->pcState(), curMacroStaticInst); 536 537 DPRINTF(Decode,"Decode: Decoded %s instruction: %#x\n", 538 curStaticInst->getName(), curStaticInst->machInst); 539#endif // TRACING_ON 540 } 541 542 if (branchPred && curStaticInst && 543 curStaticInst->isControl()) { 544 // Use a fake sequence number since we only have one 545 // instruction in flight at the same time. 546 const InstSeqNum cur_sn(0); 547 t_info.predPC = thread->pcState(); 548 const bool predict_taken( 549 branchPred->predict(curStaticInst, cur_sn, t_info.predPC, 550 curThread)); 551 552 if (predict_taken) 553 ++t_info.numPredictedBranches; 554 } 555} 556 557void 558BaseSimpleCPU::postExecute() 559{ 560 SimpleExecContext &t_info = *threadInfo[curThread]; 561 SimpleThread* thread = t_info.thread; 562 563 assert(curStaticInst); 564 565 TheISA::PCState pc = threadContexts[curThread]->pcState(); 566 Addr instAddr = pc.instAddr(); 567 if (FullSystem && thread->profile) { 568 bool usermode = TheISA::inUserMode(threadContexts[curThread]); 569 thread->profilePC = usermode ? 1 : instAddr; 570 ProfileNode *node = thread->profile->consume(threadContexts[curThread], 571 curStaticInst); 572 if (node) 573 thread->profileNode = node; 574 } 575 576 if (curStaticInst->isMemRef()) { 577 t_info.numMemRefs++; 578 } 579 580 if (curStaticInst->isLoad()) { 581 ++t_info.numLoad; 582 comLoadEventQueue[curThread]->serviceEvents(t_info.numLoad); 583 } 584 585 if (CPA::available()) { 586 CPA::cpa()->swAutoBegin(threadContexts[curThread], pc.nextInstAddr()); 587 } 588 589 if (curStaticInst->isControl()) { 590 ++t_info.numBranches; 591 } 592 593 /* Power model statistics */ 594 //integer alu accesses 595 if (curStaticInst->isInteger()){ 596 t_info.numIntAluAccesses++; 597 t_info.numIntInsts++; 598 } 599 600 //float alu accesses 601 if (curStaticInst->isFloating()){ 602 t_info.numFpAluAccesses++; 603 t_info.numFpInsts++; 604 } 605 606 //number of function calls/returns to get window accesses 607 if (curStaticInst->isCall() || curStaticInst->isReturn()){ 608 t_info.numCallsReturns++; 609 } 610 611 //the number of branch predictions that will be made 612 if (curStaticInst->isCondCtrl()){ 613 t_info.numCondCtrlInsts++; 614 } 615 616 //result bus acceses 617 if (curStaticInst->isLoad()){ 618 t_info.numLoadInsts++; 619 } 620 621 if (curStaticInst->isStore()){ 622 t_info.numStoreInsts++; 623 } 624 /* End power model statistics */ 625 626 t_info.statExecutedInstType[curStaticInst->opClass()]++; 627 628 if (FullSystem) 629 traceFunctions(instAddr); 630 631 if (traceData) { 632 traceData->dump(); 633 delete traceData; 634 traceData = NULL; 635 } 636 637 // Call CPU instruction commit probes 638 probeInstCommit(curStaticInst); 639} 640 641void 642BaseSimpleCPU::advancePC(const Fault &fault) 643{ 644 SimpleExecContext &t_info = *threadInfo[curThread]; 645 SimpleThread* thread = t_info.thread; 646 647 const bool branching(thread->pcState().branching()); 648 649 //Since we're moving to a new pc, zero out the offset 650 t_info.fetchOffset = 0; 651 if (fault != NoFault) { 652 curMacroStaticInst = StaticInst::nullStaticInstPtr; 653 fault->invoke(threadContexts[curThread], curStaticInst); 654 thread->decoder.reset(); 655 } else { 656 if (curStaticInst) { 657 if (curStaticInst->isLastMicroop()) 658 curMacroStaticInst = StaticInst::nullStaticInstPtr; 659 TheISA::PCState pcState = thread->pcState(); 660 TheISA::advancePC(pcState, curStaticInst); 661 thread->pcState(pcState); 662 } 663 } 664 665 if (branchPred && curStaticInst && curStaticInst->isControl()) { 666 // Use a fake sequence number since we only have one 667 // instruction in flight at the same time. 668 const InstSeqNum cur_sn(0); 669 670 if (t_info.predPC == thread->pcState()) { 671 // Correctly predicted branch 672 branchPred->update(cur_sn, curThread); 673 } else { 674 // Mis-predicted branch 675 branchPred->squash(cur_sn, thread->pcState(), branching, curThread); 676 ++t_info.numBranchMispred; 677 } 678 } 679} 680 681void 682BaseSimpleCPU::startup() 683{ 684 BaseCPU::startup(); 685 for (auto& t_info : threadInfo) 686 t_info->thread->startup(); 687} 688