base.cc revision 11150
1/* 2 * Copyright (c) 2010-2012,2015 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2002-2005 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 */ 43 44#include "arch/kernel_stats.hh" 45#include "arch/stacktrace.hh" 46#include "arch/tlb.hh" 47#include "arch/utility.hh" 48#include "arch/vtophys.hh" 49#include "base/loader/symtab.hh" 50#include "base/cp_annotate.hh" 51#include "base/cprintf.hh" 52#include "base/inifile.hh" 53#include "base/misc.hh" 54#include "base/pollevent.hh" 55#include "base/trace.hh" 56#include "base/types.hh" 57#include "config/the_isa.hh" 58#include "cpu/simple/base.hh" 59#include "cpu/base.hh" 60#include "cpu/checker/cpu.hh" 61#include "cpu/checker/thread_context.hh" 62#include "cpu/exetrace.hh" 63#include "cpu/pred/bpred_unit.hh" 64#include "cpu/profile.hh" 65#include "cpu/simple/exec_context.hh" 66#include "cpu/simple_thread.hh" 67#include "cpu/smt.hh" 68#include "cpu/static_inst.hh" 69#include "cpu/thread_context.hh" 70#include "debug/Decode.hh" 71#include "debug/Fetch.hh" 72#include "debug/Quiesce.hh" 73#include "mem/mem_object.hh" 74#include "mem/packet.hh" 75#include "mem/request.hh" 76#include "params/BaseSimpleCPU.hh" 77#include "sim/byteswap.hh" 78#include "sim/debug.hh" 79#include "sim/faults.hh" 80#include "sim/full_system.hh" 81#include "sim/sim_events.hh" 82#include "sim/sim_object.hh" 83#include "sim/stats.hh" 84#include "sim/system.hh" 85 86using namespace std; 87using namespace TheISA; 88 89BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p) 90 : BaseCPU(p), 91 curThread(0), 92 branchPred(p->branchPred), 93 traceData(NULL), 94 inst(), 95 _status(Idle) 96{ 97 SimpleThread *thread; 98 99 for (unsigned i = 0; i < numThreads; i++) { 100 if (FullSystem) { 101 thread = new SimpleThread(this, i, p->system, 102 p->itb, p->dtb, p->isa[i]); 103 } else { 104 thread = new SimpleThread(this, i, p->system, p->workload[i], 105 p->itb, p->dtb, p->isa[i]); 106 } 107 threadInfo.push_back(new SimpleExecContext(this, thread)); 108 ThreadContext *tc = thread->getTC(); 109 threadContexts.push_back(tc); 110 } 111 112 if (p->checker) { 113 if (numThreads != 1) 114 fatal("Checker currently does not support SMT"); 115 116 BaseCPU *temp_checker = p->checker; 117 checker = dynamic_cast<CheckerCPU *>(temp_checker); 118 checker->setSystem(p->system); 119 // Manipulate thread context 120 ThreadContext *cpu_tc = threadContexts[0]; 121 threadContexts[0] = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker); 122 } else { 123 checker = NULL; 124 } 125} 126 127void 128BaseSimpleCPU::init() 129{ 130 BaseCPU::init(); 131 132 for (auto tc : threadContexts) { 133 // Initialise the ThreadContext's memory proxies 134 tc->initMemProxies(tc); 135 136 if (FullSystem && !params()->switched_out) { 137 // initialize CPU, including PC 138 TheISA::initCPU(tc, tc->contextId()); 139 } 140 } 141} 142 143void 144BaseSimpleCPU::checkPcEventQueue() 145{ 146 Addr oldpc, pc = threadInfo[curThread]->thread->instAddr(); 147 do { 148 oldpc = pc; 149 system->pcEventQueue.service(threadContexts[curThread]); 150 pc = threadInfo[curThread]->thread->instAddr(); 151 } while (oldpc != pc); 152} 153 154void 155BaseSimpleCPU::swapActiveThread() 156{ 157 if (numThreads > 1) { 158 if ((!curStaticInst || !curStaticInst->isDelayedCommit()) && 159 !threadInfo[curThread]->stayAtPC) { 160 // Swap active threads 161 if (!activeThreads.empty()) { 162 curThread = activeThreads.front(); 163 activeThreads.pop_front(); 164 activeThreads.push_back(curThread); 165 } 166 } 167 } 168} 169 170void 171BaseSimpleCPU::countInst() 172{ 173 SimpleExecContext& t_info = *threadInfo[curThread]; 174 175 if (!curStaticInst->isMicroop() || curStaticInst->isLastMicroop()) { 176 t_info.numInst++; 177 t_info.numInsts++; 178 } 179 t_info.numOp++; 180 t_info.numOps++; 181 182 system->totalNumInsts++; 183 t_info.thread->funcExeInst++; 184} 185 186Counter 187BaseSimpleCPU::totalInsts() const 188{ 189 Counter total_inst = 0; 190 for (auto& t_info : threadInfo) { 191 total_inst += t_info->numInst; 192 } 193 194 return total_inst; 195} 196 197Counter 198BaseSimpleCPU::totalOps() const 199{ 200 Counter total_op = 0; 201 for (auto& t_info : threadInfo) { 202 total_op += t_info->numOp; 203 } 204 205 return total_op; 206} 207 208BaseSimpleCPU::~BaseSimpleCPU() 209{ 210} 211 212void 213BaseSimpleCPU::haltContext(ThreadID thread_num) 214{ 215 // for now, these are equivalent 216 suspendContext(thread_num); 217} 218 219 220void 221BaseSimpleCPU::regStats() 222{ 223 using namespace Stats; 224 225 BaseCPU::regStats(); 226 227 for (ThreadID tid = 0; tid < numThreads; tid++) { 228 SimpleExecContext& t_info = *threadInfo[tid]; 229 230 std::string thread_str = name(); 231 if (numThreads > 1) 232 thread_str += ".thread" + std::to_string(tid); 233 234 t_info.numInsts 235 .name(thread_str + ".committedInsts") 236 .desc("Number of instructions committed") 237 ; 238 239 t_info.numOps 240 .name(thread_str + ".committedOps") 241 .desc("Number of ops (including micro ops) committed") 242 ; 243 244 t_info.numIntAluAccesses 245 .name(thread_str + ".num_int_alu_accesses") 246 .desc("Number of integer alu accesses") 247 ; 248 249 t_info.numFpAluAccesses 250 .name(thread_str + ".num_fp_alu_accesses") 251 .desc("Number of float alu accesses") 252 ; 253 254 t_info.numCallsReturns 255 .name(thread_str + ".num_func_calls") 256 .desc("number of times a function call or return occured") 257 ; 258 259 t_info.numCondCtrlInsts 260 .name(thread_str + ".num_conditional_control_insts") 261 .desc("number of instructions that are conditional controls") 262 ; 263 264 t_info.numIntInsts 265 .name(thread_str + ".num_int_insts") 266 .desc("number of integer instructions") 267 ; 268 269 t_info.numFpInsts 270 .name(thread_str + ".num_fp_insts") 271 .desc("number of float instructions") 272 ; 273 274 t_info.numIntRegReads 275 .name(thread_str + ".num_int_register_reads") 276 .desc("number of times the integer registers were read") 277 ; 278 279 t_info.numIntRegWrites 280 .name(thread_str + ".num_int_register_writes") 281 .desc("number of times the integer registers were written") 282 ; 283 284 t_info.numFpRegReads 285 .name(thread_str + ".num_fp_register_reads") 286 .desc("number of times the floating registers were read") 287 ; 288 289 t_info.numFpRegWrites 290 .name(thread_str + ".num_fp_register_writes") 291 .desc("number of times the floating registers were written") 292 ; 293 294 t_info.numCCRegReads 295 .name(thread_str + ".num_cc_register_reads") 296 .desc("number of times the CC registers were read") 297 .flags(nozero) 298 ; 299 300 t_info.numCCRegWrites 301 .name(thread_str + ".num_cc_register_writes") 302 .desc("number of times the CC registers were written") 303 .flags(nozero) 304 ; 305 306 t_info.numMemRefs 307 .name(thread_str + ".num_mem_refs") 308 .desc("number of memory refs") 309 ; 310 311 t_info.numStoreInsts 312 .name(thread_str + ".num_store_insts") 313 .desc("Number of store instructions") 314 ; 315 316 t_info.numLoadInsts 317 .name(thread_str + ".num_load_insts") 318 .desc("Number of load instructions") 319 ; 320 321 t_info.notIdleFraction 322 .name(thread_str + ".not_idle_fraction") 323 .desc("Percentage of non-idle cycles") 324 ; 325 326 t_info.idleFraction 327 .name(thread_str + ".idle_fraction") 328 .desc("Percentage of idle cycles") 329 ; 330 331 t_info.numBusyCycles 332 .name(thread_str + ".num_busy_cycles") 333 .desc("Number of busy cycles") 334 ; 335 336 t_info.numIdleCycles 337 .name(thread_str + ".num_idle_cycles") 338 .desc("Number of idle cycles") 339 ; 340 341 t_info.icacheStallCycles 342 .name(thread_str + ".icache_stall_cycles") 343 .desc("ICache total stall cycles") 344 .prereq(t_info.icacheStallCycles) 345 ; 346 347 t_info.dcacheStallCycles 348 .name(thread_str + ".dcache_stall_cycles") 349 .desc("DCache total stall cycles") 350 .prereq(t_info.dcacheStallCycles) 351 ; 352 353 t_info.statExecutedInstType 354 .init(Enums::Num_OpClass) 355 .name(thread_str + ".op_class") 356 .desc("Class of executed instruction") 357 .flags(total | pdf | dist) 358 ; 359 360 for (unsigned i = 0; i < Num_OpClasses; ++i) { 361 t_info.statExecutedInstType.subname(i, Enums::OpClassStrings[i]); 362 } 363 364 t_info.idleFraction = constant(1.0) - t_info.notIdleFraction; 365 t_info.numIdleCycles = t_info.idleFraction * numCycles; 366 t_info.numBusyCycles = t_info.notIdleFraction * numCycles; 367 368 t_info.numBranches 369 .name(thread_str + ".Branches") 370 .desc("Number of branches fetched") 371 .prereq(t_info.numBranches); 372 373 t_info.numPredictedBranches 374 .name(thread_str + ".predictedBranches") 375 .desc("Number of branches predicted as taken") 376 .prereq(t_info.numPredictedBranches); 377 378 t_info.numBranchMispred 379 .name(thread_str + ".BranchMispred") 380 .desc("Number of branch mispredictions") 381 .prereq(t_info.numBranchMispred); 382 } 383} 384 385void 386BaseSimpleCPU::resetStats() 387{ 388 for (auto &thread_info : threadInfo) { 389 thread_info->notIdleFraction = (_status != Idle); 390 } 391} 392 393void 394BaseSimpleCPU::serializeThread(CheckpointOut &cp, ThreadID tid) const 395{ 396 assert(_status == Idle || _status == Running); 397 398 threadInfo[tid]->thread->serialize(cp); 399} 400 401void 402BaseSimpleCPU::unserializeThread(CheckpointIn &cp, ThreadID tid) 403{ 404 threadInfo[tid]->thread->unserialize(cp); 405} 406 407void 408change_thread_state(ThreadID tid, int activate, int priority) 409{ 410} 411 412Addr 413BaseSimpleCPU::dbg_vtophys(Addr addr) 414{ 415 return vtophys(threadContexts[curThread], addr); 416} 417 418void 419BaseSimpleCPU::wakeup() 420{ 421 for (ThreadID tid = 0; tid < numThreads; tid++) { 422 getCpuAddrMonitor(tid)->gotWakeup = true; 423 if (threadInfo[tid]->thread->status() == ThreadContext::Suspended) { 424 DPRINTF(Quiesce,"Suspended Processor awoke\n"); 425 threadInfo[tid]->thread->activate(); 426 } 427 } 428} 429 430void 431BaseSimpleCPU::checkForInterrupts() 432{ 433 SimpleExecContext&t_info = *threadInfo[curThread]; 434 SimpleThread* thread = t_info.thread; 435 ThreadContext* tc = thread->getTC(); 436 437 if (checkInterrupts(tc)) { 438 Fault interrupt = interrupts[curThread]->getInterrupt(tc); 439 440 if (interrupt != NoFault) { 441 t_info.fetchOffset = 0; 442 interrupts[curThread]->updateIntrInfo(tc); 443 interrupt->invoke(tc); 444 thread->decoder.reset(); 445 } 446 } 447} 448 449 450void 451BaseSimpleCPU::setupFetchRequest(Request *req) 452{ 453 SimpleExecContext &t_info = *threadInfo[curThread]; 454 SimpleThread* thread = t_info.thread; 455 456 Addr instAddr = thread->instAddr(); 457 458 // set up memory request for instruction fetch 459 DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr); 460 461 Addr fetchPC = (instAddr & PCMask) + t_info.fetchOffset; 462 req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instMasterId(), 463 instAddr); 464} 465 466 467void 468BaseSimpleCPU::preExecute() 469{ 470 SimpleExecContext &t_info = *threadInfo[curThread]; 471 SimpleThread* thread = t_info.thread; 472 473 // maintain $r0 semantics 474 thread->setIntReg(ZeroReg, 0); 475#if THE_ISA == ALPHA_ISA 476 thread->setFloatReg(ZeroReg, 0.0); 477#endif // ALPHA_ISA 478 479 // check for instruction-count-based events 480 comInstEventQueue[curThread]->serviceEvents(t_info.numInst); 481 system->instEventQueue.serviceEvents(system->totalNumInsts); 482 483 // decode the instruction 484 inst = gtoh(inst); 485 486 TheISA::PCState pcState = thread->pcState(); 487 488 if (isRomMicroPC(pcState.microPC())) { 489 t_info.stayAtPC = false; 490 curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(), 491 curMacroStaticInst); 492 } else if (!curMacroStaticInst) { 493 //We're not in the middle of a macro instruction 494 StaticInstPtr instPtr = NULL; 495 496 TheISA::Decoder *decoder = &(thread->decoder); 497 498 //Predecode, ie bundle up an ExtMachInst 499 //If more fetch data is needed, pass it in. 500 Addr fetchPC = (pcState.instAddr() & PCMask) + t_info.fetchOffset; 501 //if(decoder->needMoreBytes()) 502 decoder->moreBytes(pcState, fetchPC, inst); 503 //else 504 // decoder->process(); 505 506 //Decode an instruction if one is ready. Otherwise, we'll have to 507 //fetch beyond the MachInst at the current pc. 508 instPtr = decoder->decode(pcState); 509 if (instPtr) { 510 t_info.stayAtPC = false; 511 thread->pcState(pcState); 512 } else { 513 t_info.stayAtPC = true; 514 t_info.fetchOffset += sizeof(MachInst); 515 } 516 517 //If we decoded an instruction and it's microcoded, start pulling 518 //out micro ops 519 if (instPtr && instPtr->isMacroop()) { 520 curMacroStaticInst = instPtr; 521 curStaticInst = 522 curMacroStaticInst->fetchMicroop(pcState.microPC()); 523 } else { 524 curStaticInst = instPtr; 525 } 526 } else { 527 //Read the next micro op from the macro op 528 curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 529 } 530 531 //If we decoded an instruction this "tick", record information about it. 532 if (curStaticInst) { 533#if TRACING_ON 534 traceData = tracer->getInstRecord(curTick(), thread->getTC(), 535 curStaticInst, thread->pcState(), curMacroStaticInst); 536 537 DPRINTF(Decode,"Decode: Decoded %s instruction: %#x\n", 538 curStaticInst->getName(), curStaticInst->machInst); 539#endif // TRACING_ON 540 } 541 542 if (branchPred && curStaticInst && 543 curStaticInst->isControl()) { 544 // Use a fake sequence number since we only have one 545 // instruction in flight at the same time. 546 const InstSeqNum cur_sn(0); 547 t_info.predPC = thread->pcState(); 548 const bool predict_taken( 549 branchPred->predict(curStaticInst, cur_sn, t_info.predPC, 550 curThread)); 551 552 if (predict_taken) 553 ++t_info.numPredictedBranches; 554 } 555} 556 557void 558BaseSimpleCPU::postExecute() 559{ 560 SimpleExecContext &t_info = *threadInfo[curThread]; 561 SimpleThread* thread = t_info.thread; 562 563 assert(curStaticInst); 564 565 TheISA::PCState pc = threadContexts[curThread]->pcState(); 566 Addr instAddr = pc.instAddr(); 567 if (FullSystem && thread->profile) { 568 bool usermode = TheISA::inUserMode(threadContexts[curThread]); 569 thread->profilePC = usermode ? 1 : instAddr; 570 ProfileNode *node = thread->profile->consume(threadContexts[curThread], 571 curStaticInst); 572 if (node) 573 thread->profileNode = node; 574 } 575 576 if (curStaticInst->isMemRef()) { 577 t_info.numMemRefs++; 578 } 579 580 if (curStaticInst->isLoad()) { 581 ++t_info.numLoad; 582 comLoadEventQueue[curThread]->serviceEvents(t_info.numLoad); 583 } 584 585 if (CPA::available()) { 586 CPA::cpa()->swAutoBegin(threadContexts[curThread], pc.nextInstAddr()); 587 } 588 589 if (curStaticInst->isControl()) { 590 ++t_info.numBranches; 591 } 592 593 /* Power model statistics */ 594 //integer alu accesses 595 if (curStaticInst->isInteger()){ 596 t_info.numIntAluAccesses++; 597 t_info.numIntInsts++; 598 } 599 600 //float alu accesses 601 if (curStaticInst->isFloating()){ 602 t_info.numFpAluAccesses++; 603 t_info.numFpInsts++; 604 } 605 606 //number of function calls/returns to get window accesses 607 if (curStaticInst->isCall() || curStaticInst->isReturn()){ 608 t_info.numCallsReturns++; 609 } 610 611 //the number of branch predictions that will be made 612 if (curStaticInst->isCondCtrl()){ 613 t_info.numCondCtrlInsts++; 614 } 615 616 //result bus acceses 617 if (curStaticInst->isLoad()){ 618 t_info.numLoadInsts++; 619 } 620 621 if (curStaticInst->isStore()){ 622 t_info.numStoreInsts++; 623 } 624 /* End power model statistics */ 625 626 t_info.statExecutedInstType[curStaticInst->opClass()]++; 627 628 if (FullSystem) 629 traceFunctions(instAddr); 630 631 if (traceData) { 632 traceData->dump(); 633 delete traceData; 634 traceData = NULL; 635 } 636 637 // Call CPU instruction commit probes 638 probeInstCommit(curStaticInst); 639} 640 641void 642BaseSimpleCPU::advancePC(const Fault &fault) 643{ 644 SimpleExecContext &t_info = *threadInfo[curThread]; 645 SimpleThread* thread = t_info.thread; 646 647 const bool branching(thread->pcState().branching()); 648 649 //Since we're moving to a new pc, zero out the offset 650 t_info.fetchOffset = 0; 651 if (fault != NoFault) { 652 curMacroStaticInst = StaticInst::nullStaticInstPtr; 653 fault->invoke(threadContexts[curThread], curStaticInst); 654 thread->decoder.reset(); 655 } else { 656 if (curStaticInst) { 657 if (curStaticInst->isLastMicroop()) 658 curMacroStaticInst = StaticInst::nullStaticInstPtr; 659 TheISA::PCState pcState = thread->pcState(); 660 TheISA::advancePC(pcState, curStaticInst); 661 thread->pcState(pcState); 662 } 663 } 664 665 if (branchPred && curStaticInst && curStaticInst->isControl()) { 666 // Use a fake sequence number since we only have one 667 // instruction in flight at the same time. 668 const InstSeqNum cur_sn(0); 669 670 if (t_info.predPC == thread->pcState()) { 671 // Correctly predicted branch 672 branchPred->update(cur_sn, curThread); 673 } else { 674 // Mis-predicted branch 675 branchPred->squash(cur_sn, thread->pcState(), branching, curThread); 676 ++t_info.numBranchMispred; 677 } 678 } 679} 680 681void 682BaseSimpleCPU::startup() 683{ 684 BaseCPU::startup(); 685 for (auto& t_info : threadInfo) 686 t_info->thread->startup(); 687} 688