base.cc revision 1080 
1/*
2 * Copyright (c) 2002-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <cmath>
30#include <cstdio>
31#include <cstdlib>
32#include <iostream>
33#include <iomanip>
34#include <list>
35#include <sstream>
36#include <string>
37
38#include "base/cprintf.hh"
39#include "base/inifile.hh"
40#include "base/loader/symtab.hh"
41#include "base/misc.hh"
42#include "base/pollevent.hh"
43#include "base/range.hh"
44#include "base/trace.hh"
45#include "base/stats/events.hh"
46#include "cpu/base_cpu.hh"
47#include "cpu/exec_context.hh"
48#include "cpu/exetrace.hh"
49#include "cpu/full_cpu/smt.hh"
50#include "cpu/simple_cpu/simple_cpu.hh"
51#include "cpu/static_inst.hh"
52#include "mem/base_mem.hh"
53#include "mem/mem_interface.hh"
54#include "sim/builder.hh"
55#include "sim/debug.hh"
56#include "sim/host.hh"
57#include "sim/sim_events.hh"
58#include "sim/sim_object.hh"
59#include "sim/stats.hh"
60
61#ifdef FULL_SYSTEM
62#include "base/remote_gdb.hh"
63#include "dev/alpha_access.h"
64#include "dev/pciareg.h"
65#include "mem/functional_mem/memory_control.hh"
66#include "mem/functional_mem/physical_memory.hh"
67#include "sim/system.hh"
68#include "targetarch/alpha_memory.hh"
69#include "targetarch/vtophys.hh"
70#else // !FULL_SYSTEM
71#include "eio/eio.hh"
72#include "mem/functional_mem/functional_memory.hh"
73#endif // FULL_SYSTEM
74
75using namespace std;
76
77SimpleCPU::TickEvent::TickEvent(SimpleCPU *c)
78    : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), multiplier(1)
79{
80}
81
82void
83SimpleCPU::TickEvent::process()
84{
85    int count = multiplier;
86    do {
87        cpu->tick();
88    } while (--count > 0 && cpu->status() == Running);
89}
90
91const char *
92SimpleCPU::TickEvent::description()
93{
94    return "SimpleCPU tick event";
95}
96
97
98SimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu)
99    : Event(&mainEventQueue),
100      cpu(_cpu)
101{
102}
103
104void SimpleCPU::CacheCompletionEvent::process()
105{
106    cpu->processCacheCompletion();
107}
108
109const char *
110SimpleCPU::CacheCompletionEvent::description()
111{
112    return "SimpleCPU cache completion event";
113}
114
115#ifdef FULL_SYSTEM
116SimpleCPU::SimpleCPU(const string &_name,
117                     System *_system,
118                     Counter max_insts_any_thread,
119                     Counter max_insts_all_threads,
120                     Counter max_loads_any_thread,
121                     Counter max_loads_all_threads,
122                     AlphaITB *itb, AlphaDTB *dtb,
123                     FunctionalMemory *mem,
124                     MemInterface *icache_interface,
125                     MemInterface *dcache_interface,
126                     bool _def_reg, Tick freq)
127    : BaseCPU(_name, /* number_of_threads */ 1,
128              max_insts_any_thread, max_insts_all_threads,
129              max_loads_any_thread, max_loads_all_threads,
130              _system, freq),
131#else
132SimpleCPU::SimpleCPU(const string &_name, Process *_process,
133                     Counter max_insts_any_thread,
134                     Counter max_insts_all_threads,
135                     Counter max_loads_any_thread,
136                     Counter max_loads_all_threads,
137                     MemInterface *icache_interface,
138                     MemInterface *dcache_interface,
139                     bool _def_reg)
140    : BaseCPU(_name, /* number_of_threads */ 1,
141              max_insts_any_thread, max_insts_all_threads,
142              max_loads_any_thread, max_loads_all_threads),
143#endif
144      tickEvent(this), xc(NULL), defer_registration(_def_reg),
145      cacheCompletionEvent(this)
146{
147    _status = Idle;
148#ifdef FULL_SYSTEM
149    xc = new ExecContext(this, 0, system, itb, dtb, mem);
150
151    // initialize CPU, including PC
152    TheISA::initCPU(&xc->regs);
153#else
154    xc = new ExecContext(this, /* thread_num */ 0, _process, /* asid */ 0);
155#endif // !FULL_SYSTEM
156
157    icacheInterface = icache_interface;
158    dcacheInterface = dcache_interface;
159
160    memReq = new MemReq();
161    memReq->xc = xc;
162    memReq->asid = 0;
163    memReq->data = new uint8_t[64];
164
165    numInst = 0;
166    startNumInst = 0;
167    numLoad = 0;
168    startNumLoad = 0;
169    lastIcacheStall = 0;
170    lastDcacheStall = 0;
171
172    execContexts.push_back(xc);
173}
174
175SimpleCPU::~SimpleCPU()
176{
177}
178
179void SimpleCPU::init()
180{
181    if (!defer_registration) {
182        this->registerExecContexts();
183    }
184}
185
186void
187SimpleCPU::switchOut()
188{
189    _status = SwitchedOut;
190    if (tickEvent.scheduled())
191        tickEvent.squash();
192}
193
194
195void
196SimpleCPU::takeOverFrom(BaseCPU *oldCPU)
197{
198    BaseCPU::takeOverFrom(oldCPU);
199
200    assert(!tickEvent.scheduled());
201
202    // if any of this CPU's ExecContexts are active, mark the CPU as
203    // running and schedule its tick event.
204    for (int i = 0; i < execContexts.size(); ++i) {
205        ExecContext *xc = execContexts[i];
206        if (xc->status() == ExecContext::Active && _status != Running) {
207            _status = Running;
208            tickEvent.schedule(curTick);
209        }
210    }
211
212    oldCPU->switchOut();
213}
214
215
216void
217SimpleCPU::activateContext(int thread_num, int delay)
218{
219    assert(thread_num == 0);
220    assert(xc);
221
222    assert(_status == Idle);
223    notIdleFraction++;
224    scheduleTickEvent(delay);
225    _status = Running;
226}
227
228
229void
230SimpleCPU::suspendContext(int thread_num)
231{
232    assert(thread_num == 0);
233    assert(xc);
234
235    assert(_status == Running);
236    notIdleFraction--;
237    unscheduleTickEvent();
238    _status = Idle;
239}
240
241
242void
243SimpleCPU::deallocateContext(int thread_num)
244{
245    // for now, these are equivalent
246    suspendContext(thread_num);
247}
248
249
250void
251SimpleCPU::haltContext(int thread_num)
252{
253    // for now, these are equivalent
254    suspendContext(thread_num);
255}
256
257
258void
259SimpleCPU::regStats()
260{
261    using namespace Stats;
262
263    BaseCPU::regStats();
264
265    numInsts
266        .name(name() + ".num_insts")
267        .desc("Number of instructions executed")
268        ;
269
270    numMemRefs
271        .name(name() + ".num_refs")
272        .desc("Number of memory references")
273        ;
274
275    notIdleFraction
276        .name(name() + ".not_idle_fraction")
277        .desc("Percentage of non-idle cycles")
278        ;
279
280    idleFraction
281        .name(name() + ".idle_fraction")
282        .desc("Percentage of idle cycles")
283        ;
284
285    icacheStallCycles
286        .name(name() + ".icache_stall_cycles")
287        .desc("ICache total stall cycles")
288        .prereq(icacheStallCycles)
289        ;
290
291    dcacheStallCycles
292        .name(name() + ".dcache_stall_cycles")
293        .desc("DCache total stall cycles")
294        .prereq(dcacheStallCycles)
295        ;
296
297    idleFraction = constant(1.0) - notIdleFraction;
298}
299
300void
301SimpleCPU::resetStats()
302{
303    startNumInst = numInst;
304    notIdleFraction = (_status != Idle);
305}
306
307void
308SimpleCPU::serialize(ostream &os)
309{
310    BaseCPU::serialize(os);
311    SERIALIZE_ENUM(_status);
312    SERIALIZE_SCALAR(inst);
313    nameOut(os, csprintf("%s.xc", name()));
314    xc->serialize(os);
315    nameOut(os, csprintf("%s.tickEvent", name()));
316    tickEvent.serialize(os);
317    nameOut(os, csprintf("%s.cacheCompletionEvent", name()));
318    cacheCompletionEvent.serialize(os);
319}
320
321void
322SimpleCPU::unserialize(Checkpoint *cp, const string &section)
323{
324    BaseCPU::unserialize(cp, section);
325    UNSERIALIZE_ENUM(_status);
326    UNSERIALIZE_SCALAR(inst);
327    xc->unserialize(cp, csprintf("%s.xc", section));
328    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
329    cacheCompletionEvent
330        .unserialize(cp, csprintf("%s.cacheCompletionEvent", section));
331}
332
333void
334change_thread_state(int thread_number, int activate, int priority)
335{
336}
337
338Fault
339SimpleCPU::copySrcTranslate(Addr src)
340{
341    static bool no_warn = true;
342    int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
343    // Only support block sizes of 64 atm.
344    assert(blk_size == 64);
345    int offset = src & (blk_size - 1);
346
347    // Make sure block doesn't span page
348    if (no_warn && (src & (~8191)) == ((src + blk_size) & (~8191))) {
349        warn("Copied block source spans pages.");
350        no_warn = false;
351    }
352
353
354    memReq->reset(src & ~(blk_size - 1), blk_size);
355
356    // translate to physical address
357    Fault fault = xc->translateDataReadReq(memReq);
358
359    assert(fault != Alignment_Fault);
360
361    if (fault == No_Fault) {
362        xc->copySrcAddr = src;
363        xc->copySrcPhysAddr = memReq->paddr + offset;
364    } else {
365        xc->copySrcAddr = 0;
366        xc->copySrcPhysAddr = 0;
367    }
368    return fault;
369}
370
371Fault
372SimpleCPU::copy(Addr dest)
373{
374    static bool no_warn = true;
375    int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
376    // Only support block sizes of 64 atm.
377    assert(blk_size == 64);
378    uint8_t data[blk_size];
379    //assert(xc->copySrcAddr);
380    int offset = dest & (blk_size - 1);
381
382    // Make sure block doesn't span page
383    if (no_warn && (dest & (~8191)) == ((dest + blk_size) & (~8191))) {
384        no_warn = false;
385        warn("Copied block destination spans pages. ");
386    }
387
388    memReq->reset(dest & ~(blk_size -1), blk_size);
389    // translate to physical address
390    Fault fault = xc->translateDataWriteReq(memReq);
391
392    assert(fault != Alignment_Fault);
393
394    if (fault == No_Fault) {
395        Addr dest_addr = memReq->paddr + offset;
396        // Need to read straight from memory since we have more than 8 bytes.
397        memReq->paddr = xc->copySrcPhysAddr;
398        xc->mem->read(memReq, data);
399        memReq->paddr = dest_addr;
400        xc->mem->write(memReq, data);
401    }
402    return fault;
403}
404
405// precise architected memory state accessor macros
406template <class T>
407Fault
408SimpleCPU::read(Addr addr, T &data, unsigned flags)
409{
410    memReq->reset(addr, sizeof(T), flags);
411
412    // translate to physical address
413    Fault fault = xc->translateDataReadReq(memReq);
414
415    // do functional access
416    if (fault == No_Fault)
417        fault = xc->read(memReq, data);
418
419    if (traceData) {
420        traceData->setAddr(addr);
421        if (fault == No_Fault)
422            traceData->setData(data);
423    }
424
425    // if we have a cache, do cache access too
426    if (fault == No_Fault && dcacheInterface) {
427        memReq->cmd = Read;
428        memReq->completionEvent = NULL;
429        memReq->time = curTick;
430        MemAccessResult result = dcacheInterface->access(memReq);
431
432        // Ugly hack to get an event scheduled *only* if the access is
433        // a miss.  We really should add first-class support for this
434        // at some point.
435        if (result != MA_HIT && dcacheInterface->doEvents()) {
436            memReq->completionEvent = &cacheCompletionEvent;
437            lastDcacheStall = curTick;
438            unscheduleTickEvent();
439            _status = DcacheMissStall;
440        }
441    }
442
443    if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
444        recordEvent("Uncached Read");
445
446    return fault;
447}
448
449#ifndef DOXYGEN_SHOULD_SKIP_THIS
450
451template
452Fault
453SimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
454
455template
456Fault
457SimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
458
459template
460Fault
461SimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
462
463template
464Fault
465SimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
466
467#endif //DOXYGEN_SHOULD_SKIP_THIS
468
469template<>
470Fault
471SimpleCPU::read(Addr addr, double &data, unsigned flags)
472{
473    return read(addr, *(uint64_t*)&data, flags);
474}
475
476template<>
477Fault
478SimpleCPU::read(Addr addr, float &data, unsigned flags)
479{
480    return read(addr, *(uint32_t*)&data, flags);
481}
482
483
484template<>
485Fault
486SimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
487{
488    return read(addr, (uint32_t&)data, flags);
489}
490
491
492template <class T>
493Fault
494SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
495{
496    if (traceData) {
497        traceData->setAddr(addr);
498        traceData->setData(data);
499    }
500
501    memReq->reset(addr, sizeof(T), flags);
502
503    // translate to physical address
504    Fault fault = xc->translateDataWriteReq(memReq);
505
506    // do functional access
507    if (fault == No_Fault)
508        fault = xc->write(memReq, data);
509
510    if (fault == No_Fault && dcacheInterface) {
511        memReq->cmd = Write;
512        memcpy(memReq->data,(uint8_t *)&data,memReq->size);
513        memReq->completionEvent = NULL;
514        memReq->time = curTick;
515        MemAccessResult result = dcacheInterface->access(memReq);
516
517        // Ugly hack to get an event scheduled *only* if the access is
518        // a miss.  We really should add first-class support for this
519        // at some point.
520        if (result != MA_HIT && dcacheInterface->doEvents()) {
521            memReq->completionEvent = &cacheCompletionEvent;
522            lastDcacheStall = curTick;
523            unscheduleTickEvent();
524            _status = DcacheMissStall;
525        }
526    }
527
528    if (res && (fault == No_Fault))
529        *res = memReq->result;
530
531    if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
532        recordEvent("Uncached Write");
533
534    return fault;
535}
536
537
538#ifndef DOXYGEN_SHOULD_SKIP_THIS
539template
540Fault
541SimpleCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res);
542
543template
544Fault
545SimpleCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res);
546
547template
548Fault
549SimpleCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res);
550
551template
552Fault
553SimpleCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res);
554
555#endif //DOXYGEN_SHOULD_SKIP_THIS
556
557template<>
558Fault
559SimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
560{
561    return write(*(uint64_t*)&data, addr, flags, res);
562}
563
564template<>
565Fault
566SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
567{
568    return write(*(uint32_t*)&data, addr, flags, res);
569}
570
571
572template<>
573Fault
574SimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
575{
576    return write((uint32_t)data, addr, flags, res);
577}
578
579
580#ifdef FULL_SYSTEM
581Addr
582SimpleCPU::dbg_vtophys(Addr addr)
583{
584    return vtophys(xc, addr);
585}
586#endif // FULL_SYSTEM
587
588Tick save_cycle = 0;
589
590
591void
592SimpleCPU::processCacheCompletion()
593{
594    switch (status()) {
595      case IcacheMissStall:
596        icacheStallCycles += curTick - lastIcacheStall;
597        _status = IcacheMissComplete;
598        scheduleTickEvent(1);
599        break;
600      case DcacheMissStall:
601        dcacheStallCycles += curTick - lastDcacheStall;
602        _status = Running;
603        scheduleTickEvent(1);
604        break;
605      case SwitchedOut:
606        // If this CPU has been switched out due to sampling/warm-up,
607        // ignore any further status changes (e.g., due to cache
608        // misses outstanding at the time of the switch).
609        return;
610      default:
611        panic("SimpleCPU::processCacheCompletion: bad state");
612        break;
613    }
614}
615
616#ifdef FULL_SYSTEM
617void
618SimpleCPU::post_interrupt(int int_num, int index)
619{
620    BaseCPU::post_interrupt(int_num, index);
621
622    if (xc->status() == ExecContext::Suspended) {
623                DPRINTF(IPI,"Suspended Processor awoke\n");
624        xc->activate();
625    }
626}
627#endif // FULL_SYSTEM
628
629/* start simulation, program loaded, processor precise state initialized */
630void
631SimpleCPU::tick()
632{
633    numCycles++;
634
635    traceData = NULL;
636
637    Fault fault = No_Fault;
638
639#ifdef FULL_SYSTEM
640    if (AlphaISA::check_interrupts &&
641        xc->cpu->check_interrupts() &&
642        !PC_PAL(xc->regs.pc) &&
643        status() != IcacheMissComplete) {
644        int ipl = 0;
645        int summary = 0;
646        AlphaISA::check_interrupts = 0;
647        IntReg *ipr = xc->regs.ipr;
648
649        if (xc->regs.ipr[TheISA::IPR_SIRR]) {
650            for (int i = TheISA::INTLEVEL_SOFTWARE_MIN;
651                 i < TheISA::INTLEVEL_SOFTWARE_MAX; i++) {
652                if (ipr[TheISA::IPR_SIRR] & (ULL(1) << i)) {
653                    // See table 4-19 of 21164 hardware reference
654                    ipl = (i - TheISA::INTLEVEL_SOFTWARE_MIN) + 1;
655                    summary |= (ULL(1) << i);
656                }
657            }
658        }
659
660        uint64_t interrupts = xc->cpu->intr_status();
661        for (int i = TheISA::INTLEVEL_EXTERNAL_MIN;
662            i < TheISA::INTLEVEL_EXTERNAL_MAX; i++) {
663            if (interrupts & (ULL(1) << i)) {
664                // See table 4-19 of 21164 hardware reference
665                ipl = i;
666                summary |= (ULL(1) << i);
667            }
668        }
669
670        if (ipr[TheISA::IPR_ASTRR])
671            panic("asynchronous traps not implemented\n");
672
673        if (ipl && ipl > xc->regs.ipr[TheISA::IPR_IPLR]) {
674            ipr[TheISA::IPR_ISR] = summary;
675            ipr[TheISA::IPR_INTID] = ipl;
676            xc->ev5_trap(Interrupt_Fault);
677
678            DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
679                    ipr[TheISA::IPR_IPLR], ipl, summary);
680        }
681    }
682#endif
683
684    // maintain $r0 semantics
685    xc->regs.intRegFile[ZeroReg] = 0;
686#ifdef TARGET_ALPHA
687    xc->regs.floatRegFile.d[ZeroReg] = 0.0;
688#endif // TARGET_ALPHA
689
690    if (status() == IcacheMissComplete) {
691        // We've already fetched an instruction and were stalled on an
692        // I-cache miss.  No need to fetch it again.
693
694        // Set status to running; tick event will get rescheduled if
695        // necessary at end of tick() function.
696        _status = Running;
697    }
698    else {
699        // Try to fetch an instruction
700
701        // set up memory request for instruction fetch
702#ifdef FULL_SYSTEM
703#define IFETCH_FLAGS(pc)	((pc) & 1) ? PHYSICAL : 0
704#else
705#define IFETCH_FLAGS(pc)	0
706#endif
707
708        memReq->cmd = Read;
709        memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t),
710                     IFETCH_FLAGS(xc->regs.pc));
711
712        fault = xc->translateInstReq(memReq);
713
714        if (fault == No_Fault)
715            fault = xc->mem->read(memReq, inst);
716
717        if (icacheInterface && fault == No_Fault) {
718            memReq->completionEvent = NULL;
719
720            memReq->time = curTick;
721            MemAccessResult result = icacheInterface->access(memReq);
722
723            // Ugly hack to get an event scheduled *only* if the access is
724            // a miss.  We really should add first-class support for this
725            // at some point.
726            if (result != MA_HIT && icacheInterface->doEvents()) {
727                memReq->completionEvent = &cacheCompletionEvent;
728                lastIcacheStall = curTick;
729                unscheduleTickEvent();
730                _status = IcacheMissStall;
731                return;
732            }
733        }
734    }
735
736    // If we've got a valid instruction (i.e., no fault on instruction
737    // fetch), then execute it.
738    if (fault == No_Fault) {
739
740        // keep an instruction count
741        numInst++;
742        numInsts++;
743
744        // check for instruction-count-based events
745        comInstEventQueue[0]->serviceEvents(numInst);
746
747        // decode the instruction
748    inst = htoa(inst);
749        StaticInstPtr<TheISA> si(inst);
750
751        traceData = Trace::getInstRecord(curTick, xc, this, si,
752                                         xc->regs.pc);
753
754#ifdef FULL_SYSTEM
755        xc->setInst(inst);
756#endif // FULL_SYSTEM
757
758        xc->func_exe_inst++;
759
760        fault = si->execute(this, traceData);
761
762#ifdef FULL_SYSTEM
763        if (xc->fnbin)
764            xc->execute(si.get());
765#endif
766
767        if (si->isMemRef()) {
768            numMemRefs++;
769        }
770
771        if (si->isLoad()) {
772            ++numLoad;
773            comLoadEventQueue[0]->serviceEvents(numLoad);
774        }
775
776        if (traceData)
777            traceData->finalize();
778
779    }	// if (fault == No_Fault)
780
781    if (fault != No_Fault) {
782#ifdef FULL_SYSTEM
783        xc->ev5_trap(fault);
784#else // !FULL_SYSTEM
785        fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc);
786#endif // FULL_SYSTEM
787    }
788    else {
789        // go to the next instruction
790        xc->regs.pc = xc->regs.npc;
791        xc->regs.npc += sizeof(MachInst);
792    }
793
794#ifdef FULL_SYSTEM
795    Addr oldpc;
796    do {
797        oldpc = xc->regs.pc;
798        system->pcEventQueue.service(xc);
799    } while (oldpc != xc->regs.pc);
800#endif
801
802    assert(status() == Running ||
803           status() == Idle ||
804           status() == DcacheMissStall);
805
806    if (status() == Running && !tickEvent.scheduled())
807        tickEvent.schedule(curTick + 1);
808}
809
810
811////////////////////////////////////////////////////////////////////////
812//
813//  SimpleCPU Simulation Object
814//
815BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
816
817    Param<Counter> max_insts_any_thread;
818    Param<Counter> max_insts_all_threads;
819    Param<Counter> max_loads_any_thread;
820    Param<Counter> max_loads_all_threads;
821
822#ifdef FULL_SYSTEM
823    SimObjectParam<AlphaITB *> itb;
824    SimObjectParam<AlphaDTB *> dtb;
825    SimObjectParam<FunctionalMemory *> mem;
826    SimObjectParam<System *> system;
827    Param<int> mult;
828#else
829    SimObjectParam<Process *> workload;
830#endif // FULL_SYSTEM
831
832    SimObjectParam<BaseMem *> icache;
833    SimObjectParam<BaseMem *> dcache;
834
835    Param<bool> defer_registration;
836    Param<int> multiplier;
837
838END_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
839
840BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
841
842    INIT_PARAM_DFLT(max_insts_any_thread,
843                    "terminate when any thread reaches this inst count",
844                    0),
845    INIT_PARAM_DFLT(max_insts_all_threads,
846                    "terminate when all threads have reached this inst count",
847                    0),
848    INIT_PARAM_DFLT(max_loads_any_thread,
849                    "terminate when any thread reaches this load count",
850                    0),
851    INIT_PARAM_DFLT(max_loads_all_threads,
852                    "terminate when all threads have reached this load count",
853                    0),
854
855#ifdef FULL_SYSTEM
856    INIT_PARAM(itb, "Instruction TLB"),
857    INIT_PARAM(dtb, "Data TLB"),
858    INIT_PARAM(mem, "memory"),
859    INIT_PARAM(system, "system object"),
860    INIT_PARAM_DFLT(mult, "system clock multiplier", 1),
861#else
862    INIT_PARAM(workload, "processes to run"),
863#endif // FULL_SYSTEM
864
865    INIT_PARAM_DFLT(icache, "L1 instruction cache object", NULL),
866    INIT_PARAM_DFLT(dcache, "L1 data cache object", NULL),
867    INIT_PARAM_DFLT(defer_registration, "defer registration with system "
868                    "(for sampling)", false),
869
870    INIT_PARAM_DFLT(multiplier, "clock multiplier", 1)
871
872END_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
873
874
875CREATE_SIM_OBJECT(SimpleCPU)
876{
877    SimpleCPU *cpu;
878#ifdef FULL_SYSTEM
879    if (mult != 1)
880        panic("processor clock multiplier must be 1\n");
881
882    cpu = new SimpleCPU(getInstanceName(), system,
883                        max_insts_any_thread, max_insts_all_threads,
884                        max_loads_any_thread, max_loads_all_threads,
885                        itb, dtb, mem,
886                        (icache) ? icache->getInterface() : NULL,
887                        (dcache) ? dcache->getInterface() : NULL,
888                        defer_registration,
889                        ticksPerSecond * mult);
890#else
891
892    cpu = new SimpleCPU(getInstanceName(), workload,
893                        max_insts_any_thread, max_insts_all_threads,
894                        max_loads_any_thread, max_loads_all_threads,
895                        (icache) ? icache->getInterface() : NULL,
896                        (dcache) ? dcache->getInterface() : NULL,
897                        defer_registration);
898
899#endif // FULL_SYSTEM
900
901    cpu->setTickMultiplier(multiplier);
902
903    return cpu;
904}
905
906REGISTER_SIM_OBJECT("SimpleCPU", SimpleCPU)
907
908