base.cc revision 1001
1/* 2 * Copyright (c) 2002-2004 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <cmath> 30#include <cstdio> 31#include <cstdlib> 32#include <iostream> 33#include <iomanip> 34#include <list> 35#include <sstream> 36#include <string> 37 38#include "base/cprintf.hh" 39#include "base/inifile.hh" 40#include "base/loader/symtab.hh" 41#include "base/misc.hh" 42#include "base/pollevent.hh" 43#include "base/range.hh" 44#include "base/trace.hh" 45#include "base/stats/events.hh" 46#include "cpu/base_cpu.hh" 47#include "cpu/exec_context.hh" 48#include "cpu/exetrace.hh" 49#include "cpu/full_cpu/smt.hh" 50#include "cpu/simple_cpu/simple_cpu.hh" 51#include "cpu/static_inst.hh" 52#include "mem/base_mem.hh" 53#include "mem/mem_interface.hh" 54#include "sim/builder.hh" 55#include "sim/debug.hh" 56#include "sim/host.hh" 57#include "sim/sim_events.hh" 58#include "sim/sim_object.hh" 59#include "sim/stats.hh" 60 61#ifdef FULL_SYSTEM 62#include "base/remote_gdb.hh" 63#include "dev/alpha_access.h" 64#include "dev/pciareg.h" 65#include "mem/functional_mem/memory_control.hh" 66#include "mem/functional_mem/physical_memory.hh" 67#include "sim/system.hh" 68#include "targetarch/alpha_memory.hh" 69#include "targetarch/vtophys.hh" 70#else // !FULL_SYSTEM 71#include "eio/eio.hh" 72#include "mem/functional_mem/functional_memory.hh" 73#endif // FULL_SYSTEM 74 75using namespace std; 76 77SimpleCPU::TickEvent::TickEvent(SimpleCPU *c) 78 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), multiplier(1) 79{ 80} 81 82void 83SimpleCPU::TickEvent::process() 84{ 85 int count = multiplier; 86 do { 87 cpu->tick(); 88 } while (--count > 0 && cpu->status() == Running); 89} 90 91const char * 92SimpleCPU::TickEvent::description() 93{ 94 return "SimpleCPU tick event"; 95} 96 97 98SimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu) 99 : Event(&mainEventQueue), 100 cpu(_cpu) 101{ 102} 103 104void SimpleCPU::CacheCompletionEvent::process() 105{ 106 cpu->processCacheCompletion(); 107} 108 109const char * 110SimpleCPU::CacheCompletionEvent::description() 111{ 112 return "SimpleCPU cache completion event"; 113} 114 115#ifdef FULL_SYSTEM 116SimpleCPU::SimpleCPU(const string &_name, 117 System *_system, 118 Counter max_insts_any_thread, 119 Counter max_insts_all_threads, 120 Counter max_loads_any_thread, 121 Counter max_loads_all_threads, 122 AlphaITB *itb, AlphaDTB *dtb, 123 FunctionalMemory *mem, 124 MemInterface *icache_interface, 125 MemInterface *dcache_interface, 126 bool _def_reg, Tick freq) 127 : BaseCPU(_name, /* number_of_threads */ 1, 128 max_insts_any_thread, max_insts_all_threads, 129 max_loads_any_thread, max_loads_all_threads, 130 _system, freq), 131#else 132SimpleCPU::SimpleCPU(const string &_name, Process *_process, 133 Counter max_insts_any_thread, 134 Counter max_insts_all_threads, 135 Counter max_loads_any_thread, 136 Counter max_loads_all_threads, 137 MemInterface *icache_interface, 138 MemInterface *dcache_interface, 139 bool _def_reg) 140 : BaseCPU(_name, /* number_of_threads */ 1, 141 max_insts_any_thread, max_insts_all_threads, 142 max_loads_any_thread, max_loads_all_threads), 143#endif 144 tickEvent(this), xc(NULL), defer_registration(_def_reg), 145 cacheCompletionEvent(this) 146{ 147 _status = Idle; 148#ifdef FULL_SYSTEM 149 xc = new ExecContext(this, 0, system, itb, dtb, mem); 150 151 // initialize CPU, including PC 152 TheISA::initCPU(&xc->regs); 153#else 154 xc = new ExecContext(this, /* thread_num */ 0, _process, /* asid */ 0); 155#endif // !FULL_SYSTEM 156 157 icacheInterface = icache_interface; 158 dcacheInterface = dcache_interface; 159 160 memReq = new MemReq(); 161 memReq->xc = xc; 162 memReq->asid = 0; 163 memReq->data = new uint8_t[64]; 164 165 numInst = 0; 166 startNumInst = 0; 167 numLoad = 0; 168 startNumLoad = 0; 169 lastIcacheStall = 0; 170 lastDcacheStall = 0; 171 172 execContexts.push_back(xc); 173} 174 175SimpleCPU::~SimpleCPU() 176{ 177} 178 179void SimpleCPU::init() 180{ 181 if (!defer_registration) { 182 this->registerExecContexts(); 183 } 184} 185 186void 187SimpleCPU::switchOut() 188{ 189 _status = SwitchedOut; 190 if (tickEvent.scheduled()) 191 tickEvent.squash(); 192} 193 194 195void 196SimpleCPU::takeOverFrom(BaseCPU *oldCPU) 197{ 198 BaseCPU::takeOverFrom(oldCPU); 199 200 assert(!tickEvent.scheduled()); 201 202 // if any of this CPU's ExecContexts are active, mark the CPU as 203 // running and schedule its tick event. 204 for (int i = 0; i < execContexts.size(); ++i) { 205 ExecContext *xc = execContexts[i]; 206 if (xc->status() == ExecContext::Active && _status != Running) { 207 _status = Running; 208 tickEvent.schedule(curTick); 209 } 210 } 211 212 oldCPU->switchOut(); 213} 214 215 216void 217SimpleCPU::activateContext(int thread_num, int delay) 218{ 219 assert(thread_num == 0); 220 assert(xc); 221 222 assert(_status == Idle); 223 notIdleFraction++; 224 scheduleTickEvent(delay); 225 _status = Running; 226} 227 228 229void 230SimpleCPU::suspendContext(int thread_num) 231{ 232 assert(thread_num == 0); 233 assert(xc); 234 235 assert(_status == Running); 236 notIdleFraction--; 237 unscheduleTickEvent(); 238 _status = Idle; 239} 240 241 242void 243SimpleCPU::deallocateContext(int thread_num) 244{ 245 // for now, these are equivalent 246 suspendContext(thread_num); 247} 248 249 250void 251SimpleCPU::haltContext(int thread_num) 252{ 253 // for now, these are equivalent 254 suspendContext(thread_num); 255} 256 257 258void 259SimpleCPU::regStats() 260{ 261 using namespace Stats; 262 263 BaseCPU::regStats(); 264 265 numInsts 266 .name(name() + ".num_insts") 267 .desc("Number of instructions executed") 268 ; 269 270 numMemRefs 271 .name(name() + ".num_refs") 272 .desc("Number of memory references") 273 ; 274 275 notIdleFraction 276 .name(name() + ".not_idle_fraction") 277 .desc("Percentage of non-idle cycles") 278 ; 279 280 idleFraction 281 .name(name() + ".idle_fraction") 282 .desc("Percentage of idle cycles") 283 ; 284 285 icacheStallCycles 286 .name(name() + ".icache_stall_cycles") 287 .desc("ICache total stall cycles") 288 .prereq(icacheStallCycles) 289 ; 290 291 dcacheStallCycles 292 .name(name() + ".dcache_stall_cycles") 293 .desc("DCache total stall cycles") 294 .prereq(dcacheStallCycles) 295 ; 296 297 idleFraction = constant(1.0) - notIdleFraction; 298} 299 300void 301SimpleCPU::resetStats() 302{ 303 startNumInst = numInst; 304 notIdleFraction = (_status != Idle); 305} 306 307void 308SimpleCPU::serialize(ostream &os) 309{ 310 BaseCPU::serialize(os); 311 SERIALIZE_ENUM(_status); 312 SERIALIZE_SCALAR(inst); 313 nameOut(os, csprintf("%s.xc", name())); 314 xc->serialize(os); 315 nameOut(os, csprintf("%s.tickEvent", name())); 316 tickEvent.serialize(os); 317 nameOut(os, csprintf("%s.cacheCompletionEvent", name())); 318 cacheCompletionEvent.serialize(os); 319} 320 321void 322SimpleCPU::unserialize(Checkpoint *cp, const string §ion) 323{ 324 BaseCPU::unserialize(cp, section); 325 UNSERIALIZE_ENUM(_status); 326 UNSERIALIZE_SCALAR(inst); 327 xc->unserialize(cp, csprintf("%s.xc", section)); 328 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 329 cacheCompletionEvent 330 .unserialize(cp, csprintf("%s.cacheCompletionEvent", section)); 331} 332 333void 334change_thread_state(int thread_number, int activate, int priority) 335{ 336} 337 338Fault 339SimpleCPU::copySrcTranslate(Addr src) 340{ 341 memReq->reset(src, (dcacheInterface) ? 342 dcacheInterface->getBlockSize() 343 : 64); 344 345 // translate to physical address 346 Fault fault = xc->translateDataReadReq(memReq); 347 348 if (fault == No_Fault) { 349 xc->copySrcAddr = src; 350 xc->copySrcPhysAddr = memReq->paddr; 351 } else { 352 xc->copySrcAddr = 0; 353 xc->copySrcPhysAddr = 0; 354 } 355 return fault; 356} 357 358Fault 359SimpleCPU::copy(Addr dest) 360{ 361 int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 362 uint8_t data[blk_size]; 363 assert(xc->copySrcAddr); 364 memReq->reset(dest, blk_size); 365 // translate to physical address 366 Fault fault = xc->translateDataWriteReq(memReq); 367 if (fault == No_Fault) { 368 Addr dest_addr = memReq->paddr; 369 // Need to read straight from memory since we have more than 8 bytes. 370 memReq->paddr = xc->copySrcPhysAddr; 371 xc->mem->read(memReq, data); 372 memReq->paddr = dest_addr; 373 xc->mem->write(memReq, data); 374 } 375 return fault; 376} 377 378// precise architected memory state accessor macros 379template <class T> 380Fault 381SimpleCPU::read(Addr addr, T &data, unsigned flags) 382{ 383 memReq->reset(addr, sizeof(T), flags); 384 385 // translate to physical address 386 Fault fault = xc->translateDataReadReq(memReq); 387 388 // do functional access 389 if (fault == No_Fault) 390 fault = xc->read(memReq, data); 391 392 if (traceData) { 393 traceData->setAddr(addr); 394 if (fault == No_Fault) 395 traceData->setData(data); 396 } 397 398 // if we have a cache, do cache access too 399 if (fault == No_Fault && dcacheInterface) { 400 memReq->cmd = Read; 401 memReq->completionEvent = NULL; 402 memReq->time = curTick; 403 MemAccessResult result = dcacheInterface->access(memReq); 404 405 // Ugly hack to get an event scheduled *only* if the access is 406 // a miss. We really should add first-class support for this 407 // at some point. 408 if (result != MA_HIT && dcacheInterface->doEvents()) { 409 memReq->completionEvent = &cacheCompletionEvent; 410 lastDcacheStall = curTick; 411 unscheduleTickEvent(); 412 _status = DcacheMissStall; 413 } 414 } 415 416 if (!dcacheInterface && (memReq->flags & UNCACHEABLE)) 417 recordEvent("Uncached Read"); 418 419 return fault; 420} 421 422#ifndef DOXYGEN_SHOULD_SKIP_THIS 423 424template 425Fault 426SimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 427 428template 429Fault 430SimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 431 432template 433Fault 434SimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 435 436template 437Fault 438SimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 439 440#endif //DOXYGEN_SHOULD_SKIP_THIS 441 442template<> 443Fault 444SimpleCPU::read(Addr addr, double &data, unsigned flags) 445{ 446 return read(addr, *(uint64_t*)&data, flags); 447} 448 449template<> 450Fault 451SimpleCPU::read(Addr addr, float &data, unsigned flags) 452{ 453 return read(addr, *(uint32_t*)&data, flags); 454} 455 456 457template<> 458Fault 459SimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 460{ 461 return read(addr, (uint32_t&)data, flags); 462} 463 464 465template <class T> 466Fault 467SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 468{ 469 if (traceData) { 470 traceData->setAddr(addr); 471 traceData->setData(data); 472 } 473 474 memReq->reset(addr, sizeof(T), flags); 475 476 // translate to physical address 477 Fault fault = xc->translateDataWriteReq(memReq); 478 479 // do functional access 480 if (fault == No_Fault) 481 fault = xc->write(memReq, data); 482 483 if (fault == No_Fault && dcacheInterface) { 484 memReq->cmd = Write; 485 memcpy(memReq->data,(uint8_t *)&data,memReq->size); 486 memReq->completionEvent = NULL; 487 memReq->time = curTick; 488 MemAccessResult result = dcacheInterface->access(memReq); 489 490 // Ugly hack to get an event scheduled *only* if the access is 491 // a miss. We really should add first-class support for this 492 // at some point. 493 if (result != MA_HIT && dcacheInterface->doEvents()) { 494 memReq->completionEvent = &cacheCompletionEvent; 495 lastDcacheStall = curTick; 496 unscheduleTickEvent(); 497 _status = DcacheMissStall; 498 } 499 } 500 501 if (res && (fault == No_Fault)) 502 *res = memReq->result; 503 504 if (!dcacheInterface && (memReq->flags & UNCACHEABLE)) 505 recordEvent("Uncached Write"); 506 507 return fault; 508} 509 510 511#ifndef DOXYGEN_SHOULD_SKIP_THIS 512template 513Fault 514SimpleCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res); 515 516template 517Fault 518SimpleCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res); 519 520template 521Fault 522SimpleCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res); 523 524template 525Fault 526SimpleCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res); 527 528#endif //DOXYGEN_SHOULD_SKIP_THIS 529 530template<> 531Fault 532SimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 533{ 534 return write(*(uint64_t*)&data, addr, flags, res); 535} 536 537template<> 538Fault 539SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 540{ 541 return write(*(uint32_t*)&data, addr, flags, res); 542} 543 544 545template<> 546Fault 547SimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 548{ 549 return write((uint32_t)data, addr, flags, res); 550} 551 552 553#ifdef FULL_SYSTEM 554Addr 555SimpleCPU::dbg_vtophys(Addr addr) 556{ 557 return vtophys(xc, addr); 558} 559#endif // FULL_SYSTEM 560 561Tick save_cycle = 0; 562 563 564void 565SimpleCPU::processCacheCompletion() 566{ 567 switch (status()) { 568 case IcacheMissStall: 569 icacheStallCycles += curTick - lastIcacheStall; 570 _status = IcacheMissComplete; 571 scheduleTickEvent(1); 572 break; 573 case DcacheMissStall: 574 dcacheStallCycles += curTick - lastDcacheStall; 575 _status = Running; 576 scheduleTickEvent(1); 577 break; 578 case SwitchedOut: 579 // If this CPU has been switched out due to sampling/warm-up, 580 // ignore any further status changes (e.g., due to cache 581 // misses outstanding at the time of the switch). 582 return; 583 default: 584 panic("SimpleCPU::processCacheCompletion: bad state"); 585 break; 586 } 587} 588 589#ifdef FULL_SYSTEM 590void 591SimpleCPU::post_interrupt(int int_num, int index) 592{ 593 BaseCPU::post_interrupt(int_num, index); 594 595 if (xc->status() == ExecContext::Suspended) { 596 DPRINTF(IPI,"Suspended Processor awoke\n"); 597 xc->activate(); 598 } 599} 600#endif // FULL_SYSTEM 601 602/* start simulation, program loaded, processor precise state initialized */ 603void 604SimpleCPU::tick() 605{ 606 numCycles++; 607 608 traceData = NULL; 609 610 Fault fault = No_Fault; 611 612#ifdef FULL_SYSTEM 613 if (AlphaISA::check_interrupts && 614 xc->cpu->check_interrupts() && 615 !PC_PAL(xc->regs.pc) && 616 status() != IcacheMissComplete) { 617 int ipl = 0; 618 int summary = 0; 619 AlphaISA::check_interrupts = 0; 620 IntReg *ipr = xc->regs.ipr; 621 622 if (xc->regs.ipr[TheISA::IPR_SIRR]) { 623 for (int i = TheISA::INTLEVEL_SOFTWARE_MIN; 624 i < TheISA::INTLEVEL_SOFTWARE_MAX; i++) { 625 if (ipr[TheISA::IPR_SIRR] & (ULL(1) << i)) { 626 // See table 4-19 of 21164 hardware reference 627 ipl = (i - TheISA::INTLEVEL_SOFTWARE_MIN) + 1; 628 summary |= (ULL(1) << i); 629 } 630 } 631 } 632 633 uint64_t interrupts = xc->cpu->intr_status(); 634 for (int i = TheISA::INTLEVEL_EXTERNAL_MIN; 635 i < TheISA::INTLEVEL_EXTERNAL_MAX; i++) { 636 if (interrupts & (ULL(1) << i)) { 637 // See table 4-19 of 21164 hardware reference 638 ipl = i; 639 summary |= (ULL(1) << i); 640 } 641 } 642 643 if (ipr[TheISA::IPR_ASTRR]) 644 panic("asynchronous traps not implemented\n"); 645 646 if (ipl && ipl > xc->regs.ipr[TheISA::IPR_IPLR]) { 647 ipr[TheISA::IPR_ISR] = summary; 648 ipr[TheISA::IPR_INTID] = ipl; 649 xc->ev5_trap(Interrupt_Fault); 650 651 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", 652 ipr[TheISA::IPR_IPLR], ipl, summary); 653 } 654 } 655#endif 656 657 // maintain $r0 semantics 658 xc->regs.intRegFile[ZeroReg] = 0; 659#ifdef TARGET_ALPHA 660 xc->regs.floatRegFile.d[ZeroReg] = 0.0; 661#endif // TARGET_ALPHA 662 663 if (status() == IcacheMissComplete) { 664 // We've already fetched an instruction and were stalled on an 665 // I-cache miss. No need to fetch it again. 666 667 // Set status to running; tick event will get rescheduled if 668 // necessary at end of tick() function. 669 _status = Running; 670 } 671 else { 672 // Try to fetch an instruction 673 674 // set up memory request for instruction fetch 675#ifdef FULL_SYSTEM 676#define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0 677#else 678#define IFETCH_FLAGS(pc) 0 679#endif 680 681 memReq->cmd = Read; 682 memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t), 683 IFETCH_FLAGS(xc->regs.pc)); 684 685 fault = xc->translateInstReq(memReq); 686 687 if (fault == No_Fault) 688 fault = xc->mem->read(memReq, inst); 689 690 if (icacheInterface && fault == No_Fault) { 691 memReq->completionEvent = NULL; 692 693 memReq->time = curTick; 694 MemAccessResult result = icacheInterface->access(memReq); 695 696 // Ugly hack to get an event scheduled *only* if the access is 697 // a miss. We really should add first-class support for this 698 // at some point. 699 if (result != MA_HIT && icacheInterface->doEvents()) { 700 memReq->completionEvent = &cacheCompletionEvent; 701 lastIcacheStall = curTick; 702 unscheduleTickEvent(); 703 _status = IcacheMissStall; 704 return; 705 } 706 } 707 } 708 709 // If we've got a valid instruction (i.e., no fault on instruction 710 // fetch), then execute it. 711 if (fault == No_Fault) { 712 713 // keep an instruction count 714 numInst++; 715 numInsts++; 716 717 // check for instruction-count-based events 718 comInstEventQueue[0]->serviceEvents(numInst); 719 720 // decode the instruction 721 inst = htoa(inst); 722 StaticInstPtr<TheISA> si(inst); 723 724 traceData = Trace::getInstRecord(curTick, xc, this, si, 725 xc->regs.pc); 726 727#ifdef FULL_SYSTEM 728 xc->setInst(inst); 729#endif // FULL_SYSTEM 730 731 xc->func_exe_inst++; 732 733 fault = si->execute(this, traceData); 734 735#ifdef FULL_SYSTEM 736 SWContext *ctx = xc->swCtx; 737 if (ctx) 738 ctx->process(xc, si.get()); 739#endif 740 741 if (si->isMemRef()) { 742 numMemRefs++; 743 } 744 745 if (si->isLoad()) { 746 ++numLoad; 747 comLoadEventQueue[0]->serviceEvents(numLoad); 748 } 749 750 if (traceData) 751 traceData->finalize(); 752 753 } // if (fault == No_Fault) 754 755 if (fault != No_Fault) { 756#ifdef FULL_SYSTEM 757 xc->ev5_trap(fault); 758#else // !FULL_SYSTEM 759 fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc); 760#endif // FULL_SYSTEM 761 } 762 else { 763 // go to the next instruction 764 xc->regs.pc = xc->regs.npc; 765 xc->regs.npc += sizeof(MachInst); 766 } 767 768#ifdef FULL_SYSTEM 769 Addr oldpc; 770 do { 771 oldpc = xc->regs.pc; 772 system->pcEventQueue.service(xc); 773 } while (oldpc != xc->regs.pc); 774#endif 775 776 assert(status() == Running || 777 status() == Idle || 778 status() == DcacheMissStall); 779 780 if (status() == Running && !tickEvent.scheduled()) 781 tickEvent.schedule(curTick + 1); 782} 783 784 785//////////////////////////////////////////////////////////////////////// 786// 787// SimpleCPU Simulation Object 788// 789BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU) 790 791 Param<Counter> max_insts_any_thread; 792 Param<Counter> max_insts_all_threads; 793 Param<Counter> max_loads_any_thread; 794 Param<Counter> max_loads_all_threads; 795 796#ifdef FULL_SYSTEM 797 SimObjectParam<AlphaITB *> itb; 798 SimObjectParam<AlphaDTB *> dtb; 799 SimObjectParam<FunctionalMemory *> mem; 800 SimObjectParam<System *> system; 801 Param<int> mult; 802#else 803 SimObjectParam<Process *> workload; 804#endif // FULL_SYSTEM 805 806 SimObjectParam<BaseMem *> icache; 807 SimObjectParam<BaseMem *> dcache; 808 809 Param<bool> defer_registration; 810 Param<int> multiplier; 811 812END_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU) 813 814BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU) 815 816 INIT_PARAM_DFLT(max_insts_any_thread, 817 "terminate when any thread reaches this inst count", 818 0), 819 INIT_PARAM_DFLT(max_insts_all_threads, 820 "terminate when all threads have reached this inst count", 821 0), 822 INIT_PARAM_DFLT(max_loads_any_thread, 823 "terminate when any thread reaches this load count", 824 0), 825 INIT_PARAM_DFLT(max_loads_all_threads, 826 "terminate when all threads have reached this load count", 827 0), 828 829#ifdef FULL_SYSTEM 830 INIT_PARAM(itb, "Instruction TLB"), 831 INIT_PARAM(dtb, "Data TLB"), 832 INIT_PARAM(mem, "memory"), 833 INIT_PARAM(system, "system object"), 834 INIT_PARAM_DFLT(mult, "system clock multiplier", 1), 835#else 836 INIT_PARAM(workload, "processes to run"), 837#endif // FULL_SYSTEM 838 839 INIT_PARAM_DFLT(icache, "L1 instruction cache object", NULL), 840 INIT_PARAM_DFLT(dcache, "L1 data cache object", NULL), 841 INIT_PARAM_DFLT(defer_registration, "defer registration with system " 842 "(for sampling)", false), 843 844 INIT_PARAM_DFLT(multiplier, "clock multiplier", 1) 845 846END_INIT_SIM_OBJECT_PARAMS(SimpleCPU) 847 848 849CREATE_SIM_OBJECT(SimpleCPU) 850{ 851 SimpleCPU *cpu; 852#ifdef FULL_SYSTEM 853 if (mult != 1) 854 panic("processor clock multiplier must be 1\n"); 855 856 cpu = new SimpleCPU(getInstanceName(), system, 857 max_insts_any_thread, max_insts_all_threads, 858 max_loads_any_thread, max_loads_all_threads, 859 itb, dtb, mem, 860 (icache) ? icache->getInterface() : NULL, 861 (dcache) ? dcache->getInterface() : NULL, 862 defer_registration, 863 ticksPerSecond * mult); 864#else 865 866 cpu = new SimpleCPU(getInstanceName(), workload, 867 max_insts_any_thread, max_insts_all_threads, 868 max_loads_any_thread, max_loads_all_threads, 869 (icache) ? icache->getInterface() : NULL, 870 (dcache) ? dcache->getInterface() : NULL, 871 defer_registration); 872 873#endif // FULL_SYSTEM 874 875 cpu->setTickMultiplier(multiplier); 876 877 return cpu; 878} 879 880REGISTER_SIM_OBJECT("SimpleCPU", SimpleCPU) 881 882