base.cc revision 8232
12SN/A/* 27338SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37338SAli.Saidi@ARM.com * All rights reserved 47338SAli.Saidi@ARM.com * 57338SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67338SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77338SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87338SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97338SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107338SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117338SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127338SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137338SAli.Saidi@ARM.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152SN/A * All rights reserved. 162SN/A * 172SN/A * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272SN/A * 282SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412SN/A */ 422SN/A 436216Snate@binkert.org#include "arch/faults.hh" 442439SN/A#include "arch/utility.hh" 458229Snate@binkert.org#include "base/loader/symtab.hh" 466216Snate@binkert.org#include "base/cp_annotate.hh" 47146SN/A#include "base/cprintf.hh" 48146SN/A#include "base/inifile.hh" 49146SN/A#include "base/misc.hh" 50146SN/A#include "base/pollevent.hh" 51146SN/A#include "base/range.hh" 52146SN/A#include "base/trace.hh" 536216Snate@binkert.org#include "base/types.hh" 546658Snate@binkert.org#include "config/the_isa.hh" 558229Snate@binkert.org#include "cpu/simple/base.hh" 561717SN/A#include "cpu/base.hh" 57146SN/A#include "cpu/exetrace.hh" 581977SN/A#include "cpu/profile.hh" 592683Sktlim@umich.edu#include "cpu/simple_thread.hh" 601717SN/A#include "cpu/smt.hh" 61146SN/A#include "cpu/static_inst.hh" 622683Sktlim@umich.edu#include "cpu/thread_context.hh" 638232Snate@binkert.org#include "debug/Decode.hh" 648232Snate@binkert.org#include "debug/Fetch.hh" 658232Snate@binkert.org#include "debug/Quiesce.hh" 663348Sbinkertn@umich.edu#include "mem/packet.hh" 676105Ssteve.reinhardt@amd.com#include "mem/request.hh" 686216Snate@binkert.org#include "params/BaseSimpleCPU.hh" 692036SN/A#include "sim/byteswap.hh" 70146SN/A#include "sim/debug.hh" 7156SN/A#include "sim/sim_events.hh" 7256SN/A#include "sim/sim_object.hh" 73695SN/A#include "sim/stats.hh" 742901Ssaidi@eecs.umich.edu#include "sim/system.hh" 752SN/A 761858SN/A#if FULL_SYSTEM 773565Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 783565Sgblack@eecs.umich.edu#include "arch/stacktrace.hh" 792171SN/A#include "arch/tlb.hh" 802170SN/A#include "arch/vtophys.hh" 81146SN/A#else // !FULL_SYSTEM 822462SN/A#include "mem/mem_object.hh" 83146SN/A#endif // FULL_SYSTEM 842SN/A 852SN/Ausing namespace std; 862449SN/Ausing namespace TheISA; 871355SN/A 885529Snate@binkert.orgBaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p) 894495Sacolyte@umich.edu : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL) 90224SN/A{ 911858SN/A#if FULL_SYSTEM 922683Sktlim@umich.edu thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb); 932420SN/A#else 945529Snate@binkert.org thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0], 956331Sgblack@eecs.umich.edu p->itb, p->dtb); 962420SN/A#endif // !FULL_SYSTEM 972SN/A 986029Ssteve.reinhardt@amd.com thread->setStatus(ThreadContext::Halted); 992672Sktlim@umich.edu 1002683Sktlim@umich.edu tc = thread->getTC(); 1012SN/A 1022SN/A numInst = 0; 103334SN/A startNumInst = 0; 104140SN/A numLoad = 0; 105334SN/A startNumLoad = 0; 1062SN/A lastIcacheStall = 0; 1072SN/A lastDcacheStall = 0; 1082SN/A 1092680Sktlim@umich.edu threadContexts.push_back(tc); 1104377Sgblack@eecs.umich.edu 1115169Ssaidi@eecs.umich.edu 1124377Sgblack@eecs.umich.edu fetchOffset = 0; 1134377Sgblack@eecs.umich.edu stayAtPC = false; 1142SN/A} 1152SN/A 1162623SN/ABaseSimpleCPU::~BaseSimpleCPU() 1172SN/A{ 1182SN/A} 1192SN/A 120180SN/Avoid 1212623SN/ABaseSimpleCPU::deallocateContext(int thread_num) 122393SN/A{ 123393SN/A // for now, these are equivalent 124393SN/A suspendContext(thread_num); 125393SN/A} 126384SN/A 127384SN/A 128393SN/Avoid 1292623SN/ABaseSimpleCPU::haltContext(int thread_num) 130393SN/A{ 131393SN/A // for now, these are equivalent 132393SN/A suspendContext(thread_num); 133393SN/A} 134384SN/A 135189SN/A 136189SN/Avoid 1372623SN/ABaseSimpleCPU::regStats() 1382SN/A{ 139729SN/A using namespace Stats; 140334SN/A 1412SN/A BaseCPU::regStats(); 1422SN/A 1432SN/A numInsts 1442SN/A .name(name() + ".num_insts") 1452SN/A .desc("Number of instructions executed") 1462SN/A ; 1472SN/A 1487897Shestness@cs.utexas.edu numIntAluAccesses 1497897Shestness@cs.utexas.edu .name(name() + ".num_int_alu_accesses") 1507897Shestness@cs.utexas.edu .desc("Number of integer alu accesses") 1517897Shestness@cs.utexas.edu ; 1527897Shestness@cs.utexas.edu 1537897Shestness@cs.utexas.edu numFpAluAccesses 1547897Shestness@cs.utexas.edu .name(name() + ".num_fp_alu_accesses") 1557897Shestness@cs.utexas.edu .desc("Number of float alu accesses") 1567897Shestness@cs.utexas.edu ; 1577897Shestness@cs.utexas.edu 1587897Shestness@cs.utexas.edu numCallsReturns 1597897Shestness@cs.utexas.edu .name(name() + ".num_func_calls") 1607897Shestness@cs.utexas.edu .desc("number of times a function call or return occured") 1617897Shestness@cs.utexas.edu ; 1627897Shestness@cs.utexas.edu 1637897Shestness@cs.utexas.edu numCondCtrlInsts 1647897Shestness@cs.utexas.edu .name(name() + ".num_conditional_control_insts") 1657897Shestness@cs.utexas.edu .desc("number of instructions that are conditional controls") 1667897Shestness@cs.utexas.edu ; 1677897Shestness@cs.utexas.edu 1687897Shestness@cs.utexas.edu numIntInsts 1697897Shestness@cs.utexas.edu .name(name() + ".num_int_insts") 1707897Shestness@cs.utexas.edu .desc("number of integer instructions") 1717897Shestness@cs.utexas.edu ; 1727897Shestness@cs.utexas.edu 1737897Shestness@cs.utexas.edu numFpInsts 1747897Shestness@cs.utexas.edu .name(name() + ".num_fp_insts") 1757897Shestness@cs.utexas.edu .desc("number of float instructions") 1767897Shestness@cs.utexas.edu ; 1777897Shestness@cs.utexas.edu 1787897Shestness@cs.utexas.edu numIntRegReads 1797897Shestness@cs.utexas.edu .name(name() + ".num_int_register_reads") 1807897Shestness@cs.utexas.edu .desc("number of times the integer registers were read") 1817897Shestness@cs.utexas.edu ; 1827897Shestness@cs.utexas.edu 1837897Shestness@cs.utexas.edu numIntRegWrites 1847897Shestness@cs.utexas.edu .name(name() + ".num_int_register_writes") 1857897Shestness@cs.utexas.edu .desc("number of times the integer registers were written") 1867897Shestness@cs.utexas.edu ; 1877897Shestness@cs.utexas.edu 1887897Shestness@cs.utexas.edu numFpRegReads 1897897Shestness@cs.utexas.edu .name(name() + ".num_fp_register_reads") 1907897Shestness@cs.utexas.edu .desc("number of times the floating registers were read") 1917897Shestness@cs.utexas.edu ; 1927897Shestness@cs.utexas.edu 1937897Shestness@cs.utexas.edu numFpRegWrites 1947897Shestness@cs.utexas.edu .name(name() + ".num_fp_register_writes") 1957897Shestness@cs.utexas.edu .desc("number of times the floating registers were written") 1967897Shestness@cs.utexas.edu ; 1977897Shestness@cs.utexas.edu 1982SN/A numMemRefs 1997897Shestness@cs.utexas.edu .name(name()+".num_mem_refs") 2007897Shestness@cs.utexas.edu .desc("number of memory refs") 2017897Shestness@cs.utexas.edu ; 2027897Shestness@cs.utexas.edu 2037897Shestness@cs.utexas.edu numStoreInsts 2047897Shestness@cs.utexas.edu .name(name() + ".num_store_insts") 2057897Shestness@cs.utexas.edu .desc("Number of store instructions") 2067897Shestness@cs.utexas.edu ; 2077897Shestness@cs.utexas.edu 2087897Shestness@cs.utexas.edu numLoadInsts 2097897Shestness@cs.utexas.edu .name(name() + ".num_load_insts") 2107897Shestness@cs.utexas.edu .desc("Number of load instructions") 2112SN/A ; 2122SN/A 2131001SN/A notIdleFraction 2141001SN/A .name(name() + ".not_idle_fraction") 2151001SN/A .desc("Percentage of non-idle cycles") 2161001SN/A ; 2171001SN/A 2182SN/A idleFraction 2192SN/A .name(name() + ".idle_fraction") 2202SN/A .desc("Percentage of idle cycles") 2212SN/A ; 2222SN/A 2237897Shestness@cs.utexas.edu numBusyCycles 2247897Shestness@cs.utexas.edu .name(name() + ".num_busy_cycles") 2257897Shestness@cs.utexas.edu .desc("Number of busy cycles") 2267897Shestness@cs.utexas.edu ; 2277897Shestness@cs.utexas.edu 2287897Shestness@cs.utexas.edu numIdleCycles 2297897Shestness@cs.utexas.edu .name(name()+".num_idle_cycles") 2307897Shestness@cs.utexas.edu .desc("Number of idle cycles") 2317897Shestness@cs.utexas.edu ; 2327897Shestness@cs.utexas.edu 2332SN/A icacheStallCycles 2342SN/A .name(name() + ".icache_stall_cycles") 2352SN/A .desc("ICache total stall cycles") 2362SN/A .prereq(icacheStallCycles) 2372SN/A ; 2382SN/A 2392SN/A dcacheStallCycles 2402SN/A .name(name() + ".dcache_stall_cycles") 2412SN/A .desc("DCache total stall cycles") 2422SN/A .prereq(dcacheStallCycles) 2432SN/A ; 2442SN/A 2452390SN/A icacheRetryCycles 2462390SN/A .name(name() + ".icache_retry_cycles") 2472390SN/A .desc("ICache total retry cycles") 2482390SN/A .prereq(icacheRetryCycles) 2492390SN/A ; 2502390SN/A 2512390SN/A dcacheRetryCycles 2522390SN/A .name(name() + ".dcache_retry_cycles") 2532390SN/A .desc("DCache total retry cycles") 2542390SN/A .prereq(dcacheRetryCycles) 2552390SN/A ; 2562390SN/A 257385SN/A idleFraction = constant(1.0) - notIdleFraction; 2587897Shestness@cs.utexas.edu numIdleCycles = idleFraction * numCycles; 2597897Shestness@cs.utexas.edu numBusyCycles = (notIdleFraction)*numCycles; 2602SN/A} 2612SN/A 2622SN/Avoid 2632623SN/ABaseSimpleCPU::resetStats() 264334SN/A{ 2652361SN/A// startNumInst = numInst; 2665496Ssaidi@eecs.umich.edu notIdleFraction = (_status != Idle); 267334SN/A} 268334SN/A 269334SN/Avoid 2702623SN/ABaseSimpleCPU::serialize(ostream &os) 2712SN/A{ 2725496Ssaidi@eecs.umich.edu SERIALIZE_ENUM(_status); 273921SN/A BaseCPU::serialize(os); 2742915Sktlim@umich.edu// SERIALIZE_SCALAR(inst); 2752915Sktlim@umich.edu nameOut(os, csprintf("%s.xc.0", name())); 2762683Sktlim@umich.edu thread->serialize(os); 2772SN/A} 2782SN/A 2792SN/Avoid 2802623SN/ABaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 2812SN/A{ 2825496Ssaidi@eecs.umich.edu UNSERIALIZE_ENUM(_status); 283921SN/A BaseCPU::unserialize(cp, section); 2842915Sktlim@umich.edu// UNSERIALIZE_SCALAR(inst); 2852915Sktlim@umich.edu thread->unserialize(cp, csprintf("%s.xc.0", section)); 2862SN/A} 2872SN/A 2882SN/Avoid 2896221Snate@binkert.orgchange_thread_state(ThreadID tid, int activate, int priority) 2902SN/A{ 2912SN/A} 2922SN/A 2931858SN/A#if FULL_SYSTEM 2942SN/AAddr 2952623SN/ABaseSimpleCPU::dbg_vtophys(Addr addr) 2962SN/A{ 2972680Sktlim@umich.edu return vtophys(tc, addr); 2982SN/A} 2992SN/A#endif // FULL_SYSTEM 3002SN/A 3011858SN/A#if FULL_SYSTEM 3022SN/Avoid 3035807Snate@binkert.orgBaseSimpleCPU::wakeup() 3042SN/A{ 3055807Snate@binkert.org if (thread->status() != ThreadContext::Suspended) 3065807Snate@binkert.org return; 3072SN/A 3085807Snate@binkert.org DPRINTF(Quiesce,"Suspended Processor awoke\n"); 3095807Snate@binkert.org thread->activate(); 3102SN/A} 3112SN/A#endif // FULL_SYSTEM 3122SN/A 3132SN/Avoid 3142623SN/ABaseSimpleCPU::checkForInterrupts() 3152SN/A{ 3161858SN/A#if FULL_SYSTEM 3175704Snate@binkert.org if (checkInterrupts(tc)) { 3185647Sgblack@eecs.umich.edu Fault interrupt = interrupts->getInterrupt(tc); 3192SN/A 3203520Sgblack@eecs.umich.edu if (interrupt != NoFault) { 3217338SAli.Saidi@ARM.com fetchOffset = 0; 3225647Sgblack@eecs.umich.edu interrupts->updateIntrInfo(tc); 3233520Sgblack@eecs.umich.edu interrupt->invoke(tc); 3247408Sgblack@eecs.umich.edu predecoder.reset(); 3252SN/A } 3262SN/A } 3272SN/A#endif 3282623SN/A} 3292SN/A 3302623SN/A 3315894Sgblack@eecs.umich.eduvoid 3322662Sstever@eecs.umich.eduBaseSimpleCPU::setupFetchRequest(Request *req) 3332623SN/A{ 3347720Sgblack@eecs.umich.edu Addr instAddr = thread->instAddr(); 3354495Sacolyte@umich.edu 3362623SN/A // set up memory request for instruction fetch 3377720Sgblack@eecs.umich.edu DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr); 3382623SN/A 3397720Sgblack@eecs.umich.edu Addr fetchPC = (instAddr & PCMask) + fetchOffset; 3407720Sgblack@eecs.umich.edu req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instAddr); 3412623SN/A} 3422623SN/A 3432623SN/A 3442623SN/Avoid 3452623SN/ABaseSimpleCPU::preExecute() 3462623SN/A{ 3472SN/A // maintain $r0 semantics 3482683Sktlim@umich.edu thread->setIntReg(ZeroReg, 0); 3492427SN/A#if THE_ISA == ALPHA_ISA 3502683Sktlim@umich.edu thread->setFloatReg(ZeroReg, 0.0); 3512427SN/A#endif // ALPHA_ISA 3522SN/A 3532623SN/A // check for instruction-count-based events 3542623SN/A comInstEventQueue[0]->serviceEvents(numInst); 3557897Shestness@cs.utexas.edu system->instEventQueue.serviceEvents(system->totalNumInsts); 3562SN/A 3572623SN/A // decode the instruction 3582623SN/A inst = gtoh(inst); 3594377Sgblack@eecs.umich.edu 3607720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 3614377Sgblack@eecs.umich.edu 3627720Sgblack@eecs.umich.edu if (isRomMicroPC(pcState.microPC())) { 3635665Sgblack@eecs.umich.edu stayAtPC = false; 3647720Sgblack@eecs.umich.edu curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(), 3657720Sgblack@eecs.umich.edu curMacroStaticInst); 3665665Sgblack@eecs.umich.edu } else if (!curMacroStaticInst) { 3675665Sgblack@eecs.umich.edu //We're not in the middle of a macro instruction 3684181Sgblack@eecs.umich.edu StaticInstPtr instPtr = NULL; 3694181Sgblack@eecs.umich.edu 3704181Sgblack@eecs.umich.edu //Predecode, ie bundle up an ExtMachInst 3714182Sgblack@eecs.umich.edu //This should go away once the constructor can be set up properly 3724182Sgblack@eecs.umich.edu predecoder.setTC(thread->getTC()); 3734182Sgblack@eecs.umich.edu //If more fetch data is needed, pass it in. 3747720Sgblack@eecs.umich.edu Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset; 3754593Sgblack@eecs.umich.edu //if(predecoder.needMoreBytes()) 3767720Sgblack@eecs.umich.edu predecoder.moreBytes(pcState, fetchPC, inst); 3774593Sgblack@eecs.umich.edu //else 3784593Sgblack@eecs.umich.edu // predecoder.process(); 3794377Sgblack@eecs.umich.edu 3804377Sgblack@eecs.umich.edu //If an instruction is ready, decode it. Otherwise, we'll have to 3814377Sgblack@eecs.umich.edu //fetch beyond the MachInst at the current pc. 3824377Sgblack@eecs.umich.edu if (predecoder.extMachInstReady()) { 3834377Sgblack@eecs.umich.edu stayAtPC = false; 3847720Sgblack@eecs.umich.edu ExtMachInst machInst = predecoder.getExtMachInst(pcState); 3857720Sgblack@eecs.umich.edu thread->pcState(pcState); 3867720Sgblack@eecs.umich.edu instPtr = StaticInst::decode(machInst, pcState.instAddr()); 3874377Sgblack@eecs.umich.edu } else { 3884377Sgblack@eecs.umich.edu stayAtPC = true; 3894377Sgblack@eecs.umich.edu fetchOffset += sizeof(MachInst); 3904377Sgblack@eecs.umich.edu } 3914181Sgblack@eecs.umich.edu 3924181Sgblack@eecs.umich.edu //If we decoded an instruction and it's microcoded, start pulling 3934181Sgblack@eecs.umich.edu //out micro ops 3944539Sgblack@eecs.umich.edu if (instPtr && instPtr->isMacroop()) { 3953276Sgblack@eecs.umich.edu curMacroStaticInst = instPtr; 3967720Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 3973280Sgblack@eecs.umich.edu } else { 3983280Sgblack@eecs.umich.edu curStaticInst = instPtr; 3993276Sgblack@eecs.umich.edu } 4003276Sgblack@eecs.umich.edu } else { 4013276Sgblack@eecs.umich.edu //Read the next micro op from the macro op 4027720Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 4033276Sgblack@eecs.umich.edu } 4043276Sgblack@eecs.umich.edu 4054181Sgblack@eecs.umich.edu //If we decoded an instruction this "tick", record information about it. 4064181Sgblack@eecs.umich.edu if(curStaticInst) 4074181Sgblack@eecs.umich.edu { 4084522Ssaidi@eecs.umich.edu#if TRACING_ON 4097823Ssteve.reinhardt@amd.com traceData = tracer->getInstRecord(curTick(), tc, 4107720Sgblack@eecs.umich.edu curStaticInst, thread->pcState(), curMacroStaticInst); 4112470SN/A 4124181Sgblack@eecs.umich.edu DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n", 4134181Sgblack@eecs.umich.edu curStaticInst->getName(), curStaticInst->machInst); 4144522Ssaidi@eecs.umich.edu#endif // TRACING_ON 4154181Sgblack@eecs.umich.edu } 4162623SN/A} 4172623SN/A 4182623SN/Avoid 4192623SN/ABaseSimpleCPU::postExecute() 4202623SN/A{ 4217720Sgblack@eecs.umich.edu assert(curStaticInst); 4227720Sgblack@eecs.umich.edu 4237720Sgblack@eecs.umich.edu TheISA::PCState pc = tc->pcState(); 4247720Sgblack@eecs.umich.edu Addr instAddr = pc.instAddr(); 4252623SN/A#if FULL_SYSTEM 4267720Sgblack@eecs.umich.edu if (thread->profile) { 4273577Sgblack@eecs.umich.edu bool usermode = TheISA::inUserMode(tc); 4287720Sgblack@eecs.umich.edu thread->profilePC = usermode ? 1 : instAddr; 4295086Sgblack@eecs.umich.edu ProfileNode *node = thread->profile->consume(tc, curStaticInst); 4302623SN/A if (node) 4312683Sktlim@umich.edu thread->profileNode = node; 4322623SN/A } 4332420SN/A#endif 4342SN/A 4352623SN/A if (curStaticInst->isMemRef()) { 4362623SN/A numMemRefs++; 4372SN/A } 4382SN/A 4392623SN/A if (curStaticInst->isLoad()) { 4402623SN/A ++numLoad; 4412623SN/A comLoadEventQueue[0]->serviceEvents(numLoad); 4422623SN/A } 4432SN/A 4445953Ssaidi@eecs.umich.edu if (CPA::available()) { 4457720Sgblack@eecs.umich.edu CPA::cpa()->swAutoBegin(tc, pc.nextInstAddr()); 4465953Ssaidi@eecs.umich.edu } 4475953Ssaidi@eecs.umich.edu 4487897Shestness@cs.utexas.edu /* Power model statistics */ 4497897Shestness@cs.utexas.edu //integer alu accesses 4507897Shestness@cs.utexas.edu if (curStaticInst->isInteger()){ 4517897Shestness@cs.utexas.edu numIntAluAccesses++; 4527897Shestness@cs.utexas.edu numIntInsts++; 4537897Shestness@cs.utexas.edu } 4547897Shestness@cs.utexas.edu 4557897Shestness@cs.utexas.edu //float alu accesses 4567897Shestness@cs.utexas.edu if (curStaticInst->isFloating()){ 4577897Shestness@cs.utexas.edu numFpAluAccesses++; 4587897Shestness@cs.utexas.edu numFpInsts++; 4597897Shestness@cs.utexas.edu } 4607897Shestness@cs.utexas.edu 4617897Shestness@cs.utexas.edu //number of function calls/returns to get window accesses 4627897Shestness@cs.utexas.edu if (curStaticInst->isCall() || curStaticInst->isReturn()){ 4637897Shestness@cs.utexas.edu numCallsReturns++; 4647897Shestness@cs.utexas.edu } 4657897Shestness@cs.utexas.edu 4667897Shestness@cs.utexas.edu //the number of branch predictions that will be made 4677897Shestness@cs.utexas.edu if (curStaticInst->isCondCtrl()){ 4687897Shestness@cs.utexas.edu numCondCtrlInsts++; 4697897Shestness@cs.utexas.edu } 4707897Shestness@cs.utexas.edu 4717897Shestness@cs.utexas.edu //result bus acceses 4727897Shestness@cs.utexas.edu if (curStaticInst->isLoad()){ 4737897Shestness@cs.utexas.edu numLoadInsts++; 4747897Shestness@cs.utexas.edu } 4757897Shestness@cs.utexas.edu 4767897Shestness@cs.utexas.edu if (curStaticInst->isStore()){ 4777897Shestness@cs.utexas.edu numStoreInsts++; 4787897Shestness@cs.utexas.edu } 4797897Shestness@cs.utexas.edu /* End power model statistics */ 4807897Shestness@cs.utexas.edu 4817720Sgblack@eecs.umich.edu traceFunctions(instAddr); 4822644Sstever@eecs.umich.edu 4832644Sstever@eecs.umich.edu if (traceData) { 4844046Sbinkertn@umich.edu traceData->dump(); 4854046Sbinkertn@umich.edu delete traceData; 4864046Sbinkertn@umich.edu traceData = NULL; 4872644Sstever@eecs.umich.edu } 4882623SN/A} 4892SN/A 4902SN/A 4912623SN/Avoid 4922623SN/ABaseSimpleCPU::advancePC(Fault fault) 4932623SN/A{ 4944377Sgblack@eecs.umich.edu //Since we're moving to a new pc, zero out the offset 4954377Sgblack@eecs.umich.edu fetchOffset = 0; 4962090SN/A if (fault != NoFault) { 4973905Ssaidi@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 4987678Sgblack@eecs.umich.edu fault->invoke(tc, curStaticInst); 4995120Sgblack@eecs.umich.edu predecoder.reset(); 5004377Sgblack@eecs.umich.edu } else { 5017720Sgblack@eecs.umich.edu if (curStaticInst) { 5027720Sgblack@eecs.umich.edu if (curStaticInst->isLastMicroop()) 5037720Sgblack@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 5047720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5057720Sgblack@eecs.umich.edu TheISA::advancePC(pcState, curStaticInst); 5067720Sgblack@eecs.umich.edu thread->pcState(pcState); 5073276Sgblack@eecs.umich.edu } 5082SN/A } 5092SN/A} 5102SN/A 5115250Sksewell@umich.edu/*Fault 5125222Sksewell@umich.eduBaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr) 5135222Sksewell@umich.edu{ 5145222Sksewell@umich.edu // translate to physical address 5155222Sksewell@umich.edu Fault fault = NoFault; 5165222Sksewell@umich.edu int CacheID = Op & 0x3; // Lower 3 bits identify Cache 5175222Sksewell@umich.edu int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation 5185222Sksewell@umich.edu if(CacheID > 1) 5195222Sksewell@umich.edu { 5205222Sksewell@umich.edu warn("CacheOps not implemented for secondary/tertiary caches\n"); 5215222Sksewell@umich.edu } 5225222Sksewell@umich.edu else 5235222Sksewell@umich.edu { 5245222Sksewell@umich.edu switch(CacheOP) 5255222Sksewell@umich.edu { // Fill Packet Type 5265222Sksewell@umich.edu case 0: warn("Invalidate Cache Op\n"); 5275222Sksewell@umich.edu break; 5285222Sksewell@umich.edu case 1: warn("Index Load Tag Cache Op\n"); 5295222Sksewell@umich.edu break; 5305222Sksewell@umich.edu case 2: warn("Index Store Tag Cache Op\n"); 5315222Sksewell@umich.edu break; 5325222Sksewell@umich.edu case 4: warn("Hit Invalidate Cache Op\n"); 5335222Sksewell@umich.edu break; 5345222Sksewell@umich.edu case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n"); 5355222Sksewell@umich.edu break; 5365222Sksewell@umich.edu case 6: warn("Hit Writeback\n"); 5375222Sksewell@umich.edu break; 5385222Sksewell@umich.edu case 7: warn("Fetch & Lock Cache Op\n"); 5395222Sksewell@umich.edu break; 5405222Sksewell@umich.edu default: warn("Unimplemented Cache Op\n"); 5415222Sksewell@umich.edu } 5425222Sksewell@umich.edu } 5435222Sksewell@umich.edu return fault; 5445250Sksewell@umich.edu}*/ 545