base.cc revision 7897
12SN/A/* 27338SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37338SAli.Saidi@ARM.com * All rights reserved 47338SAli.Saidi@ARM.com * 57338SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67338SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77338SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87338SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97338SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107338SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117338SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127338SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137338SAli.Saidi@ARM.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152SN/A * All rights reserved. 162SN/A * 172SN/A * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272SN/A * 282SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412SN/A */ 422SN/A 436216Snate@binkert.org#include "arch/faults.hh" 442439SN/A#include "arch/utility.hh" 456216Snate@binkert.org#include "base/cp_annotate.hh" 46146SN/A#include "base/cprintf.hh" 47146SN/A#include "base/inifile.hh" 48146SN/A#include "base/loader/symtab.hh" 49146SN/A#include "base/misc.hh" 50146SN/A#include "base/pollevent.hh" 51146SN/A#include "base/range.hh" 52146SN/A#include "base/trace.hh" 536216Snate@binkert.org#include "base/types.hh" 546658Snate@binkert.org#include "config/the_isa.hh" 551717SN/A#include "cpu/base.hh" 56146SN/A#include "cpu/exetrace.hh" 571977SN/A#include "cpu/profile.hh" 582623SN/A#include "cpu/simple/base.hh" 592683Sktlim@umich.edu#include "cpu/simple_thread.hh" 601717SN/A#include "cpu/smt.hh" 61146SN/A#include "cpu/static_inst.hh" 622683Sktlim@umich.edu#include "cpu/thread_context.hh" 633348Sbinkertn@umich.edu#include "mem/packet.hh" 646105Ssteve.reinhardt@amd.com#include "mem/request.hh" 656216Snate@binkert.org#include "params/BaseSimpleCPU.hh" 662036SN/A#include "sim/byteswap.hh" 67146SN/A#include "sim/debug.hh" 6856SN/A#include "sim/sim_events.hh" 6956SN/A#include "sim/sim_object.hh" 70695SN/A#include "sim/stats.hh" 712901Ssaidi@eecs.umich.edu#include "sim/system.hh" 722SN/A 731858SN/A#if FULL_SYSTEM 743565Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 753565Sgblack@eecs.umich.edu#include "arch/stacktrace.hh" 762171SN/A#include "arch/tlb.hh" 772170SN/A#include "arch/vtophys.hh" 78146SN/A#else // !FULL_SYSTEM 792462SN/A#include "mem/mem_object.hh" 80146SN/A#endif // FULL_SYSTEM 812SN/A 822SN/Ausing namespace std; 832449SN/Ausing namespace TheISA; 841355SN/A 855529Snate@binkert.orgBaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p) 864495Sacolyte@umich.edu : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL) 87224SN/A{ 881858SN/A#if FULL_SYSTEM 892683Sktlim@umich.edu thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb); 902420SN/A#else 915529Snate@binkert.org thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0], 926331Sgblack@eecs.umich.edu p->itb, p->dtb); 932420SN/A#endif // !FULL_SYSTEM 942SN/A 956029Ssteve.reinhardt@amd.com thread->setStatus(ThreadContext::Halted); 962672Sktlim@umich.edu 972683Sktlim@umich.edu tc = thread->getTC(); 982SN/A 992SN/A numInst = 0; 100334SN/A startNumInst = 0; 101140SN/A numLoad = 0; 102334SN/A startNumLoad = 0; 1032SN/A lastIcacheStall = 0; 1042SN/A lastDcacheStall = 0; 1052SN/A 1062680Sktlim@umich.edu threadContexts.push_back(tc); 1074377Sgblack@eecs.umich.edu 1085169Ssaidi@eecs.umich.edu 1094377Sgblack@eecs.umich.edu fetchOffset = 0; 1104377Sgblack@eecs.umich.edu stayAtPC = false; 1112SN/A} 1122SN/A 1132623SN/ABaseSimpleCPU::~BaseSimpleCPU() 1142SN/A{ 1152SN/A} 1162SN/A 117180SN/Avoid 1182623SN/ABaseSimpleCPU::deallocateContext(int thread_num) 119393SN/A{ 120393SN/A // for now, these are equivalent 121393SN/A suspendContext(thread_num); 122393SN/A} 123384SN/A 124384SN/A 125393SN/Avoid 1262623SN/ABaseSimpleCPU::haltContext(int thread_num) 127393SN/A{ 128393SN/A // for now, these are equivalent 129393SN/A suspendContext(thread_num); 130393SN/A} 131384SN/A 132189SN/A 133189SN/Avoid 1342623SN/ABaseSimpleCPU::regStats() 1352SN/A{ 136729SN/A using namespace Stats; 137334SN/A 1382SN/A BaseCPU::regStats(); 1392SN/A 1402SN/A numInsts 1412SN/A .name(name() + ".num_insts") 1422SN/A .desc("Number of instructions executed") 1432SN/A ; 1442SN/A 1457897Shestness@cs.utexas.edu numIntAluAccesses 1467897Shestness@cs.utexas.edu .name(name() + ".num_int_alu_accesses") 1477897Shestness@cs.utexas.edu .desc("Number of integer alu accesses") 1487897Shestness@cs.utexas.edu ; 1497897Shestness@cs.utexas.edu 1507897Shestness@cs.utexas.edu numFpAluAccesses 1517897Shestness@cs.utexas.edu .name(name() + ".num_fp_alu_accesses") 1527897Shestness@cs.utexas.edu .desc("Number of float alu accesses") 1537897Shestness@cs.utexas.edu ; 1547897Shestness@cs.utexas.edu 1557897Shestness@cs.utexas.edu numCallsReturns 1567897Shestness@cs.utexas.edu .name(name() + ".num_func_calls") 1577897Shestness@cs.utexas.edu .desc("number of times a function call or return occured") 1587897Shestness@cs.utexas.edu ; 1597897Shestness@cs.utexas.edu 1607897Shestness@cs.utexas.edu numCondCtrlInsts 1617897Shestness@cs.utexas.edu .name(name() + ".num_conditional_control_insts") 1627897Shestness@cs.utexas.edu .desc("number of instructions that are conditional controls") 1637897Shestness@cs.utexas.edu ; 1647897Shestness@cs.utexas.edu 1657897Shestness@cs.utexas.edu numIntInsts 1667897Shestness@cs.utexas.edu .name(name() + ".num_int_insts") 1677897Shestness@cs.utexas.edu .desc("number of integer instructions") 1687897Shestness@cs.utexas.edu ; 1697897Shestness@cs.utexas.edu 1707897Shestness@cs.utexas.edu numFpInsts 1717897Shestness@cs.utexas.edu .name(name() + ".num_fp_insts") 1727897Shestness@cs.utexas.edu .desc("number of float instructions") 1737897Shestness@cs.utexas.edu ; 1747897Shestness@cs.utexas.edu 1757897Shestness@cs.utexas.edu numIntRegReads 1767897Shestness@cs.utexas.edu .name(name() + ".num_int_register_reads") 1777897Shestness@cs.utexas.edu .desc("number of times the integer registers were read") 1787897Shestness@cs.utexas.edu ; 1797897Shestness@cs.utexas.edu 1807897Shestness@cs.utexas.edu numIntRegWrites 1817897Shestness@cs.utexas.edu .name(name() + ".num_int_register_writes") 1827897Shestness@cs.utexas.edu .desc("number of times the integer registers were written") 1837897Shestness@cs.utexas.edu ; 1847897Shestness@cs.utexas.edu 1857897Shestness@cs.utexas.edu numFpRegReads 1867897Shestness@cs.utexas.edu .name(name() + ".num_fp_register_reads") 1877897Shestness@cs.utexas.edu .desc("number of times the floating registers were read") 1887897Shestness@cs.utexas.edu ; 1897897Shestness@cs.utexas.edu 1907897Shestness@cs.utexas.edu numFpRegWrites 1917897Shestness@cs.utexas.edu .name(name() + ".num_fp_register_writes") 1927897Shestness@cs.utexas.edu .desc("number of times the floating registers were written") 1937897Shestness@cs.utexas.edu ; 1947897Shestness@cs.utexas.edu 1952SN/A numMemRefs 1967897Shestness@cs.utexas.edu .name(name()+".num_mem_refs") 1977897Shestness@cs.utexas.edu .desc("number of memory refs") 1987897Shestness@cs.utexas.edu ; 1997897Shestness@cs.utexas.edu 2007897Shestness@cs.utexas.edu numStoreInsts 2017897Shestness@cs.utexas.edu .name(name() + ".num_store_insts") 2027897Shestness@cs.utexas.edu .desc("Number of store instructions") 2037897Shestness@cs.utexas.edu ; 2047897Shestness@cs.utexas.edu 2057897Shestness@cs.utexas.edu numLoadInsts 2067897Shestness@cs.utexas.edu .name(name() + ".num_load_insts") 2077897Shestness@cs.utexas.edu .desc("Number of load instructions") 2082SN/A ; 2092SN/A 2101001SN/A notIdleFraction 2111001SN/A .name(name() + ".not_idle_fraction") 2121001SN/A .desc("Percentage of non-idle cycles") 2131001SN/A ; 2141001SN/A 2152SN/A idleFraction 2162SN/A .name(name() + ".idle_fraction") 2172SN/A .desc("Percentage of idle cycles") 2182SN/A ; 2192SN/A 2207897Shestness@cs.utexas.edu numBusyCycles 2217897Shestness@cs.utexas.edu .name(name() + ".num_busy_cycles") 2227897Shestness@cs.utexas.edu .desc("Number of busy cycles") 2237897Shestness@cs.utexas.edu ; 2247897Shestness@cs.utexas.edu 2257897Shestness@cs.utexas.edu numIdleCycles 2267897Shestness@cs.utexas.edu .name(name()+".num_idle_cycles") 2277897Shestness@cs.utexas.edu .desc("Number of idle cycles") 2287897Shestness@cs.utexas.edu ; 2297897Shestness@cs.utexas.edu 2302SN/A icacheStallCycles 2312SN/A .name(name() + ".icache_stall_cycles") 2322SN/A .desc("ICache total stall cycles") 2332SN/A .prereq(icacheStallCycles) 2342SN/A ; 2352SN/A 2362SN/A dcacheStallCycles 2372SN/A .name(name() + ".dcache_stall_cycles") 2382SN/A .desc("DCache total stall cycles") 2392SN/A .prereq(dcacheStallCycles) 2402SN/A ; 2412SN/A 2422390SN/A icacheRetryCycles 2432390SN/A .name(name() + ".icache_retry_cycles") 2442390SN/A .desc("ICache total retry cycles") 2452390SN/A .prereq(icacheRetryCycles) 2462390SN/A ; 2472390SN/A 2482390SN/A dcacheRetryCycles 2492390SN/A .name(name() + ".dcache_retry_cycles") 2502390SN/A .desc("DCache total retry cycles") 2512390SN/A .prereq(dcacheRetryCycles) 2522390SN/A ; 2532390SN/A 254385SN/A idleFraction = constant(1.0) - notIdleFraction; 2557897Shestness@cs.utexas.edu numIdleCycles = idleFraction * numCycles; 2567897Shestness@cs.utexas.edu numBusyCycles = (notIdleFraction)*numCycles; 2572SN/A} 2582SN/A 2592SN/Avoid 2602623SN/ABaseSimpleCPU::resetStats() 261334SN/A{ 2622361SN/A// startNumInst = numInst; 2635496Ssaidi@eecs.umich.edu notIdleFraction = (_status != Idle); 264334SN/A} 265334SN/A 266334SN/Avoid 2672623SN/ABaseSimpleCPU::serialize(ostream &os) 2682SN/A{ 2695496Ssaidi@eecs.umich.edu SERIALIZE_ENUM(_status); 270921SN/A BaseCPU::serialize(os); 2712915Sktlim@umich.edu// SERIALIZE_SCALAR(inst); 2722915Sktlim@umich.edu nameOut(os, csprintf("%s.xc.0", name())); 2732683Sktlim@umich.edu thread->serialize(os); 2742SN/A} 2752SN/A 2762SN/Avoid 2772623SN/ABaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 2782SN/A{ 2795496Ssaidi@eecs.umich.edu UNSERIALIZE_ENUM(_status); 280921SN/A BaseCPU::unserialize(cp, section); 2812915Sktlim@umich.edu// UNSERIALIZE_SCALAR(inst); 2822915Sktlim@umich.edu thread->unserialize(cp, csprintf("%s.xc.0", section)); 2832SN/A} 2842SN/A 2852SN/Avoid 2866221Snate@binkert.orgchange_thread_state(ThreadID tid, int activate, int priority) 2872SN/A{ 2882SN/A} 2892SN/A 2901858SN/A#if FULL_SYSTEM 2912SN/AAddr 2922623SN/ABaseSimpleCPU::dbg_vtophys(Addr addr) 2932SN/A{ 2942680Sktlim@umich.edu return vtophys(tc, addr); 2952SN/A} 2962SN/A#endif // FULL_SYSTEM 2972SN/A 2981858SN/A#if FULL_SYSTEM 2992SN/Avoid 3005807Snate@binkert.orgBaseSimpleCPU::wakeup() 3012SN/A{ 3025807Snate@binkert.org if (thread->status() != ThreadContext::Suspended) 3035807Snate@binkert.org return; 3042SN/A 3055807Snate@binkert.org DPRINTF(Quiesce,"Suspended Processor awoke\n"); 3065807Snate@binkert.org thread->activate(); 3072SN/A} 3082SN/A#endif // FULL_SYSTEM 3092SN/A 3102SN/Avoid 3112623SN/ABaseSimpleCPU::checkForInterrupts() 3122SN/A{ 3131858SN/A#if FULL_SYSTEM 3145704Snate@binkert.org if (checkInterrupts(tc)) { 3155647Sgblack@eecs.umich.edu Fault interrupt = interrupts->getInterrupt(tc); 3162SN/A 3173520Sgblack@eecs.umich.edu if (interrupt != NoFault) { 3187338SAli.Saidi@ARM.com fetchOffset = 0; 3195647Sgblack@eecs.umich.edu interrupts->updateIntrInfo(tc); 3203520Sgblack@eecs.umich.edu interrupt->invoke(tc); 3217408Sgblack@eecs.umich.edu predecoder.reset(); 3222SN/A } 3232SN/A } 3242SN/A#endif 3252623SN/A} 3262SN/A 3272623SN/A 3285894Sgblack@eecs.umich.eduvoid 3292662Sstever@eecs.umich.eduBaseSimpleCPU::setupFetchRequest(Request *req) 3302623SN/A{ 3317720Sgblack@eecs.umich.edu Addr instAddr = thread->instAddr(); 3324495Sacolyte@umich.edu 3332623SN/A // set up memory request for instruction fetch 3347720Sgblack@eecs.umich.edu DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr); 3352623SN/A 3367720Sgblack@eecs.umich.edu Addr fetchPC = (instAddr & PCMask) + fetchOffset; 3377720Sgblack@eecs.umich.edu req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instAddr); 3382623SN/A} 3392623SN/A 3402623SN/A 3412623SN/Avoid 3422623SN/ABaseSimpleCPU::preExecute() 3432623SN/A{ 3442SN/A // maintain $r0 semantics 3452683Sktlim@umich.edu thread->setIntReg(ZeroReg, 0); 3462427SN/A#if THE_ISA == ALPHA_ISA 3472683Sktlim@umich.edu thread->setFloatReg(ZeroReg, 0.0); 3482427SN/A#endif // ALPHA_ISA 3492SN/A 3502623SN/A // check for instruction-count-based events 3512623SN/A comInstEventQueue[0]->serviceEvents(numInst); 3527897Shestness@cs.utexas.edu system->instEventQueue.serviceEvents(system->totalNumInsts); 3532SN/A 3542623SN/A // decode the instruction 3552623SN/A inst = gtoh(inst); 3564377Sgblack@eecs.umich.edu 3577720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 3584377Sgblack@eecs.umich.edu 3597720Sgblack@eecs.umich.edu if (isRomMicroPC(pcState.microPC())) { 3605665Sgblack@eecs.umich.edu stayAtPC = false; 3617720Sgblack@eecs.umich.edu curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(), 3627720Sgblack@eecs.umich.edu curMacroStaticInst); 3635665Sgblack@eecs.umich.edu } else if (!curMacroStaticInst) { 3645665Sgblack@eecs.umich.edu //We're not in the middle of a macro instruction 3654181Sgblack@eecs.umich.edu StaticInstPtr instPtr = NULL; 3664181Sgblack@eecs.umich.edu 3674181Sgblack@eecs.umich.edu //Predecode, ie bundle up an ExtMachInst 3684182Sgblack@eecs.umich.edu //This should go away once the constructor can be set up properly 3694182Sgblack@eecs.umich.edu predecoder.setTC(thread->getTC()); 3704182Sgblack@eecs.umich.edu //If more fetch data is needed, pass it in. 3717720Sgblack@eecs.umich.edu Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset; 3724593Sgblack@eecs.umich.edu //if(predecoder.needMoreBytes()) 3737720Sgblack@eecs.umich.edu predecoder.moreBytes(pcState, fetchPC, inst); 3744593Sgblack@eecs.umich.edu //else 3754593Sgblack@eecs.umich.edu // predecoder.process(); 3764377Sgblack@eecs.umich.edu 3774377Sgblack@eecs.umich.edu //If an instruction is ready, decode it. Otherwise, we'll have to 3784377Sgblack@eecs.umich.edu //fetch beyond the MachInst at the current pc. 3794377Sgblack@eecs.umich.edu if (predecoder.extMachInstReady()) { 3804377Sgblack@eecs.umich.edu stayAtPC = false; 3817720Sgblack@eecs.umich.edu ExtMachInst machInst = predecoder.getExtMachInst(pcState); 3827720Sgblack@eecs.umich.edu thread->pcState(pcState); 3837720Sgblack@eecs.umich.edu instPtr = StaticInst::decode(machInst, pcState.instAddr()); 3844377Sgblack@eecs.umich.edu } else { 3854377Sgblack@eecs.umich.edu stayAtPC = true; 3864377Sgblack@eecs.umich.edu fetchOffset += sizeof(MachInst); 3874377Sgblack@eecs.umich.edu } 3884181Sgblack@eecs.umich.edu 3894181Sgblack@eecs.umich.edu //If we decoded an instruction and it's microcoded, start pulling 3904181Sgblack@eecs.umich.edu //out micro ops 3914539Sgblack@eecs.umich.edu if (instPtr && instPtr->isMacroop()) { 3923276Sgblack@eecs.umich.edu curMacroStaticInst = instPtr; 3937720Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 3943280Sgblack@eecs.umich.edu } else { 3953280Sgblack@eecs.umich.edu curStaticInst = instPtr; 3963276Sgblack@eecs.umich.edu } 3973276Sgblack@eecs.umich.edu } else { 3983276Sgblack@eecs.umich.edu //Read the next micro op from the macro op 3997720Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 4003276Sgblack@eecs.umich.edu } 4013276Sgblack@eecs.umich.edu 4024181Sgblack@eecs.umich.edu //If we decoded an instruction this "tick", record information about it. 4034181Sgblack@eecs.umich.edu if(curStaticInst) 4044181Sgblack@eecs.umich.edu { 4054522Ssaidi@eecs.umich.edu#if TRACING_ON 4067823Ssteve.reinhardt@amd.com traceData = tracer->getInstRecord(curTick(), tc, 4077720Sgblack@eecs.umich.edu curStaticInst, thread->pcState(), curMacroStaticInst); 4082470SN/A 4094181Sgblack@eecs.umich.edu DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n", 4104181Sgblack@eecs.umich.edu curStaticInst->getName(), curStaticInst->machInst); 4114522Ssaidi@eecs.umich.edu#endif // TRACING_ON 4124181Sgblack@eecs.umich.edu } 4132623SN/A} 4142623SN/A 4152623SN/Avoid 4162623SN/ABaseSimpleCPU::postExecute() 4172623SN/A{ 4187720Sgblack@eecs.umich.edu assert(curStaticInst); 4197720Sgblack@eecs.umich.edu 4207720Sgblack@eecs.umich.edu TheISA::PCState pc = tc->pcState(); 4217720Sgblack@eecs.umich.edu Addr instAddr = pc.instAddr(); 4222623SN/A#if FULL_SYSTEM 4237720Sgblack@eecs.umich.edu if (thread->profile) { 4243577Sgblack@eecs.umich.edu bool usermode = TheISA::inUserMode(tc); 4257720Sgblack@eecs.umich.edu thread->profilePC = usermode ? 1 : instAddr; 4265086Sgblack@eecs.umich.edu ProfileNode *node = thread->profile->consume(tc, curStaticInst); 4272623SN/A if (node) 4282683Sktlim@umich.edu thread->profileNode = node; 4292623SN/A } 4302420SN/A#endif 4312SN/A 4322623SN/A if (curStaticInst->isMemRef()) { 4332623SN/A numMemRefs++; 4342SN/A } 4352SN/A 4362623SN/A if (curStaticInst->isLoad()) { 4372623SN/A ++numLoad; 4382623SN/A comLoadEventQueue[0]->serviceEvents(numLoad); 4392623SN/A } 4402SN/A 4415953Ssaidi@eecs.umich.edu if (CPA::available()) { 4427720Sgblack@eecs.umich.edu CPA::cpa()->swAutoBegin(tc, pc.nextInstAddr()); 4435953Ssaidi@eecs.umich.edu } 4445953Ssaidi@eecs.umich.edu 4457897Shestness@cs.utexas.edu /* Power model statistics */ 4467897Shestness@cs.utexas.edu //integer alu accesses 4477897Shestness@cs.utexas.edu if (curStaticInst->isInteger()){ 4487897Shestness@cs.utexas.edu numIntAluAccesses++; 4497897Shestness@cs.utexas.edu numIntInsts++; 4507897Shestness@cs.utexas.edu } 4517897Shestness@cs.utexas.edu 4527897Shestness@cs.utexas.edu //float alu accesses 4537897Shestness@cs.utexas.edu if (curStaticInst->isFloating()){ 4547897Shestness@cs.utexas.edu numFpAluAccesses++; 4557897Shestness@cs.utexas.edu numFpInsts++; 4567897Shestness@cs.utexas.edu } 4577897Shestness@cs.utexas.edu 4587897Shestness@cs.utexas.edu //number of function calls/returns to get window accesses 4597897Shestness@cs.utexas.edu if (curStaticInst->isCall() || curStaticInst->isReturn()){ 4607897Shestness@cs.utexas.edu numCallsReturns++; 4617897Shestness@cs.utexas.edu } 4627897Shestness@cs.utexas.edu 4637897Shestness@cs.utexas.edu //the number of branch predictions that will be made 4647897Shestness@cs.utexas.edu if (curStaticInst->isCondCtrl()){ 4657897Shestness@cs.utexas.edu numCondCtrlInsts++; 4667897Shestness@cs.utexas.edu } 4677897Shestness@cs.utexas.edu 4687897Shestness@cs.utexas.edu //result bus acceses 4697897Shestness@cs.utexas.edu if (curStaticInst->isLoad()){ 4707897Shestness@cs.utexas.edu numLoadInsts++; 4717897Shestness@cs.utexas.edu } 4727897Shestness@cs.utexas.edu 4737897Shestness@cs.utexas.edu if (curStaticInst->isStore()){ 4747897Shestness@cs.utexas.edu numStoreInsts++; 4757897Shestness@cs.utexas.edu } 4767897Shestness@cs.utexas.edu /* End power model statistics */ 4777897Shestness@cs.utexas.edu 4787720Sgblack@eecs.umich.edu traceFunctions(instAddr); 4792644Sstever@eecs.umich.edu 4802644Sstever@eecs.umich.edu if (traceData) { 4814046Sbinkertn@umich.edu traceData->dump(); 4824046Sbinkertn@umich.edu delete traceData; 4834046Sbinkertn@umich.edu traceData = NULL; 4842644Sstever@eecs.umich.edu } 4852623SN/A} 4862SN/A 4872SN/A 4882623SN/Avoid 4892623SN/ABaseSimpleCPU::advancePC(Fault fault) 4902623SN/A{ 4914377Sgblack@eecs.umich.edu //Since we're moving to a new pc, zero out the offset 4924377Sgblack@eecs.umich.edu fetchOffset = 0; 4932090SN/A if (fault != NoFault) { 4943905Ssaidi@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 4957678Sgblack@eecs.umich.edu fault->invoke(tc, curStaticInst); 4965120Sgblack@eecs.umich.edu predecoder.reset(); 4974377Sgblack@eecs.umich.edu } else { 4987720Sgblack@eecs.umich.edu if (curStaticInst) { 4997720Sgblack@eecs.umich.edu if (curStaticInst->isLastMicroop()) 5007720Sgblack@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 5017720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5027720Sgblack@eecs.umich.edu TheISA::advancePC(pcState, curStaticInst); 5037720Sgblack@eecs.umich.edu thread->pcState(pcState); 5043276Sgblack@eecs.umich.edu } 5052SN/A } 5062SN/A} 5072SN/A 5085250Sksewell@umich.edu/*Fault 5095222Sksewell@umich.eduBaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr) 5105222Sksewell@umich.edu{ 5115222Sksewell@umich.edu // translate to physical address 5125222Sksewell@umich.edu Fault fault = NoFault; 5135222Sksewell@umich.edu int CacheID = Op & 0x3; // Lower 3 bits identify Cache 5145222Sksewell@umich.edu int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation 5155222Sksewell@umich.edu if(CacheID > 1) 5165222Sksewell@umich.edu { 5175222Sksewell@umich.edu warn("CacheOps not implemented for secondary/tertiary caches\n"); 5185222Sksewell@umich.edu } 5195222Sksewell@umich.edu else 5205222Sksewell@umich.edu { 5215222Sksewell@umich.edu switch(CacheOP) 5225222Sksewell@umich.edu { // Fill Packet Type 5235222Sksewell@umich.edu case 0: warn("Invalidate Cache Op\n"); 5245222Sksewell@umich.edu break; 5255222Sksewell@umich.edu case 1: warn("Index Load Tag Cache Op\n"); 5265222Sksewell@umich.edu break; 5275222Sksewell@umich.edu case 2: warn("Index Store Tag Cache Op\n"); 5285222Sksewell@umich.edu break; 5295222Sksewell@umich.edu case 4: warn("Hit Invalidate Cache Op\n"); 5305222Sksewell@umich.edu break; 5315222Sksewell@umich.edu case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n"); 5325222Sksewell@umich.edu break; 5335222Sksewell@umich.edu case 6: warn("Hit Writeback\n"); 5345222Sksewell@umich.edu break; 5355222Sksewell@umich.edu case 7: warn("Fetch & Lock Cache Op\n"); 5365222Sksewell@umich.edu break; 5375222Sksewell@umich.edu default: warn("Unimplemented Cache Op\n"); 5385222Sksewell@umich.edu } 5395222Sksewell@umich.edu } 5405222Sksewell@umich.edu return fault; 5415250Sksewell@umich.edu}*/ 542