base.cc revision 7720
12SN/A/* 27338SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37338SAli.Saidi@ARM.com * All rights reserved 47338SAli.Saidi@ARM.com * 57338SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67338SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77338SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87338SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97338SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107338SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117338SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127338SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137338SAli.Saidi@ARM.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152SN/A * All rights reserved. 162SN/A * 172SN/A * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272SN/A * 282SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412SN/A */ 422SN/A 436216Snate@binkert.org#include "arch/faults.hh" 442439SN/A#include "arch/utility.hh" 456216Snate@binkert.org#include "base/cp_annotate.hh" 46146SN/A#include "base/cprintf.hh" 47146SN/A#include "base/inifile.hh" 48146SN/A#include "base/loader/symtab.hh" 49146SN/A#include "base/misc.hh" 50146SN/A#include "base/pollevent.hh" 51146SN/A#include "base/range.hh" 52146SN/A#include "base/trace.hh" 536216Snate@binkert.org#include "base/types.hh" 546658Snate@binkert.org#include "config/the_isa.hh" 551717SN/A#include "cpu/base.hh" 56146SN/A#include "cpu/exetrace.hh" 571977SN/A#include "cpu/profile.hh" 582623SN/A#include "cpu/simple/base.hh" 592683Sktlim@umich.edu#include "cpu/simple_thread.hh" 601717SN/A#include "cpu/smt.hh" 61146SN/A#include "cpu/static_inst.hh" 622683Sktlim@umich.edu#include "cpu/thread_context.hh" 633348Sbinkertn@umich.edu#include "mem/packet.hh" 646105Ssteve.reinhardt@amd.com#include "mem/request.hh" 656216Snate@binkert.org#include "params/BaseSimpleCPU.hh" 662036SN/A#include "sim/byteswap.hh" 67146SN/A#include "sim/debug.hh" 6856SN/A#include "sim/sim_events.hh" 6956SN/A#include "sim/sim_object.hh" 70695SN/A#include "sim/stats.hh" 712901Ssaidi@eecs.umich.edu#include "sim/system.hh" 722SN/A 731858SN/A#if FULL_SYSTEM 743565Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 753565Sgblack@eecs.umich.edu#include "arch/stacktrace.hh" 762171SN/A#include "arch/tlb.hh" 772170SN/A#include "arch/vtophys.hh" 78146SN/A#else // !FULL_SYSTEM 792462SN/A#include "mem/mem_object.hh" 80146SN/A#endif // FULL_SYSTEM 812SN/A 822SN/Ausing namespace std; 832449SN/Ausing namespace TheISA; 841355SN/A 855529Snate@binkert.orgBaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p) 864495Sacolyte@umich.edu : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL) 87224SN/A{ 881858SN/A#if FULL_SYSTEM 892683Sktlim@umich.edu thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb); 902420SN/A#else 915529Snate@binkert.org thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0], 926331Sgblack@eecs.umich.edu p->itb, p->dtb); 932420SN/A#endif // !FULL_SYSTEM 942SN/A 956029Ssteve.reinhardt@amd.com thread->setStatus(ThreadContext::Halted); 962672Sktlim@umich.edu 972683Sktlim@umich.edu tc = thread->getTC(); 982SN/A 992SN/A numInst = 0; 100334SN/A startNumInst = 0; 101140SN/A numLoad = 0; 102334SN/A startNumLoad = 0; 1032SN/A lastIcacheStall = 0; 1042SN/A lastDcacheStall = 0; 1052SN/A 1062680Sktlim@umich.edu threadContexts.push_back(tc); 1074377Sgblack@eecs.umich.edu 1085169Ssaidi@eecs.umich.edu 1094377Sgblack@eecs.umich.edu fetchOffset = 0; 1104377Sgblack@eecs.umich.edu stayAtPC = false; 1112SN/A} 1122SN/A 1132623SN/ABaseSimpleCPU::~BaseSimpleCPU() 1142SN/A{ 1152SN/A} 1162SN/A 117180SN/Avoid 1182623SN/ABaseSimpleCPU::deallocateContext(int thread_num) 119393SN/A{ 120393SN/A // for now, these are equivalent 121393SN/A suspendContext(thread_num); 122393SN/A} 123384SN/A 124384SN/A 125393SN/Avoid 1262623SN/ABaseSimpleCPU::haltContext(int thread_num) 127393SN/A{ 128393SN/A // for now, these are equivalent 129393SN/A suspendContext(thread_num); 130393SN/A} 131384SN/A 132189SN/A 133189SN/Avoid 1342623SN/ABaseSimpleCPU::regStats() 1352SN/A{ 136729SN/A using namespace Stats; 137334SN/A 1382SN/A BaseCPU::regStats(); 1392SN/A 1402SN/A numInsts 1412SN/A .name(name() + ".num_insts") 1422SN/A .desc("Number of instructions executed") 1432SN/A ; 1442SN/A 1452SN/A numMemRefs 1462SN/A .name(name() + ".num_refs") 1472SN/A .desc("Number of memory references") 1482SN/A ; 1492SN/A 1501001SN/A notIdleFraction 1511001SN/A .name(name() + ".not_idle_fraction") 1521001SN/A .desc("Percentage of non-idle cycles") 1531001SN/A ; 1541001SN/A 1552SN/A idleFraction 1562SN/A .name(name() + ".idle_fraction") 1572SN/A .desc("Percentage of idle cycles") 1582SN/A ; 1592SN/A 1602SN/A icacheStallCycles 1612SN/A .name(name() + ".icache_stall_cycles") 1622SN/A .desc("ICache total stall cycles") 1632SN/A .prereq(icacheStallCycles) 1642SN/A ; 1652SN/A 1662SN/A dcacheStallCycles 1672SN/A .name(name() + ".dcache_stall_cycles") 1682SN/A .desc("DCache total stall cycles") 1692SN/A .prereq(dcacheStallCycles) 1702SN/A ; 1712SN/A 1722390SN/A icacheRetryCycles 1732390SN/A .name(name() + ".icache_retry_cycles") 1742390SN/A .desc("ICache total retry cycles") 1752390SN/A .prereq(icacheRetryCycles) 1762390SN/A ; 1772390SN/A 1782390SN/A dcacheRetryCycles 1792390SN/A .name(name() + ".dcache_retry_cycles") 1802390SN/A .desc("DCache total retry cycles") 1812390SN/A .prereq(dcacheRetryCycles) 1822390SN/A ; 1832390SN/A 184385SN/A idleFraction = constant(1.0) - notIdleFraction; 1852SN/A} 1862SN/A 1872SN/Avoid 1882623SN/ABaseSimpleCPU::resetStats() 189334SN/A{ 1902361SN/A// startNumInst = numInst; 1915496Ssaidi@eecs.umich.edu notIdleFraction = (_status != Idle); 192334SN/A} 193334SN/A 194334SN/Avoid 1952623SN/ABaseSimpleCPU::serialize(ostream &os) 1962SN/A{ 1975496Ssaidi@eecs.umich.edu SERIALIZE_ENUM(_status); 198921SN/A BaseCPU::serialize(os); 1992915Sktlim@umich.edu// SERIALIZE_SCALAR(inst); 2002915Sktlim@umich.edu nameOut(os, csprintf("%s.xc.0", name())); 2012683Sktlim@umich.edu thread->serialize(os); 2022SN/A} 2032SN/A 2042SN/Avoid 2052623SN/ABaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 2062SN/A{ 2075496Ssaidi@eecs.umich.edu UNSERIALIZE_ENUM(_status); 208921SN/A BaseCPU::unserialize(cp, section); 2092915Sktlim@umich.edu// UNSERIALIZE_SCALAR(inst); 2102915Sktlim@umich.edu thread->unserialize(cp, csprintf("%s.xc.0", section)); 2112SN/A} 2122SN/A 2132SN/Avoid 2146221Snate@binkert.orgchange_thread_state(ThreadID tid, int activate, int priority) 2152SN/A{ 2162SN/A} 2172SN/A 2187045Ssteve.reinhardt@amd.comvoid 2197045Ssteve.reinhardt@amd.comBaseSimpleCPU::prefetch(Addr addr, unsigned flags) 2207045Ssteve.reinhardt@amd.com{ 2217045Ssteve.reinhardt@amd.com if (traceData) { 2227045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 2237045Ssteve.reinhardt@amd.com } 2247045Ssteve.reinhardt@amd.com 2257045Ssteve.reinhardt@amd.com // need to do this... 2267045Ssteve.reinhardt@amd.com} 2277045Ssteve.reinhardt@amd.com 2287045Ssteve.reinhardt@amd.comvoid 2297045Ssteve.reinhardt@amd.comBaseSimpleCPU::writeHint(Addr addr, int size, unsigned flags) 2307045Ssteve.reinhardt@amd.com{ 2317045Ssteve.reinhardt@amd.com if (traceData) { 2327045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 2337045Ssteve.reinhardt@amd.com } 2347045Ssteve.reinhardt@amd.com 2357045Ssteve.reinhardt@amd.com // need to do this... 2367045Ssteve.reinhardt@amd.com} 2377045Ssteve.reinhardt@amd.com 2387045Ssteve.reinhardt@amd.com 239595SN/AFault 2402623SN/ABaseSimpleCPU::copySrcTranslate(Addr src) 241595SN/A{ 2422390SN/A#if 0 2431080SN/A static bool no_warn = true; 2446227Snate@binkert.org unsigned blk_size = 2456227Snate@binkert.org (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 2461080SN/A // Only support block sizes of 64 atm. 2471080SN/A assert(blk_size == 64); 2481080SN/A int offset = src & (blk_size - 1); 2491080SN/A 2501080SN/A // Make sure block doesn't span page 2511121SN/A if (no_warn && 2522107SN/A (src & PageMask) != ((src + blk_size) & PageMask) && 2531089SN/A (src >> 40) != 0xfffffc) { 2541089SN/A warn("Copied block source spans pages %x.", src); 2551080SN/A no_warn = false; 2561080SN/A } 2571080SN/A 2581080SN/A memReq->reset(src & ~(blk_size - 1), blk_size); 259595SN/A 2602623SN/A // translate to physical address 2612683Sktlim@umich.edu Fault fault = thread->translateDataReadReq(req); 262595SN/A 2632090SN/A if (fault == NoFault) { 2642683Sktlim@umich.edu thread->copySrcAddr = src; 2652683Sktlim@umich.edu thread->copySrcPhysAddr = memReq->paddr + offset; 266595SN/A } else { 2672205SN/A assert(!fault->isAlignmentFault()); 2682205SN/A 2692683Sktlim@umich.edu thread->copySrcAddr = 0; 2702683Sktlim@umich.edu thread->copySrcPhysAddr = 0; 271595SN/A } 272595SN/A return fault; 2732390SN/A#else 2742423SN/A return NoFault; 2752390SN/A#endif 276595SN/A} 277595SN/A 278595SN/AFault 2792623SN/ABaseSimpleCPU::copy(Addr dest) 280595SN/A{ 2812390SN/A#if 0 2821080SN/A static bool no_warn = true; 2836227Snate@binkert.org unsigned blk_size = 2846227Snate@binkert.org (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 2851080SN/A // Only support block sizes of 64 atm. 2861080SN/A assert(blk_size == 64); 287595SN/A uint8_t data[blk_size]; 2882683Sktlim@umich.edu //assert(thread->copySrcAddr); 2891080SN/A int offset = dest & (blk_size - 1); 2901080SN/A 2911080SN/A // Make sure block doesn't span page 2921121SN/A if (no_warn && 2932107SN/A (dest & PageMask) != ((dest + blk_size) & PageMask) && 2941089SN/A (dest >> 40) != 0xfffffc) { 2951080SN/A no_warn = false; 2961089SN/A warn("Copied block destination spans pages %x. ", dest); 2971080SN/A } 2981080SN/A 2991080SN/A memReq->reset(dest & ~(blk_size -1), blk_size); 300595SN/A // translate to physical address 3012683Sktlim@umich.edu Fault fault = thread->translateDataWriteReq(req); 3021080SN/A 3032090SN/A if (fault == NoFault) { 3041080SN/A Addr dest_addr = memReq->paddr + offset; 305595SN/A // Need to read straight from memory since we have more than 8 bytes. 3062683Sktlim@umich.edu memReq->paddr = thread->copySrcPhysAddr; 3072683Sktlim@umich.edu thread->mem->read(memReq, data); 308595SN/A memReq->paddr = dest_addr; 3092683Sktlim@umich.edu thread->mem->write(memReq, data); 3101098SN/A if (dcacheInterface) { 3111098SN/A memReq->cmd = Copy; 3121098SN/A memReq->completionEvent = NULL; 3132683Sktlim@umich.edu memReq->paddr = thread->copySrcPhysAddr; 3141098SN/A memReq->dest = dest_addr; 3151098SN/A memReq->size = 64; 3161098SN/A memReq->time = curTick; 3171098SN/A dcacheInterface->access(memReq); 3181098SN/A } 319595SN/A } 3202205SN/A else 3212205SN/A assert(!fault->isAlignmentFault()); 3222205SN/A 323595SN/A return fault; 3242390SN/A#else 3252420SN/A panic("copy not implemented"); 3262423SN/A return NoFault; 3272390SN/A#endif 328595SN/A} 329595SN/A 3301858SN/A#if FULL_SYSTEM 3312SN/AAddr 3322623SN/ABaseSimpleCPU::dbg_vtophys(Addr addr) 3332SN/A{ 3342680Sktlim@umich.edu return vtophys(tc, addr); 3352SN/A} 3362SN/A#endif // FULL_SYSTEM 3372SN/A 3381858SN/A#if FULL_SYSTEM 3392SN/Avoid 3405807Snate@binkert.orgBaseSimpleCPU::wakeup() 3412SN/A{ 3425807Snate@binkert.org if (thread->status() != ThreadContext::Suspended) 3435807Snate@binkert.org return; 3442SN/A 3455807Snate@binkert.org DPRINTF(Quiesce,"Suspended Processor awoke\n"); 3465807Snate@binkert.org thread->activate(); 3472SN/A} 3482SN/A#endif // FULL_SYSTEM 3492SN/A 3502SN/Avoid 3512623SN/ABaseSimpleCPU::checkForInterrupts() 3522SN/A{ 3531858SN/A#if FULL_SYSTEM 3545704Snate@binkert.org if (checkInterrupts(tc)) { 3555647Sgblack@eecs.umich.edu Fault interrupt = interrupts->getInterrupt(tc); 3562SN/A 3573520Sgblack@eecs.umich.edu if (interrupt != NoFault) { 3587338SAli.Saidi@ARM.com fetchOffset = 0; 3595647Sgblack@eecs.umich.edu interrupts->updateIntrInfo(tc); 3603520Sgblack@eecs.umich.edu interrupt->invoke(tc); 3617408Sgblack@eecs.umich.edu predecoder.reset(); 3622SN/A } 3632SN/A } 3642SN/A#endif 3652623SN/A} 3662SN/A 3672623SN/A 3685894Sgblack@eecs.umich.eduvoid 3692662Sstever@eecs.umich.eduBaseSimpleCPU::setupFetchRequest(Request *req) 3702623SN/A{ 3717720Sgblack@eecs.umich.edu Addr instAddr = thread->instAddr(); 3724495Sacolyte@umich.edu 3732623SN/A // set up memory request for instruction fetch 3747720Sgblack@eecs.umich.edu DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr); 3752623SN/A 3767720Sgblack@eecs.umich.edu Addr fetchPC = (instAddr & PCMask) + fetchOffset; 3777720Sgblack@eecs.umich.edu req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instAddr); 3782623SN/A} 3792623SN/A 3802623SN/A 3812623SN/Avoid 3822623SN/ABaseSimpleCPU::preExecute() 3832623SN/A{ 3842SN/A // maintain $r0 semantics 3852683Sktlim@umich.edu thread->setIntReg(ZeroReg, 0); 3862427SN/A#if THE_ISA == ALPHA_ISA 3872683Sktlim@umich.edu thread->setFloatReg(ZeroReg, 0.0); 3882427SN/A#endif // ALPHA_ISA 3892SN/A 3902623SN/A // check for instruction-count-based events 3912623SN/A comInstEventQueue[0]->serviceEvents(numInst); 3922SN/A 3932623SN/A // decode the instruction 3942623SN/A inst = gtoh(inst); 3954377Sgblack@eecs.umich.edu 3967720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 3974377Sgblack@eecs.umich.edu 3987720Sgblack@eecs.umich.edu if (isRomMicroPC(pcState.microPC())) { 3995665Sgblack@eecs.umich.edu stayAtPC = false; 4007720Sgblack@eecs.umich.edu curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(), 4017720Sgblack@eecs.umich.edu curMacroStaticInst); 4025665Sgblack@eecs.umich.edu } else if (!curMacroStaticInst) { 4035665Sgblack@eecs.umich.edu //We're not in the middle of a macro instruction 4044181Sgblack@eecs.umich.edu StaticInstPtr instPtr = NULL; 4054181Sgblack@eecs.umich.edu 4064181Sgblack@eecs.umich.edu //Predecode, ie bundle up an ExtMachInst 4074182Sgblack@eecs.umich.edu //This should go away once the constructor can be set up properly 4084182Sgblack@eecs.umich.edu predecoder.setTC(thread->getTC()); 4094182Sgblack@eecs.umich.edu //If more fetch data is needed, pass it in. 4107720Sgblack@eecs.umich.edu Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset; 4114593Sgblack@eecs.umich.edu //if(predecoder.needMoreBytes()) 4127720Sgblack@eecs.umich.edu predecoder.moreBytes(pcState, fetchPC, inst); 4134593Sgblack@eecs.umich.edu //else 4144593Sgblack@eecs.umich.edu // predecoder.process(); 4154377Sgblack@eecs.umich.edu 4164377Sgblack@eecs.umich.edu //If an instruction is ready, decode it. Otherwise, we'll have to 4174377Sgblack@eecs.umich.edu //fetch beyond the MachInst at the current pc. 4184377Sgblack@eecs.umich.edu if (predecoder.extMachInstReady()) { 4194377Sgblack@eecs.umich.edu stayAtPC = false; 4207720Sgblack@eecs.umich.edu ExtMachInst machInst = predecoder.getExtMachInst(pcState); 4217720Sgblack@eecs.umich.edu thread->pcState(pcState); 4227720Sgblack@eecs.umich.edu instPtr = StaticInst::decode(machInst, pcState.instAddr()); 4234377Sgblack@eecs.umich.edu } else { 4244377Sgblack@eecs.umich.edu stayAtPC = true; 4254377Sgblack@eecs.umich.edu fetchOffset += sizeof(MachInst); 4264377Sgblack@eecs.umich.edu } 4274181Sgblack@eecs.umich.edu 4284181Sgblack@eecs.umich.edu //If we decoded an instruction and it's microcoded, start pulling 4294181Sgblack@eecs.umich.edu //out micro ops 4304539Sgblack@eecs.umich.edu if (instPtr && instPtr->isMacroop()) { 4313276Sgblack@eecs.umich.edu curMacroStaticInst = instPtr; 4327720Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 4333280Sgblack@eecs.umich.edu } else { 4343280Sgblack@eecs.umich.edu curStaticInst = instPtr; 4353276Sgblack@eecs.umich.edu } 4363276Sgblack@eecs.umich.edu } else { 4373276Sgblack@eecs.umich.edu //Read the next micro op from the macro op 4387720Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 4393276Sgblack@eecs.umich.edu } 4403276Sgblack@eecs.umich.edu 4414181Sgblack@eecs.umich.edu //If we decoded an instruction this "tick", record information about it. 4424181Sgblack@eecs.umich.edu if(curStaticInst) 4434181Sgblack@eecs.umich.edu { 4444522Ssaidi@eecs.umich.edu#if TRACING_ON 4455784Sgblack@eecs.umich.edu traceData = tracer->getInstRecord(curTick, tc, 4467720Sgblack@eecs.umich.edu curStaticInst, thread->pcState(), curMacroStaticInst); 4472470SN/A 4484181Sgblack@eecs.umich.edu DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n", 4494181Sgblack@eecs.umich.edu curStaticInst->getName(), curStaticInst->machInst); 4504522Ssaidi@eecs.umich.edu#endif // TRACING_ON 4514181Sgblack@eecs.umich.edu } 4522623SN/A} 4532623SN/A 4542623SN/Avoid 4552623SN/ABaseSimpleCPU::postExecute() 4562623SN/A{ 4577720Sgblack@eecs.umich.edu assert(curStaticInst); 4587720Sgblack@eecs.umich.edu 4597720Sgblack@eecs.umich.edu TheISA::PCState pc = tc->pcState(); 4607720Sgblack@eecs.umich.edu Addr instAddr = pc.instAddr(); 4612623SN/A#if FULL_SYSTEM 4627720Sgblack@eecs.umich.edu if (thread->profile) { 4633577Sgblack@eecs.umich.edu bool usermode = TheISA::inUserMode(tc); 4647720Sgblack@eecs.umich.edu thread->profilePC = usermode ? 1 : instAddr; 4655086Sgblack@eecs.umich.edu ProfileNode *node = thread->profile->consume(tc, curStaticInst); 4662623SN/A if (node) 4672683Sktlim@umich.edu thread->profileNode = node; 4682623SN/A } 4692420SN/A#endif 4702SN/A 4712623SN/A if (curStaticInst->isMemRef()) { 4722623SN/A numMemRefs++; 4732SN/A } 4742SN/A 4752623SN/A if (curStaticInst->isLoad()) { 4762623SN/A ++numLoad; 4772623SN/A comLoadEventQueue[0]->serviceEvents(numLoad); 4782623SN/A } 4792SN/A 4805953Ssaidi@eecs.umich.edu if (CPA::available()) { 4817720Sgblack@eecs.umich.edu CPA::cpa()->swAutoBegin(tc, pc.nextInstAddr()); 4825953Ssaidi@eecs.umich.edu } 4835953Ssaidi@eecs.umich.edu 4847720Sgblack@eecs.umich.edu traceFunctions(instAddr); 4852644Sstever@eecs.umich.edu 4862644Sstever@eecs.umich.edu if (traceData) { 4874046Sbinkertn@umich.edu traceData->dump(); 4884046Sbinkertn@umich.edu delete traceData; 4894046Sbinkertn@umich.edu traceData = NULL; 4902644Sstever@eecs.umich.edu } 4912623SN/A} 4922SN/A 4932SN/A 4942623SN/Avoid 4952623SN/ABaseSimpleCPU::advancePC(Fault fault) 4962623SN/A{ 4974377Sgblack@eecs.umich.edu //Since we're moving to a new pc, zero out the offset 4984377Sgblack@eecs.umich.edu fetchOffset = 0; 4992090SN/A if (fault != NoFault) { 5003905Ssaidi@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 5017678Sgblack@eecs.umich.edu fault->invoke(tc, curStaticInst); 5025120Sgblack@eecs.umich.edu predecoder.reset(); 5034377Sgblack@eecs.umich.edu } else { 5047720Sgblack@eecs.umich.edu if (curStaticInst) { 5057720Sgblack@eecs.umich.edu if (curStaticInst->isLastMicroop()) 5067720Sgblack@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 5077720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5087720Sgblack@eecs.umich.edu TheISA::advancePC(pcState, curStaticInst); 5097720Sgblack@eecs.umich.edu thread->pcState(pcState); 5103276Sgblack@eecs.umich.edu } 5112SN/A } 5122SN/A} 5132SN/A 5145250Sksewell@umich.edu/*Fault 5155222Sksewell@umich.eduBaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr) 5165222Sksewell@umich.edu{ 5175222Sksewell@umich.edu // translate to physical address 5185222Sksewell@umich.edu Fault fault = NoFault; 5195222Sksewell@umich.edu int CacheID = Op & 0x3; // Lower 3 bits identify Cache 5205222Sksewell@umich.edu int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation 5215222Sksewell@umich.edu if(CacheID > 1) 5225222Sksewell@umich.edu { 5235222Sksewell@umich.edu warn("CacheOps not implemented for secondary/tertiary caches\n"); 5245222Sksewell@umich.edu } 5255222Sksewell@umich.edu else 5265222Sksewell@umich.edu { 5275222Sksewell@umich.edu switch(CacheOP) 5285222Sksewell@umich.edu { // Fill Packet Type 5295222Sksewell@umich.edu case 0: warn("Invalidate Cache Op\n"); 5305222Sksewell@umich.edu break; 5315222Sksewell@umich.edu case 1: warn("Index Load Tag Cache Op\n"); 5325222Sksewell@umich.edu break; 5335222Sksewell@umich.edu case 2: warn("Index Store Tag Cache Op\n"); 5345222Sksewell@umich.edu break; 5355222Sksewell@umich.edu case 4: warn("Hit Invalidate Cache Op\n"); 5365222Sksewell@umich.edu break; 5375222Sksewell@umich.edu case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n"); 5385222Sksewell@umich.edu break; 5395222Sksewell@umich.edu case 6: warn("Hit Writeback\n"); 5405222Sksewell@umich.edu break; 5415222Sksewell@umich.edu case 7: warn("Fetch & Lock Cache Op\n"); 5425222Sksewell@umich.edu break; 5435222Sksewell@umich.edu default: warn("Unimplemented Cache Op\n"); 5445222Sksewell@umich.edu } 5455222Sksewell@umich.edu } 5465222Sksewell@umich.edu return fault; 5475250Sksewell@umich.edu}*/ 548