base.cc revision 7408
12SN/A/* 27338SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37338SAli.Saidi@ARM.com * All rights reserved 47338SAli.Saidi@ARM.com * 57338SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67338SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77338SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87338SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97338SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107338SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117338SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127338SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137338SAli.Saidi@ARM.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152SN/A * All rights reserved. 162SN/A * 172SN/A * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272SN/A * 282SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412SN/A */ 422SN/A 436216Snate@binkert.org#include "arch/faults.hh" 442439SN/A#include "arch/utility.hh" 456216Snate@binkert.org#include "base/cp_annotate.hh" 46146SN/A#include "base/cprintf.hh" 47146SN/A#include "base/inifile.hh" 48146SN/A#include "base/loader/symtab.hh" 49146SN/A#include "base/misc.hh" 50146SN/A#include "base/pollevent.hh" 51146SN/A#include "base/range.hh" 521717SN/A#include "base/stats/events.hh" 53146SN/A#include "base/trace.hh" 546216Snate@binkert.org#include "base/types.hh" 556658Snate@binkert.org#include "config/the_isa.hh" 561717SN/A#include "cpu/base.hh" 57146SN/A#include "cpu/exetrace.hh" 581977SN/A#include "cpu/profile.hh" 592623SN/A#include "cpu/simple/base.hh" 602683Sktlim@umich.edu#include "cpu/simple_thread.hh" 611717SN/A#include "cpu/smt.hh" 62146SN/A#include "cpu/static_inst.hh" 632683Sktlim@umich.edu#include "cpu/thread_context.hh" 643348Sbinkertn@umich.edu#include "mem/packet.hh" 656105Ssteve.reinhardt@amd.com#include "mem/request.hh" 666216Snate@binkert.org#include "params/BaseSimpleCPU.hh" 672036SN/A#include "sim/byteswap.hh" 68146SN/A#include "sim/debug.hh" 6956SN/A#include "sim/sim_events.hh" 7056SN/A#include "sim/sim_object.hh" 71695SN/A#include "sim/stats.hh" 722901Ssaidi@eecs.umich.edu#include "sim/system.hh" 732SN/A 741858SN/A#if FULL_SYSTEM 753565Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 763565Sgblack@eecs.umich.edu#include "arch/stacktrace.hh" 772171SN/A#include "arch/tlb.hh" 782170SN/A#include "arch/vtophys.hh" 793562Sgblack@eecs.umich.edu#include "base/remote_gdb.hh" 80146SN/A#else // !FULL_SYSTEM 812462SN/A#include "mem/mem_object.hh" 82146SN/A#endif // FULL_SYSTEM 832SN/A 842SN/Ausing namespace std; 852449SN/Ausing namespace TheISA; 861355SN/A 875529Snate@binkert.orgBaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p) 884495Sacolyte@umich.edu : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL) 89224SN/A{ 901858SN/A#if FULL_SYSTEM 912683Sktlim@umich.edu thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb); 922420SN/A#else 935529Snate@binkert.org thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0], 946331Sgblack@eecs.umich.edu p->itb, p->dtb); 952420SN/A#endif // !FULL_SYSTEM 962SN/A 976029Ssteve.reinhardt@amd.com thread->setStatus(ThreadContext::Halted); 982672Sktlim@umich.edu 992683Sktlim@umich.edu tc = thread->getTC(); 1002SN/A 1012SN/A numInst = 0; 102334SN/A startNumInst = 0; 103140SN/A numLoad = 0; 104334SN/A startNumLoad = 0; 1052SN/A lastIcacheStall = 0; 1062SN/A lastDcacheStall = 0; 1072SN/A 1082680Sktlim@umich.edu threadContexts.push_back(tc); 1094377Sgblack@eecs.umich.edu 1105169Ssaidi@eecs.umich.edu 1114377Sgblack@eecs.umich.edu fetchOffset = 0; 1124377Sgblack@eecs.umich.edu stayAtPC = false; 1132SN/A} 1142SN/A 1152623SN/ABaseSimpleCPU::~BaseSimpleCPU() 1162SN/A{ 1172SN/A} 1182SN/A 119180SN/Avoid 1202623SN/ABaseSimpleCPU::deallocateContext(int thread_num) 121393SN/A{ 122393SN/A // for now, these are equivalent 123393SN/A suspendContext(thread_num); 124393SN/A} 125384SN/A 126384SN/A 127393SN/Avoid 1282623SN/ABaseSimpleCPU::haltContext(int thread_num) 129393SN/A{ 130393SN/A // for now, these are equivalent 131393SN/A suspendContext(thread_num); 132393SN/A} 133384SN/A 134189SN/A 135189SN/Avoid 1362623SN/ABaseSimpleCPU::regStats() 1372SN/A{ 138729SN/A using namespace Stats; 139334SN/A 1402SN/A BaseCPU::regStats(); 1412SN/A 1422SN/A numInsts 1432SN/A .name(name() + ".num_insts") 1442SN/A .desc("Number of instructions executed") 1452SN/A ; 1462SN/A 1472SN/A numMemRefs 1482SN/A .name(name() + ".num_refs") 1492SN/A .desc("Number of memory references") 1502SN/A ; 1512SN/A 1521001SN/A notIdleFraction 1531001SN/A .name(name() + ".not_idle_fraction") 1541001SN/A .desc("Percentage of non-idle cycles") 1551001SN/A ; 1561001SN/A 1572SN/A idleFraction 1582SN/A .name(name() + ".idle_fraction") 1592SN/A .desc("Percentage of idle cycles") 1602SN/A ; 1612SN/A 1622SN/A icacheStallCycles 1632SN/A .name(name() + ".icache_stall_cycles") 1642SN/A .desc("ICache total stall cycles") 1652SN/A .prereq(icacheStallCycles) 1662SN/A ; 1672SN/A 1682SN/A dcacheStallCycles 1692SN/A .name(name() + ".dcache_stall_cycles") 1702SN/A .desc("DCache total stall cycles") 1712SN/A .prereq(dcacheStallCycles) 1722SN/A ; 1732SN/A 1742390SN/A icacheRetryCycles 1752390SN/A .name(name() + ".icache_retry_cycles") 1762390SN/A .desc("ICache total retry cycles") 1772390SN/A .prereq(icacheRetryCycles) 1782390SN/A ; 1792390SN/A 1802390SN/A dcacheRetryCycles 1812390SN/A .name(name() + ".dcache_retry_cycles") 1822390SN/A .desc("DCache total retry cycles") 1832390SN/A .prereq(dcacheRetryCycles) 1842390SN/A ; 1852390SN/A 186385SN/A idleFraction = constant(1.0) - notIdleFraction; 1872SN/A} 1882SN/A 1892SN/Avoid 1902623SN/ABaseSimpleCPU::resetStats() 191334SN/A{ 1922361SN/A// startNumInst = numInst; 1935496Ssaidi@eecs.umich.edu notIdleFraction = (_status != Idle); 194334SN/A} 195334SN/A 196334SN/Avoid 1972623SN/ABaseSimpleCPU::serialize(ostream &os) 1982SN/A{ 1995496Ssaidi@eecs.umich.edu SERIALIZE_ENUM(_status); 200921SN/A BaseCPU::serialize(os); 2012915Sktlim@umich.edu// SERIALIZE_SCALAR(inst); 2022915Sktlim@umich.edu nameOut(os, csprintf("%s.xc.0", name())); 2032683Sktlim@umich.edu thread->serialize(os); 2042SN/A} 2052SN/A 2062SN/Avoid 2072623SN/ABaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 2082SN/A{ 2095496Ssaidi@eecs.umich.edu UNSERIALIZE_ENUM(_status); 210921SN/A BaseCPU::unserialize(cp, section); 2112915Sktlim@umich.edu// UNSERIALIZE_SCALAR(inst); 2122915Sktlim@umich.edu thread->unserialize(cp, csprintf("%s.xc.0", section)); 2132SN/A} 2142SN/A 2152SN/Avoid 2166221Snate@binkert.orgchange_thread_state(ThreadID tid, int activate, int priority) 2172SN/A{ 2182SN/A} 2192SN/A 2207045Ssteve.reinhardt@amd.comvoid 2217045Ssteve.reinhardt@amd.comBaseSimpleCPU::prefetch(Addr addr, unsigned flags) 2227045Ssteve.reinhardt@amd.com{ 2237045Ssteve.reinhardt@amd.com if (traceData) { 2247045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 2257045Ssteve.reinhardt@amd.com } 2267045Ssteve.reinhardt@amd.com 2277045Ssteve.reinhardt@amd.com // need to do this... 2287045Ssteve.reinhardt@amd.com} 2297045Ssteve.reinhardt@amd.com 2307045Ssteve.reinhardt@amd.comvoid 2317045Ssteve.reinhardt@amd.comBaseSimpleCPU::writeHint(Addr addr, int size, unsigned flags) 2327045Ssteve.reinhardt@amd.com{ 2337045Ssteve.reinhardt@amd.com if (traceData) { 2347045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 2357045Ssteve.reinhardt@amd.com } 2367045Ssteve.reinhardt@amd.com 2377045Ssteve.reinhardt@amd.com // need to do this... 2387045Ssteve.reinhardt@amd.com} 2397045Ssteve.reinhardt@amd.com 2407045Ssteve.reinhardt@amd.com 241595SN/AFault 2422623SN/ABaseSimpleCPU::copySrcTranslate(Addr src) 243595SN/A{ 2442390SN/A#if 0 2451080SN/A static bool no_warn = true; 2466227Snate@binkert.org unsigned blk_size = 2476227Snate@binkert.org (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 2481080SN/A // Only support block sizes of 64 atm. 2491080SN/A assert(blk_size == 64); 2501080SN/A int offset = src & (blk_size - 1); 2511080SN/A 2521080SN/A // Make sure block doesn't span page 2531121SN/A if (no_warn && 2542107SN/A (src & PageMask) != ((src + blk_size) & PageMask) && 2551089SN/A (src >> 40) != 0xfffffc) { 2561089SN/A warn("Copied block source spans pages %x.", src); 2571080SN/A no_warn = false; 2581080SN/A } 2591080SN/A 2601080SN/A memReq->reset(src & ~(blk_size - 1), blk_size); 261595SN/A 2622623SN/A // translate to physical address 2632683Sktlim@umich.edu Fault fault = thread->translateDataReadReq(req); 264595SN/A 2652090SN/A if (fault == NoFault) { 2662683Sktlim@umich.edu thread->copySrcAddr = src; 2672683Sktlim@umich.edu thread->copySrcPhysAddr = memReq->paddr + offset; 268595SN/A } else { 2692205SN/A assert(!fault->isAlignmentFault()); 2702205SN/A 2712683Sktlim@umich.edu thread->copySrcAddr = 0; 2722683Sktlim@umich.edu thread->copySrcPhysAddr = 0; 273595SN/A } 274595SN/A return fault; 2752390SN/A#else 2762423SN/A return NoFault; 2772390SN/A#endif 278595SN/A} 279595SN/A 280595SN/AFault 2812623SN/ABaseSimpleCPU::copy(Addr dest) 282595SN/A{ 2832390SN/A#if 0 2841080SN/A static bool no_warn = true; 2856227Snate@binkert.org unsigned blk_size = 2866227Snate@binkert.org (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 2871080SN/A // Only support block sizes of 64 atm. 2881080SN/A assert(blk_size == 64); 289595SN/A uint8_t data[blk_size]; 2902683Sktlim@umich.edu //assert(thread->copySrcAddr); 2911080SN/A int offset = dest & (blk_size - 1); 2921080SN/A 2931080SN/A // Make sure block doesn't span page 2941121SN/A if (no_warn && 2952107SN/A (dest & PageMask) != ((dest + blk_size) & PageMask) && 2961089SN/A (dest >> 40) != 0xfffffc) { 2971080SN/A no_warn = false; 2981089SN/A warn("Copied block destination spans pages %x. ", dest); 2991080SN/A } 3001080SN/A 3011080SN/A memReq->reset(dest & ~(blk_size -1), blk_size); 302595SN/A // translate to physical address 3032683Sktlim@umich.edu Fault fault = thread->translateDataWriteReq(req); 3041080SN/A 3052090SN/A if (fault == NoFault) { 3061080SN/A Addr dest_addr = memReq->paddr + offset; 307595SN/A // Need to read straight from memory since we have more than 8 bytes. 3082683Sktlim@umich.edu memReq->paddr = thread->copySrcPhysAddr; 3092683Sktlim@umich.edu thread->mem->read(memReq, data); 310595SN/A memReq->paddr = dest_addr; 3112683Sktlim@umich.edu thread->mem->write(memReq, data); 3121098SN/A if (dcacheInterface) { 3131098SN/A memReq->cmd = Copy; 3141098SN/A memReq->completionEvent = NULL; 3152683Sktlim@umich.edu memReq->paddr = thread->copySrcPhysAddr; 3161098SN/A memReq->dest = dest_addr; 3171098SN/A memReq->size = 64; 3181098SN/A memReq->time = curTick; 3191098SN/A dcacheInterface->access(memReq); 3201098SN/A } 321595SN/A } 3222205SN/A else 3232205SN/A assert(!fault->isAlignmentFault()); 3242205SN/A 325595SN/A return fault; 3262390SN/A#else 3272420SN/A panic("copy not implemented"); 3282423SN/A return NoFault; 3292390SN/A#endif 330595SN/A} 331595SN/A 3321858SN/A#if FULL_SYSTEM 3332SN/AAddr 3342623SN/ABaseSimpleCPU::dbg_vtophys(Addr addr) 3352SN/A{ 3362680Sktlim@umich.edu return vtophys(tc, addr); 3372SN/A} 3382SN/A#endif // FULL_SYSTEM 3392SN/A 3401858SN/A#if FULL_SYSTEM 3412SN/Avoid 3425807Snate@binkert.orgBaseSimpleCPU::wakeup() 3432SN/A{ 3445807Snate@binkert.org if (thread->status() != ThreadContext::Suspended) 3455807Snate@binkert.org return; 3462SN/A 3475807Snate@binkert.org DPRINTF(Quiesce,"Suspended Processor awoke\n"); 3485807Snate@binkert.org thread->activate(); 3492SN/A} 3502SN/A#endif // FULL_SYSTEM 3512SN/A 3522SN/Avoid 3532623SN/ABaseSimpleCPU::checkForInterrupts() 3542SN/A{ 3551858SN/A#if FULL_SYSTEM 3565704Snate@binkert.org if (checkInterrupts(tc)) { 3575647Sgblack@eecs.umich.edu Fault interrupt = interrupts->getInterrupt(tc); 3582SN/A 3593520Sgblack@eecs.umich.edu if (interrupt != NoFault) { 3607338SAli.Saidi@ARM.com fetchOffset = 0; 3615647Sgblack@eecs.umich.edu interrupts->updateIntrInfo(tc); 3623520Sgblack@eecs.umich.edu interrupt->invoke(tc); 3637408Sgblack@eecs.umich.edu predecoder.reset(); 3642SN/A } 3652SN/A } 3662SN/A#endif 3672623SN/A} 3682SN/A 3692623SN/A 3705894Sgblack@eecs.umich.eduvoid 3712662Sstever@eecs.umich.eduBaseSimpleCPU::setupFetchRequest(Request *req) 3722623SN/A{ 3734514Ssaidi@eecs.umich.edu Addr threadPC = thread->readPC(); 3744495Sacolyte@umich.edu 3752623SN/A // set up memory request for instruction fetch 3763093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 3774495Sacolyte@umich.edu DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC, 3783093Sksewell@umich.edu thread->readNextPC(),thread->readNextNPC()); 3793093Sksewell@umich.edu#else 3804564Sgblack@eecs.umich.edu DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p\n",threadPC, 3812741Sksewell@umich.edu thread->readNextPC()); 3822741Sksewell@umich.edu#endif 3832623SN/A 3844564Sgblack@eecs.umich.edu Addr fetchPC = (threadPC & PCMask) + fetchOffset; 3856105Ssteve.reinhardt@amd.com req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, threadPC); 3862623SN/A} 3872623SN/A 3882623SN/A 3892623SN/Avoid 3902623SN/ABaseSimpleCPU::preExecute() 3912623SN/A{ 3922SN/A // maintain $r0 semantics 3932683Sktlim@umich.edu thread->setIntReg(ZeroReg, 0); 3942427SN/A#if THE_ISA == ALPHA_ISA 3952683Sktlim@umich.edu thread->setFloatReg(ZeroReg, 0.0); 3962427SN/A#endif // ALPHA_ISA 3972SN/A 3982623SN/A // check for instruction-count-based events 3992623SN/A comInstEventQueue[0]->serviceEvents(numInst); 4002SN/A 4012623SN/A // decode the instruction 4022623SN/A inst = gtoh(inst); 4034377Sgblack@eecs.umich.edu 4045665Sgblack@eecs.umich.edu MicroPC upc = thread->readMicroPC(); 4054377Sgblack@eecs.umich.edu 4065665Sgblack@eecs.umich.edu if (isRomMicroPC(upc)) { 4075665Sgblack@eecs.umich.edu stayAtPC = false; 4085665Sgblack@eecs.umich.edu curStaticInst = microcodeRom.fetchMicroop(upc, curMacroStaticInst); 4095665Sgblack@eecs.umich.edu } else if (!curMacroStaticInst) { 4105665Sgblack@eecs.umich.edu //We're not in the middle of a macro instruction 4114181Sgblack@eecs.umich.edu StaticInstPtr instPtr = NULL; 4124181Sgblack@eecs.umich.edu 4134181Sgblack@eecs.umich.edu //Predecode, ie bundle up an ExtMachInst 4144182Sgblack@eecs.umich.edu //This should go away once the constructor can be set up properly 4154182Sgblack@eecs.umich.edu predecoder.setTC(thread->getTC()); 4164182Sgblack@eecs.umich.edu //If more fetch data is needed, pass it in. 4174593Sgblack@eecs.umich.edu Addr fetchPC = (thread->readPC() & PCMask) + fetchOffset; 4184593Sgblack@eecs.umich.edu //if(predecoder.needMoreBytes()) 4194593Sgblack@eecs.umich.edu predecoder.moreBytes(thread->readPC(), fetchPC, inst); 4204593Sgblack@eecs.umich.edu //else 4214593Sgblack@eecs.umich.edu // predecoder.process(); 4224377Sgblack@eecs.umich.edu 4234377Sgblack@eecs.umich.edu //If an instruction is ready, decode it. Otherwise, we'll have to 4244377Sgblack@eecs.umich.edu //fetch beyond the MachInst at the current pc. 4254377Sgblack@eecs.umich.edu if (predecoder.extMachInstReady()) { 4267100Sgblack@eecs.umich.edu#if THE_ISA == X86_ISA || THE_ISA == ARM_ISA 4274377Sgblack@eecs.umich.edu thread->setNextPC(thread->readPC() + predecoder.getInstSize()); 4284377Sgblack@eecs.umich.edu#endif // X86_ISA 4294377Sgblack@eecs.umich.edu stayAtPC = false; 4304572Sacolyte@umich.edu instPtr = StaticInst::decode(predecoder.getExtMachInst(), 4314572Sacolyte@umich.edu thread->readPC()); 4324377Sgblack@eecs.umich.edu } else { 4334377Sgblack@eecs.umich.edu stayAtPC = true; 4344377Sgblack@eecs.umich.edu fetchOffset += sizeof(MachInst); 4354377Sgblack@eecs.umich.edu } 4364181Sgblack@eecs.umich.edu 4374181Sgblack@eecs.umich.edu //If we decoded an instruction and it's microcoded, start pulling 4384181Sgblack@eecs.umich.edu //out micro ops 4394539Sgblack@eecs.umich.edu if (instPtr && instPtr->isMacroop()) { 4403276Sgblack@eecs.umich.edu curMacroStaticInst = instPtr; 4415665Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst->fetchMicroop(upc); 4423280Sgblack@eecs.umich.edu } else { 4433280Sgblack@eecs.umich.edu curStaticInst = instPtr; 4443276Sgblack@eecs.umich.edu } 4453276Sgblack@eecs.umich.edu } else { 4463276Sgblack@eecs.umich.edu //Read the next micro op from the macro op 4475665Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst->fetchMicroop(upc); 4483276Sgblack@eecs.umich.edu } 4493276Sgblack@eecs.umich.edu 4504181Sgblack@eecs.umich.edu //If we decoded an instruction this "tick", record information about it. 4514181Sgblack@eecs.umich.edu if(curStaticInst) 4524181Sgblack@eecs.umich.edu { 4534522Ssaidi@eecs.umich.edu#if TRACING_ON 4545784Sgblack@eecs.umich.edu traceData = tracer->getInstRecord(curTick, tc, 4555784Sgblack@eecs.umich.edu curStaticInst, thread->readPC(), 4565784Sgblack@eecs.umich.edu curMacroStaticInst, thread->readMicroPC()); 4572470SN/A 4584181Sgblack@eecs.umich.edu DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n", 4594181Sgblack@eecs.umich.edu curStaticInst->getName(), curStaticInst->machInst); 4604522Ssaidi@eecs.umich.edu#endif // TRACING_ON 4612623SN/A 4622623SN/A#if FULL_SYSTEM 4634181Sgblack@eecs.umich.edu thread->setInst(inst); 4642623SN/A#endif // FULL_SYSTEM 4654181Sgblack@eecs.umich.edu } 4662623SN/A} 4672623SN/A 4682623SN/Avoid 4692623SN/ABaseSimpleCPU::postExecute() 4702623SN/A{ 4712623SN/A#if FULL_SYSTEM 4725086Sgblack@eecs.umich.edu if (thread->profile && curStaticInst) { 4733577Sgblack@eecs.umich.edu bool usermode = TheISA::inUserMode(tc); 4742683Sktlim@umich.edu thread->profilePC = usermode ? 1 : thread->readPC(); 4755086Sgblack@eecs.umich.edu ProfileNode *node = thread->profile->consume(tc, curStaticInst); 4762623SN/A if (node) 4772683Sktlim@umich.edu thread->profileNode = node; 4782623SN/A } 4792420SN/A#endif 4802SN/A 4812623SN/A if (curStaticInst->isMemRef()) { 4822623SN/A numMemRefs++; 4832SN/A } 4842SN/A 4852623SN/A if (curStaticInst->isLoad()) { 4862623SN/A ++numLoad; 4872623SN/A comLoadEventQueue[0]->serviceEvents(numLoad); 4882623SN/A } 4892SN/A 4905953Ssaidi@eecs.umich.edu if (CPA::available()) { 4915953Ssaidi@eecs.umich.edu CPA::cpa()->swAutoBegin(tc, thread->readNextPC()); 4925953Ssaidi@eecs.umich.edu } 4935953Ssaidi@eecs.umich.edu 4942683Sktlim@umich.edu traceFunctions(thread->readPC()); 4952644Sstever@eecs.umich.edu 4962644Sstever@eecs.umich.edu if (traceData) { 4974046Sbinkertn@umich.edu traceData->dump(); 4984046Sbinkertn@umich.edu delete traceData; 4994046Sbinkertn@umich.edu traceData = NULL; 5002644Sstever@eecs.umich.edu } 5012623SN/A} 5022SN/A 5032SN/A 5042623SN/Avoid 5052623SN/ABaseSimpleCPU::advancePC(Fault fault) 5062623SN/A{ 5074377Sgblack@eecs.umich.edu //Since we're moving to a new pc, zero out the offset 5084377Sgblack@eecs.umich.edu fetchOffset = 0; 5092090SN/A if (fault != NoFault) { 5103905Ssaidi@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 5117408Sgblack@eecs.umich.edu fault->invoke(tc); 5125120Sgblack@eecs.umich.edu predecoder.reset(); 5134377Sgblack@eecs.umich.edu } else { 5143276Sgblack@eecs.umich.edu //If we're at the last micro op for this instruction 5154539Sgblack@eecs.umich.edu if (curStaticInst && curStaticInst->isLastMicroop()) { 5165665Sgblack@eecs.umich.edu //We should be working with a macro op or be in the ROM 5175665Sgblack@eecs.umich.edu assert(curMacroStaticInst || 5185665Sgblack@eecs.umich.edu isRomMicroPC(thread->readMicroPC())); 5193276Sgblack@eecs.umich.edu //Close out this macro op, and clean up the 5203276Sgblack@eecs.umich.edu //microcode state 5213280Sgblack@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 5225665Sgblack@eecs.umich.edu thread->setMicroPC(normalMicroPC(0)); 5235665Sgblack@eecs.umich.edu thread->setNextMicroPC(normalMicroPC(1)); 5243276Sgblack@eecs.umich.edu } 5253276Sgblack@eecs.umich.edu //If we're still in a macro op 5265665Sgblack@eecs.umich.edu if (curMacroStaticInst || isRomMicroPC(thread->readMicroPC())) { 5273276Sgblack@eecs.umich.edu //Advance the micro pc 5283280Sgblack@eecs.umich.edu thread->setMicroPC(thread->readNextMicroPC()); 5293276Sgblack@eecs.umich.edu //Advance the "next" micro pc. Note that there are no delay 5303276Sgblack@eecs.umich.edu //slots, and micro ops are "word" addressed. 5313280Sgblack@eecs.umich.edu thread->setNextMicroPC(thread->readNextMicroPC() + 1); 5323276Sgblack@eecs.umich.edu } else { 5333276Sgblack@eecs.umich.edu // go to the next instruction 5343276Sgblack@eecs.umich.edu thread->setPC(thread->readNextPC()); 5353276Sgblack@eecs.umich.edu thread->setNextPC(thread->readNextNPC()); 5363276Sgblack@eecs.umich.edu thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst)); 5373276Sgblack@eecs.umich.edu assert(thread->readNextPC() != thread->readNextNPC()); 5383276Sgblack@eecs.umich.edu } 5392SN/A } 5402SN/A} 5412SN/A 5425250Sksewell@umich.edu/*Fault 5435222Sksewell@umich.eduBaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr) 5445222Sksewell@umich.edu{ 5455222Sksewell@umich.edu // translate to physical address 5465222Sksewell@umich.edu Fault fault = NoFault; 5475222Sksewell@umich.edu int CacheID = Op & 0x3; // Lower 3 bits identify Cache 5485222Sksewell@umich.edu int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation 5495222Sksewell@umich.edu if(CacheID > 1) 5505222Sksewell@umich.edu { 5515222Sksewell@umich.edu warn("CacheOps not implemented for secondary/tertiary caches\n"); 5525222Sksewell@umich.edu } 5535222Sksewell@umich.edu else 5545222Sksewell@umich.edu { 5555222Sksewell@umich.edu switch(CacheOP) 5565222Sksewell@umich.edu { // Fill Packet Type 5575222Sksewell@umich.edu case 0: warn("Invalidate Cache Op\n"); 5585222Sksewell@umich.edu break; 5595222Sksewell@umich.edu case 1: warn("Index Load Tag Cache Op\n"); 5605222Sksewell@umich.edu break; 5615222Sksewell@umich.edu case 2: warn("Index Store Tag Cache Op\n"); 5625222Sksewell@umich.edu break; 5635222Sksewell@umich.edu case 4: warn("Hit Invalidate Cache Op\n"); 5645222Sksewell@umich.edu break; 5655222Sksewell@umich.edu case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n"); 5665222Sksewell@umich.edu break; 5675222Sksewell@umich.edu case 6: warn("Hit Writeback\n"); 5685222Sksewell@umich.edu break; 5695222Sksewell@umich.edu case 7: warn("Fetch & Lock Cache Op\n"); 5705222Sksewell@umich.edu break; 5715222Sksewell@umich.edu default: warn("Unimplemented Cache Op\n"); 5725222Sksewell@umich.edu } 5735222Sksewell@umich.edu } 5745222Sksewell@umich.edu return fault; 5755250Sksewell@umich.edu}*/ 576