base.cc revision 7045
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292SN/A */ 302SN/A 316216Snate@binkert.org#include "arch/faults.hh" 322439SN/A#include "arch/utility.hh" 336216Snate@binkert.org#include "base/cp_annotate.hh" 34146SN/A#include "base/cprintf.hh" 35146SN/A#include "base/inifile.hh" 36146SN/A#include "base/loader/symtab.hh" 37146SN/A#include "base/misc.hh" 38146SN/A#include "base/pollevent.hh" 39146SN/A#include "base/range.hh" 401717SN/A#include "base/stats/events.hh" 41146SN/A#include "base/trace.hh" 426216Snate@binkert.org#include "base/types.hh" 436658Snate@binkert.org#include "config/the_isa.hh" 441717SN/A#include "cpu/base.hh" 45146SN/A#include "cpu/exetrace.hh" 461977SN/A#include "cpu/profile.hh" 472623SN/A#include "cpu/simple/base.hh" 482683Sktlim@umich.edu#include "cpu/simple_thread.hh" 491717SN/A#include "cpu/smt.hh" 50146SN/A#include "cpu/static_inst.hh" 512683Sktlim@umich.edu#include "cpu/thread_context.hh" 523348Sbinkertn@umich.edu#include "mem/packet.hh" 536105Ssteve.reinhardt@amd.com#include "mem/request.hh" 546216Snate@binkert.org#include "params/BaseSimpleCPU.hh" 552036SN/A#include "sim/byteswap.hh" 56146SN/A#include "sim/debug.hh" 5756SN/A#include "sim/sim_events.hh" 5856SN/A#include "sim/sim_object.hh" 59695SN/A#include "sim/stats.hh" 602901Ssaidi@eecs.umich.edu#include "sim/system.hh" 612SN/A 621858SN/A#if FULL_SYSTEM 633565Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 643565Sgblack@eecs.umich.edu#include "arch/stacktrace.hh" 652171SN/A#include "arch/tlb.hh" 662170SN/A#include "arch/vtophys.hh" 673562Sgblack@eecs.umich.edu#include "base/remote_gdb.hh" 68146SN/A#else // !FULL_SYSTEM 692462SN/A#include "mem/mem_object.hh" 70146SN/A#endif // FULL_SYSTEM 712SN/A 722SN/Ausing namespace std; 732449SN/Ausing namespace TheISA; 741355SN/A 755529Snate@binkert.orgBaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p) 764495Sacolyte@umich.edu : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL) 77224SN/A{ 781858SN/A#if FULL_SYSTEM 792683Sktlim@umich.edu thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb); 802420SN/A#else 815529Snate@binkert.org thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0], 826331Sgblack@eecs.umich.edu p->itb, p->dtb); 832420SN/A#endif // !FULL_SYSTEM 842SN/A 856029Ssteve.reinhardt@amd.com thread->setStatus(ThreadContext::Halted); 862672Sktlim@umich.edu 872683Sktlim@umich.edu tc = thread->getTC(); 882SN/A 892SN/A numInst = 0; 90334SN/A startNumInst = 0; 91140SN/A numLoad = 0; 92334SN/A startNumLoad = 0; 932SN/A lastIcacheStall = 0; 942SN/A lastDcacheStall = 0; 952SN/A 962680Sktlim@umich.edu threadContexts.push_back(tc); 974377Sgblack@eecs.umich.edu 985169Ssaidi@eecs.umich.edu 994377Sgblack@eecs.umich.edu fetchOffset = 0; 1004377Sgblack@eecs.umich.edu stayAtPC = false; 1012SN/A} 1022SN/A 1032623SN/ABaseSimpleCPU::~BaseSimpleCPU() 1042SN/A{ 1052SN/A} 1062SN/A 107180SN/Avoid 1082623SN/ABaseSimpleCPU::deallocateContext(int thread_num) 109393SN/A{ 110393SN/A // for now, these are equivalent 111393SN/A suspendContext(thread_num); 112393SN/A} 113384SN/A 114384SN/A 115393SN/Avoid 1162623SN/ABaseSimpleCPU::haltContext(int thread_num) 117393SN/A{ 118393SN/A // for now, these are equivalent 119393SN/A suspendContext(thread_num); 120393SN/A} 121384SN/A 122189SN/A 123189SN/Avoid 1242623SN/ABaseSimpleCPU::regStats() 1252SN/A{ 126729SN/A using namespace Stats; 127334SN/A 1282SN/A BaseCPU::regStats(); 1292SN/A 1302SN/A numInsts 1312SN/A .name(name() + ".num_insts") 1322SN/A .desc("Number of instructions executed") 1332SN/A ; 1342SN/A 1352SN/A numMemRefs 1362SN/A .name(name() + ".num_refs") 1372SN/A .desc("Number of memory references") 1382SN/A ; 1392SN/A 1401001SN/A notIdleFraction 1411001SN/A .name(name() + ".not_idle_fraction") 1421001SN/A .desc("Percentage of non-idle cycles") 1431001SN/A ; 1441001SN/A 1452SN/A idleFraction 1462SN/A .name(name() + ".idle_fraction") 1472SN/A .desc("Percentage of idle cycles") 1482SN/A ; 1492SN/A 1502SN/A icacheStallCycles 1512SN/A .name(name() + ".icache_stall_cycles") 1522SN/A .desc("ICache total stall cycles") 1532SN/A .prereq(icacheStallCycles) 1542SN/A ; 1552SN/A 1562SN/A dcacheStallCycles 1572SN/A .name(name() + ".dcache_stall_cycles") 1582SN/A .desc("DCache total stall cycles") 1592SN/A .prereq(dcacheStallCycles) 1602SN/A ; 1612SN/A 1622390SN/A icacheRetryCycles 1632390SN/A .name(name() + ".icache_retry_cycles") 1642390SN/A .desc("ICache total retry cycles") 1652390SN/A .prereq(icacheRetryCycles) 1662390SN/A ; 1672390SN/A 1682390SN/A dcacheRetryCycles 1692390SN/A .name(name() + ".dcache_retry_cycles") 1702390SN/A .desc("DCache total retry cycles") 1712390SN/A .prereq(dcacheRetryCycles) 1722390SN/A ; 1732390SN/A 174385SN/A idleFraction = constant(1.0) - notIdleFraction; 1752SN/A} 1762SN/A 1772SN/Avoid 1782623SN/ABaseSimpleCPU::resetStats() 179334SN/A{ 1802361SN/A// startNumInst = numInst; 1815496Ssaidi@eecs.umich.edu notIdleFraction = (_status != Idle); 182334SN/A} 183334SN/A 184334SN/Avoid 1852623SN/ABaseSimpleCPU::serialize(ostream &os) 1862SN/A{ 1875496Ssaidi@eecs.umich.edu SERIALIZE_ENUM(_status); 188921SN/A BaseCPU::serialize(os); 1892915Sktlim@umich.edu// SERIALIZE_SCALAR(inst); 1902915Sktlim@umich.edu nameOut(os, csprintf("%s.xc.0", name())); 1912683Sktlim@umich.edu thread->serialize(os); 1922SN/A} 1932SN/A 1942SN/Avoid 1952623SN/ABaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1962SN/A{ 1975496Ssaidi@eecs.umich.edu UNSERIALIZE_ENUM(_status); 198921SN/A BaseCPU::unserialize(cp, section); 1992915Sktlim@umich.edu// UNSERIALIZE_SCALAR(inst); 2002915Sktlim@umich.edu thread->unserialize(cp, csprintf("%s.xc.0", section)); 2012SN/A} 2022SN/A 2032SN/Avoid 2046221Snate@binkert.orgchange_thread_state(ThreadID tid, int activate, int priority) 2052SN/A{ 2062SN/A} 2072SN/A 2087045Ssteve.reinhardt@amd.comvoid 2097045Ssteve.reinhardt@amd.comBaseSimpleCPU::prefetch(Addr addr, unsigned flags) 2107045Ssteve.reinhardt@amd.com{ 2117045Ssteve.reinhardt@amd.com if (traceData) { 2127045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 2137045Ssteve.reinhardt@amd.com } 2147045Ssteve.reinhardt@amd.com 2157045Ssteve.reinhardt@amd.com // need to do this... 2167045Ssteve.reinhardt@amd.com} 2177045Ssteve.reinhardt@amd.com 2187045Ssteve.reinhardt@amd.comvoid 2197045Ssteve.reinhardt@amd.comBaseSimpleCPU::writeHint(Addr addr, int size, unsigned flags) 2207045Ssteve.reinhardt@amd.com{ 2217045Ssteve.reinhardt@amd.com if (traceData) { 2227045Ssteve.reinhardt@amd.com traceData->setAddr(addr); 2237045Ssteve.reinhardt@amd.com } 2247045Ssteve.reinhardt@amd.com 2257045Ssteve.reinhardt@amd.com // need to do this... 2267045Ssteve.reinhardt@amd.com} 2277045Ssteve.reinhardt@amd.com 2287045Ssteve.reinhardt@amd.com 229595SN/AFault 2302623SN/ABaseSimpleCPU::copySrcTranslate(Addr src) 231595SN/A{ 2322390SN/A#if 0 2331080SN/A static bool no_warn = true; 2346227Snate@binkert.org unsigned blk_size = 2356227Snate@binkert.org (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 2361080SN/A // Only support block sizes of 64 atm. 2371080SN/A assert(blk_size == 64); 2381080SN/A int offset = src & (blk_size - 1); 2391080SN/A 2401080SN/A // Make sure block doesn't span page 2411121SN/A if (no_warn && 2422107SN/A (src & PageMask) != ((src + blk_size) & PageMask) && 2431089SN/A (src >> 40) != 0xfffffc) { 2441089SN/A warn("Copied block source spans pages %x.", src); 2451080SN/A no_warn = false; 2461080SN/A } 2471080SN/A 2481080SN/A memReq->reset(src & ~(blk_size - 1), blk_size); 249595SN/A 2502623SN/A // translate to physical address 2512683Sktlim@umich.edu Fault fault = thread->translateDataReadReq(req); 252595SN/A 2532090SN/A if (fault == NoFault) { 2542683Sktlim@umich.edu thread->copySrcAddr = src; 2552683Sktlim@umich.edu thread->copySrcPhysAddr = memReq->paddr + offset; 256595SN/A } else { 2572205SN/A assert(!fault->isAlignmentFault()); 2582205SN/A 2592683Sktlim@umich.edu thread->copySrcAddr = 0; 2602683Sktlim@umich.edu thread->copySrcPhysAddr = 0; 261595SN/A } 262595SN/A return fault; 2632390SN/A#else 2642423SN/A return NoFault; 2652390SN/A#endif 266595SN/A} 267595SN/A 268595SN/AFault 2692623SN/ABaseSimpleCPU::copy(Addr dest) 270595SN/A{ 2712390SN/A#if 0 2721080SN/A static bool no_warn = true; 2736227Snate@binkert.org unsigned blk_size = 2746227Snate@binkert.org (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 2751080SN/A // Only support block sizes of 64 atm. 2761080SN/A assert(blk_size == 64); 277595SN/A uint8_t data[blk_size]; 2782683Sktlim@umich.edu //assert(thread->copySrcAddr); 2791080SN/A int offset = dest & (blk_size - 1); 2801080SN/A 2811080SN/A // Make sure block doesn't span page 2821121SN/A if (no_warn && 2832107SN/A (dest & PageMask) != ((dest + blk_size) & PageMask) && 2841089SN/A (dest >> 40) != 0xfffffc) { 2851080SN/A no_warn = false; 2861089SN/A warn("Copied block destination spans pages %x. ", dest); 2871080SN/A } 2881080SN/A 2891080SN/A memReq->reset(dest & ~(blk_size -1), blk_size); 290595SN/A // translate to physical address 2912683Sktlim@umich.edu Fault fault = thread->translateDataWriteReq(req); 2921080SN/A 2932090SN/A if (fault == NoFault) { 2941080SN/A Addr dest_addr = memReq->paddr + offset; 295595SN/A // Need to read straight from memory since we have more than 8 bytes. 2962683Sktlim@umich.edu memReq->paddr = thread->copySrcPhysAddr; 2972683Sktlim@umich.edu thread->mem->read(memReq, data); 298595SN/A memReq->paddr = dest_addr; 2992683Sktlim@umich.edu thread->mem->write(memReq, data); 3001098SN/A if (dcacheInterface) { 3011098SN/A memReq->cmd = Copy; 3021098SN/A memReq->completionEvent = NULL; 3032683Sktlim@umich.edu memReq->paddr = thread->copySrcPhysAddr; 3041098SN/A memReq->dest = dest_addr; 3051098SN/A memReq->size = 64; 3061098SN/A memReq->time = curTick; 3071098SN/A dcacheInterface->access(memReq); 3081098SN/A } 309595SN/A } 3102205SN/A else 3112205SN/A assert(!fault->isAlignmentFault()); 3122205SN/A 313595SN/A return fault; 3142390SN/A#else 3152420SN/A panic("copy not implemented"); 3162423SN/A return NoFault; 3172390SN/A#endif 318595SN/A} 319595SN/A 3201858SN/A#if FULL_SYSTEM 3212SN/AAddr 3222623SN/ABaseSimpleCPU::dbg_vtophys(Addr addr) 3232SN/A{ 3242680Sktlim@umich.edu return vtophys(tc, addr); 3252SN/A} 3262SN/A#endif // FULL_SYSTEM 3272SN/A 3281858SN/A#if FULL_SYSTEM 3292SN/Avoid 3305807Snate@binkert.orgBaseSimpleCPU::wakeup() 3312SN/A{ 3325807Snate@binkert.org if (thread->status() != ThreadContext::Suspended) 3335807Snate@binkert.org return; 3342SN/A 3355807Snate@binkert.org DPRINTF(Quiesce,"Suspended Processor awoke\n"); 3365807Snate@binkert.org thread->activate(); 3372SN/A} 3382SN/A#endif // FULL_SYSTEM 3392SN/A 3402SN/Avoid 3412623SN/ABaseSimpleCPU::checkForInterrupts() 3422SN/A{ 3431858SN/A#if FULL_SYSTEM 3445704Snate@binkert.org if (checkInterrupts(tc)) { 3455647Sgblack@eecs.umich.edu Fault interrupt = interrupts->getInterrupt(tc); 3462SN/A 3473520Sgblack@eecs.umich.edu if (interrupt != NoFault) { 3485835Sgblack@eecs.umich.edu predecoder.reset(); 3495647Sgblack@eecs.umich.edu interrupts->updateIntrInfo(tc); 3503520Sgblack@eecs.umich.edu interrupt->invoke(tc); 3512SN/A } 3522SN/A } 3532SN/A#endif 3542623SN/A} 3552SN/A 3562623SN/A 3575894Sgblack@eecs.umich.eduvoid 3582662Sstever@eecs.umich.eduBaseSimpleCPU::setupFetchRequest(Request *req) 3592623SN/A{ 3604514Ssaidi@eecs.umich.edu Addr threadPC = thread->readPC(); 3614495Sacolyte@umich.edu 3622623SN/A // set up memory request for instruction fetch 3633093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 3644495Sacolyte@umich.edu DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC, 3653093Sksewell@umich.edu thread->readNextPC(),thread->readNextNPC()); 3663093Sksewell@umich.edu#else 3674564Sgblack@eecs.umich.edu DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p\n",threadPC, 3682741Sksewell@umich.edu thread->readNextPC()); 3692741Sksewell@umich.edu#endif 3702623SN/A 3714564Sgblack@eecs.umich.edu Addr fetchPC = (threadPC & PCMask) + fetchOffset; 3726105Ssteve.reinhardt@amd.com req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, threadPC); 3732623SN/A} 3742623SN/A 3752623SN/A 3762623SN/Avoid 3772623SN/ABaseSimpleCPU::preExecute() 3782623SN/A{ 3792SN/A // maintain $r0 semantics 3802683Sktlim@umich.edu thread->setIntReg(ZeroReg, 0); 3812427SN/A#if THE_ISA == ALPHA_ISA 3822683Sktlim@umich.edu thread->setFloatReg(ZeroReg, 0.0); 3832427SN/A#endif // ALPHA_ISA 3842SN/A 3852623SN/A // check for instruction-count-based events 3862623SN/A comInstEventQueue[0]->serviceEvents(numInst); 3872SN/A 3882623SN/A // decode the instruction 3892623SN/A inst = gtoh(inst); 3904377Sgblack@eecs.umich.edu 3915665Sgblack@eecs.umich.edu MicroPC upc = thread->readMicroPC(); 3924377Sgblack@eecs.umich.edu 3935665Sgblack@eecs.umich.edu if (isRomMicroPC(upc)) { 3945665Sgblack@eecs.umich.edu stayAtPC = false; 3955665Sgblack@eecs.umich.edu curStaticInst = microcodeRom.fetchMicroop(upc, curMacroStaticInst); 3965665Sgblack@eecs.umich.edu } else if (!curMacroStaticInst) { 3975665Sgblack@eecs.umich.edu //We're not in the middle of a macro instruction 3984181Sgblack@eecs.umich.edu StaticInstPtr instPtr = NULL; 3994181Sgblack@eecs.umich.edu 4004181Sgblack@eecs.umich.edu //Predecode, ie bundle up an ExtMachInst 4014182Sgblack@eecs.umich.edu //This should go away once the constructor can be set up properly 4024182Sgblack@eecs.umich.edu predecoder.setTC(thread->getTC()); 4034182Sgblack@eecs.umich.edu //If more fetch data is needed, pass it in. 4044593Sgblack@eecs.umich.edu Addr fetchPC = (thread->readPC() & PCMask) + fetchOffset; 4054593Sgblack@eecs.umich.edu //if(predecoder.needMoreBytes()) 4064593Sgblack@eecs.umich.edu predecoder.moreBytes(thread->readPC(), fetchPC, inst); 4074593Sgblack@eecs.umich.edu //else 4084593Sgblack@eecs.umich.edu // predecoder.process(); 4094377Sgblack@eecs.umich.edu 4104377Sgblack@eecs.umich.edu //If an instruction is ready, decode it. Otherwise, we'll have to 4114377Sgblack@eecs.umich.edu //fetch beyond the MachInst at the current pc. 4124377Sgblack@eecs.umich.edu if (predecoder.extMachInstReady()) { 4134377Sgblack@eecs.umich.edu#if THE_ISA == X86_ISA 4144377Sgblack@eecs.umich.edu thread->setNextPC(thread->readPC() + predecoder.getInstSize()); 4154377Sgblack@eecs.umich.edu#endif // X86_ISA 4164377Sgblack@eecs.umich.edu stayAtPC = false; 4174572Sacolyte@umich.edu instPtr = StaticInst::decode(predecoder.getExtMachInst(), 4184572Sacolyte@umich.edu thread->readPC()); 4194377Sgblack@eecs.umich.edu } else { 4204377Sgblack@eecs.umich.edu stayAtPC = true; 4214377Sgblack@eecs.umich.edu fetchOffset += sizeof(MachInst); 4224377Sgblack@eecs.umich.edu } 4234181Sgblack@eecs.umich.edu 4244181Sgblack@eecs.umich.edu //If we decoded an instruction and it's microcoded, start pulling 4254181Sgblack@eecs.umich.edu //out micro ops 4264539Sgblack@eecs.umich.edu if (instPtr && instPtr->isMacroop()) { 4273276Sgblack@eecs.umich.edu curMacroStaticInst = instPtr; 4285665Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst->fetchMicroop(upc); 4293280Sgblack@eecs.umich.edu } else { 4303280Sgblack@eecs.umich.edu curStaticInst = instPtr; 4313276Sgblack@eecs.umich.edu } 4323276Sgblack@eecs.umich.edu } else { 4333276Sgblack@eecs.umich.edu //Read the next micro op from the macro op 4345665Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst->fetchMicroop(upc); 4353276Sgblack@eecs.umich.edu } 4363276Sgblack@eecs.umich.edu 4374181Sgblack@eecs.umich.edu //If we decoded an instruction this "tick", record information about it. 4384181Sgblack@eecs.umich.edu if(curStaticInst) 4394181Sgblack@eecs.umich.edu { 4404522Ssaidi@eecs.umich.edu#if TRACING_ON 4415784Sgblack@eecs.umich.edu traceData = tracer->getInstRecord(curTick, tc, 4425784Sgblack@eecs.umich.edu curStaticInst, thread->readPC(), 4435784Sgblack@eecs.umich.edu curMacroStaticInst, thread->readMicroPC()); 4442470SN/A 4454181Sgblack@eecs.umich.edu DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n", 4464181Sgblack@eecs.umich.edu curStaticInst->getName(), curStaticInst->machInst); 4474522Ssaidi@eecs.umich.edu#endif // TRACING_ON 4482623SN/A 4492623SN/A#if FULL_SYSTEM 4504181Sgblack@eecs.umich.edu thread->setInst(inst); 4512623SN/A#endif // FULL_SYSTEM 4524181Sgblack@eecs.umich.edu } 4532623SN/A} 4542623SN/A 4552623SN/Avoid 4562623SN/ABaseSimpleCPU::postExecute() 4572623SN/A{ 4582623SN/A#if FULL_SYSTEM 4595086Sgblack@eecs.umich.edu if (thread->profile && curStaticInst) { 4603577Sgblack@eecs.umich.edu bool usermode = TheISA::inUserMode(tc); 4612683Sktlim@umich.edu thread->profilePC = usermode ? 1 : thread->readPC(); 4625086Sgblack@eecs.umich.edu ProfileNode *node = thread->profile->consume(tc, curStaticInst); 4632623SN/A if (node) 4642683Sktlim@umich.edu thread->profileNode = node; 4652623SN/A } 4662420SN/A#endif 4672SN/A 4682623SN/A if (curStaticInst->isMemRef()) { 4692623SN/A numMemRefs++; 4702SN/A } 4712SN/A 4722623SN/A if (curStaticInst->isLoad()) { 4732623SN/A ++numLoad; 4742623SN/A comLoadEventQueue[0]->serviceEvents(numLoad); 4752623SN/A } 4762SN/A 4775953Ssaidi@eecs.umich.edu if (CPA::available()) { 4785953Ssaidi@eecs.umich.edu CPA::cpa()->swAutoBegin(tc, thread->readNextPC()); 4795953Ssaidi@eecs.umich.edu } 4805953Ssaidi@eecs.umich.edu 4812683Sktlim@umich.edu traceFunctions(thread->readPC()); 4822644Sstever@eecs.umich.edu 4832644Sstever@eecs.umich.edu if (traceData) { 4844046Sbinkertn@umich.edu traceData->dump(); 4854046Sbinkertn@umich.edu delete traceData; 4864046Sbinkertn@umich.edu traceData = NULL; 4872644Sstever@eecs.umich.edu } 4882623SN/A} 4892SN/A 4902SN/A 4912623SN/Avoid 4922623SN/ABaseSimpleCPU::advancePC(Fault fault) 4932623SN/A{ 4944377Sgblack@eecs.umich.edu //Since we're moving to a new pc, zero out the offset 4954377Sgblack@eecs.umich.edu fetchOffset = 0; 4962090SN/A if (fault != NoFault) { 4973905Ssaidi@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 4985120Sgblack@eecs.umich.edu predecoder.reset(); 4995281Sgblack@eecs.umich.edu fault->invoke(tc); 5004377Sgblack@eecs.umich.edu } else { 5013276Sgblack@eecs.umich.edu //If we're at the last micro op for this instruction 5024539Sgblack@eecs.umich.edu if (curStaticInst && curStaticInst->isLastMicroop()) { 5035665Sgblack@eecs.umich.edu //We should be working with a macro op or be in the ROM 5045665Sgblack@eecs.umich.edu assert(curMacroStaticInst || 5055665Sgblack@eecs.umich.edu isRomMicroPC(thread->readMicroPC())); 5063276Sgblack@eecs.umich.edu //Close out this macro op, and clean up the 5073276Sgblack@eecs.umich.edu //microcode state 5083280Sgblack@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 5095665Sgblack@eecs.umich.edu thread->setMicroPC(normalMicroPC(0)); 5105665Sgblack@eecs.umich.edu thread->setNextMicroPC(normalMicroPC(1)); 5113276Sgblack@eecs.umich.edu } 5123276Sgblack@eecs.umich.edu //If we're still in a macro op 5135665Sgblack@eecs.umich.edu if (curMacroStaticInst || isRomMicroPC(thread->readMicroPC())) { 5143276Sgblack@eecs.umich.edu //Advance the micro pc 5153280Sgblack@eecs.umich.edu thread->setMicroPC(thread->readNextMicroPC()); 5163276Sgblack@eecs.umich.edu //Advance the "next" micro pc. Note that there are no delay 5173276Sgblack@eecs.umich.edu //slots, and micro ops are "word" addressed. 5183280Sgblack@eecs.umich.edu thread->setNextMicroPC(thread->readNextMicroPC() + 1); 5193276Sgblack@eecs.umich.edu } else { 5203276Sgblack@eecs.umich.edu // go to the next instruction 5213276Sgblack@eecs.umich.edu thread->setPC(thread->readNextPC()); 5223276Sgblack@eecs.umich.edu thread->setNextPC(thread->readNextNPC()); 5233276Sgblack@eecs.umich.edu thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst)); 5243276Sgblack@eecs.umich.edu assert(thread->readNextPC() != thread->readNextNPC()); 5253276Sgblack@eecs.umich.edu } 5262SN/A } 5272SN/A} 5282SN/A 5295250Sksewell@umich.edu/*Fault 5305222Sksewell@umich.eduBaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr) 5315222Sksewell@umich.edu{ 5325222Sksewell@umich.edu // translate to physical address 5335222Sksewell@umich.edu Fault fault = NoFault; 5345222Sksewell@umich.edu int CacheID = Op & 0x3; // Lower 3 bits identify Cache 5355222Sksewell@umich.edu int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation 5365222Sksewell@umich.edu if(CacheID > 1) 5375222Sksewell@umich.edu { 5385222Sksewell@umich.edu warn("CacheOps not implemented for secondary/tertiary caches\n"); 5395222Sksewell@umich.edu } 5405222Sksewell@umich.edu else 5415222Sksewell@umich.edu { 5425222Sksewell@umich.edu switch(CacheOP) 5435222Sksewell@umich.edu { // Fill Packet Type 5445222Sksewell@umich.edu case 0: warn("Invalidate Cache Op\n"); 5455222Sksewell@umich.edu break; 5465222Sksewell@umich.edu case 1: warn("Index Load Tag Cache Op\n"); 5475222Sksewell@umich.edu break; 5485222Sksewell@umich.edu case 2: warn("Index Store Tag Cache Op\n"); 5495222Sksewell@umich.edu break; 5505222Sksewell@umich.edu case 4: warn("Hit Invalidate Cache Op\n"); 5515222Sksewell@umich.edu break; 5525222Sksewell@umich.edu case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n"); 5535222Sksewell@umich.edu break; 5545222Sksewell@umich.edu case 6: warn("Hit Writeback\n"); 5555222Sksewell@umich.edu break; 5565222Sksewell@umich.edu case 7: warn("Fetch & Lock Cache Op\n"); 5575222Sksewell@umich.edu break; 5585222Sksewell@umich.edu default: warn("Unimplemented Cache Op\n"); 5595222Sksewell@umich.edu } 5605222Sksewell@umich.edu } 5615222Sksewell@umich.edu return fault; 5625250Sksewell@umich.edu}*/ 563