base.cc revision 6105
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292SN/A */ 302SN/A 312439SN/A#include "arch/utility.hh" 322984Sgblack@eecs.umich.edu#include "arch/faults.hh" 33146SN/A#include "base/cprintf.hh" 345953Ssaidi@eecs.umich.edu#include "base/cp_annotate.hh" 35146SN/A#include "base/inifile.hh" 36146SN/A#include "base/loader/symtab.hh" 37146SN/A#include "base/misc.hh" 38146SN/A#include "base/pollevent.hh" 39146SN/A#include "base/range.hh" 401717SN/A#include "base/stats/events.hh" 41146SN/A#include "base/trace.hh" 421717SN/A#include "cpu/base.hh" 43146SN/A#include "cpu/exetrace.hh" 441977SN/A#include "cpu/profile.hh" 452623SN/A#include "cpu/simple/base.hh" 462683Sktlim@umich.edu#include "cpu/simple_thread.hh" 471717SN/A#include "cpu/smt.hh" 48146SN/A#include "cpu/static_inst.hh" 492683Sktlim@umich.edu#include "cpu/thread_context.hh" 503348Sbinkertn@umich.edu#include "mem/packet.hh" 516105Ssteve.reinhardt@amd.com#include "mem/request.hh" 522036SN/A#include "sim/byteswap.hh" 53146SN/A#include "sim/debug.hh" 5456SN/A#include "sim/host.hh" 5556SN/A#include "sim/sim_events.hh" 5656SN/A#include "sim/sim_object.hh" 57695SN/A#include "sim/stats.hh" 582901Ssaidi@eecs.umich.edu#include "sim/system.hh" 592SN/A 601858SN/A#if FULL_SYSTEM 613565Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 623565Sgblack@eecs.umich.edu#include "arch/stacktrace.hh" 632171SN/A#include "arch/tlb.hh" 642170SN/A#include "arch/vtophys.hh" 653562Sgblack@eecs.umich.edu#include "base/remote_gdb.hh" 66146SN/A#else // !FULL_SYSTEM 672462SN/A#include "mem/mem_object.hh" 68146SN/A#endif // FULL_SYSTEM 692SN/A 705529Snate@binkert.org#include "params/BaseSimpleCPU.hh" 715529Snate@binkert.org 722SN/Ausing namespace std; 732449SN/Ausing namespace TheISA; 741355SN/A 755529Snate@binkert.orgBaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p) 764495Sacolyte@umich.edu : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL) 77224SN/A{ 781858SN/A#if FULL_SYSTEM 792683Sktlim@umich.edu thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb); 802420SN/A#else 815529Snate@binkert.org thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0], 824997Sgblack@eecs.umich.edu p->itb, p->dtb, /* asid */ 0); 832420SN/A#endif // !FULL_SYSTEM 842SN/A 856029Ssteve.reinhardt@amd.com thread->setStatus(ThreadContext::Halted); 862672Sktlim@umich.edu 872683Sktlim@umich.edu tc = thread->getTC(); 882SN/A 892SN/A numInst = 0; 90334SN/A startNumInst = 0; 91140SN/A numLoad = 0; 92334SN/A startNumLoad = 0; 932SN/A lastIcacheStall = 0; 942SN/A lastDcacheStall = 0; 952SN/A 962680Sktlim@umich.edu threadContexts.push_back(tc); 974377Sgblack@eecs.umich.edu 985169Ssaidi@eecs.umich.edu 994377Sgblack@eecs.umich.edu fetchOffset = 0; 1004377Sgblack@eecs.umich.edu stayAtPC = false; 1012SN/A} 1022SN/A 1032623SN/ABaseSimpleCPU::~BaseSimpleCPU() 1042SN/A{ 1052SN/A} 1062SN/A 107180SN/Avoid 1082623SN/ABaseSimpleCPU::deallocateContext(int thread_num) 109393SN/A{ 110393SN/A // for now, these are equivalent 111393SN/A suspendContext(thread_num); 112393SN/A} 113384SN/A 114384SN/A 115393SN/Avoid 1162623SN/ABaseSimpleCPU::haltContext(int thread_num) 117393SN/A{ 118393SN/A // for now, these are equivalent 119393SN/A suspendContext(thread_num); 120393SN/A} 121384SN/A 122189SN/A 123189SN/Avoid 1242623SN/ABaseSimpleCPU::regStats() 1252SN/A{ 126729SN/A using namespace Stats; 127334SN/A 1282SN/A BaseCPU::regStats(); 1292SN/A 1302SN/A numInsts 1312SN/A .name(name() + ".num_insts") 1322SN/A .desc("Number of instructions executed") 1332SN/A ; 1342SN/A 1352SN/A numMemRefs 1362SN/A .name(name() + ".num_refs") 1372SN/A .desc("Number of memory references") 1382SN/A ; 1392SN/A 1401001SN/A notIdleFraction 1411001SN/A .name(name() + ".not_idle_fraction") 1421001SN/A .desc("Percentage of non-idle cycles") 1431001SN/A ; 1441001SN/A 1452SN/A idleFraction 1462SN/A .name(name() + ".idle_fraction") 1472SN/A .desc("Percentage of idle cycles") 1482SN/A ; 1492SN/A 1502SN/A icacheStallCycles 1512SN/A .name(name() + ".icache_stall_cycles") 1522SN/A .desc("ICache total stall cycles") 1532SN/A .prereq(icacheStallCycles) 1542SN/A ; 1552SN/A 1562SN/A dcacheStallCycles 1572SN/A .name(name() + ".dcache_stall_cycles") 1582SN/A .desc("DCache total stall cycles") 1592SN/A .prereq(dcacheStallCycles) 1602SN/A ; 1612SN/A 1622390SN/A icacheRetryCycles 1632390SN/A .name(name() + ".icache_retry_cycles") 1642390SN/A .desc("ICache total retry cycles") 1652390SN/A .prereq(icacheRetryCycles) 1662390SN/A ; 1672390SN/A 1682390SN/A dcacheRetryCycles 1692390SN/A .name(name() + ".dcache_retry_cycles") 1702390SN/A .desc("DCache total retry cycles") 1712390SN/A .prereq(dcacheRetryCycles) 1722390SN/A ; 1732390SN/A 174385SN/A idleFraction = constant(1.0) - notIdleFraction; 1752SN/A} 1762SN/A 1772SN/Avoid 1782623SN/ABaseSimpleCPU::resetStats() 179334SN/A{ 1802361SN/A// startNumInst = numInst; 1815496Ssaidi@eecs.umich.edu notIdleFraction = (_status != Idle); 182334SN/A} 183334SN/A 184334SN/Avoid 1852623SN/ABaseSimpleCPU::serialize(ostream &os) 1862SN/A{ 1875496Ssaidi@eecs.umich.edu SERIALIZE_ENUM(_status); 188921SN/A BaseCPU::serialize(os); 1892915Sktlim@umich.edu// SERIALIZE_SCALAR(inst); 1902915Sktlim@umich.edu nameOut(os, csprintf("%s.xc.0", name())); 1912683Sktlim@umich.edu thread->serialize(os); 1922SN/A} 1932SN/A 1942SN/Avoid 1952623SN/ABaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1962SN/A{ 1975496Ssaidi@eecs.umich.edu UNSERIALIZE_ENUM(_status); 198921SN/A BaseCPU::unserialize(cp, section); 1992915Sktlim@umich.edu// UNSERIALIZE_SCALAR(inst); 2002915Sktlim@umich.edu thread->unserialize(cp, csprintf("%s.xc.0", section)); 2012SN/A} 2022SN/A 2032SN/Avoid 2042SN/Achange_thread_state(int thread_number, int activate, int priority) 2052SN/A{ 2062SN/A} 2072SN/A 208595SN/AFault 2092623SN/ABaseSimpleCPU::copySrcTranslate(Addr src) 210595SN/A{ 2112390SN/A#if 0 2121080SN/A static bool no_warn = true; 2131080SN/A int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 2141080SN/A // Only support block sizes of 64 atm. 2151080SN/A assert(blk_size == 64); 2161080SN/A int offset = src & (blk_size - 1); 2171080SN/A 2181080SN/A // Make sure block doesn't span page 2191121SN/A if (no_warn && 2202107SN/A (src & PageMask) != ((src + blk_size) & PageMask) && 2211089SN/A (src >> 40) != 0xfffffc) { 2221089SN/A warn("Copied block source spans pages %x.", src); 2231080SN/A no_warn = false; 2241080SN/A } 2251080SN/A 2261080SN/A memReq->reset(src & ~(blk_size - 1), blk_size); 227595SN/A 2282623SN/A // translate to physical address 2292683Sktlim@umich.edu Fault fault = thread->translateDataReadReq(req); 230595SN/A 2312090SN/A if (fault == NoFault) { 2322683Sktlim@umich.edu thread->copySrcAddr = src; 2332683Sktlim@umich.edu thread->copySrcPhysAddr = memReq->paddr + offset; 234595SN/A } else { 2352205SN/A assert(!fault->isAlignmentFault()); 2362205SN/A 2372683Sktlim@umich.edu thread->copySrcAddr = 0; 2382683Sktlim@umich.edu thread->copySrcPhysAddr = 0; 239595SN/A } 240595SN/A return fault; 2412390SN/A#else 2422423SN/A return NoFault; 2432390SN/A#endif 244595SN/A} 245595SN/A 246595SN/AFault 2472623SN/ABaseSimpleCPU::copy(Addr dest) 248595SN/A{ 2492390SN/A#if 0 2501080SN/A static bool no_warn = true; 251595SN/A int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 2521080SN/A // Only support block sizes of 64 atm. 2531080SN/A assert(blk_size == 64); 254595SN/A uint8_t data[blk_size]; 2552683Sktlim@umich.edu //assert(thread->copySrcAddr); 2561080SN/A int offset = dest & (blk_size - 1); 2571080SN/A 2581080SN/A // Make sure block doesn't span page 2591121SN/A if (no_warn && 2602107SN/A (dest & PageMask) != ((dest + blk_size) & PageMask) && 2611089SN/A (dest >> 40) != 0xfffffc) { 2621080SN/A no_warn = false; 2631089SN/A warn("Copied block destination spans pages %x. ", dest); 2641080SN/A } 2651080SN/A 2661080SN/A memReq->reset(dest & ~(blk_size -1), blk_size); 267595SN/A // translate to physical address 2682683Sktlim@umich.edu Fault fault = thread->translateDataWriteReq(req); 2691080SN/A 2702090SN/A if (fault == NoFault) { 2711080SN/A Addr dest_addr = memReq->paddr + offset; 272595SN/A // Need to read straight from memory since we have more than 8 bytes. 2732683Sktlim@umich.edu memReq->paddr = thread->copySrcPhysAddr; 2742683Sktlim@umich.edu thread->mem->read(memReq, data); 275595SN/A memReq->paddr = dest_addr; 2762683Sktlim@umich.edu thread->mem->write(memReq, data); 2771098SN/A if (dcacheInterface) { 2781098SN/A memReq->cmd = Copy; 2791098SN/A memReq->completionEvent = NULL; 2802683Sktlim@umich.edu memReq->paddr = thread->copySrcPhysAddr; 2811098SN/A memReq->dest = dest_addr; 2821098SN/A memReq->size = 64; 2831098SN/A memReq->time = curTick; 2846105Ssteve.reinhardt@amd.com memReq->flags &= ~INST_FETCH; 2851098SN/A dcacheInterface->access(memReq); 2861098SN/A } 287595SN/A } 2882205SN/A else 2892205SN/A assert(!fault->isAlignmentFault()); 2902205SN/A 291595SN/A return fault; 2922390SN/A#else 2932420SN/A panic("copy not implemented"); 2942423SN/A return NoFault; 2952390SN/A#endif 296595SN/A} 297595SN/A 2981858SN/A#if FULL_SYSTEM 2992SN/AAddr 3002623SN/ABaseSimpleCPU::dbg_vtophys(Addr addr) 3012SN/A{ 3022680Sktlim@umich.edu return vtophys(tc, addr); 3032SN/A} 3042SN/A#endif // FULL_SYSTEM 3052SN/A 3061858SN/A#if FULL_SYSTEM 3072SN/Avoid 3085807Snate@binkert.orgBaseSimpleCPU::wakeup() 3092SN/A{ 3105807Snate@binkert.org if (thread->status() != ThreadContext::Suspended) 3115807Snate@binkert.org return; 3122SN/A 3135807Snate@binkert.org DPRINTF(Quiesce,"Suspended Processor awoke\n"); 3145807Snate@binkert.org thread->activate(); 3152SN/A} 3162SN/A#endif // FULL_SYSTEM 3172SN/A 3182SN/Avoid 3192623SN/ABaseSimpleCPU::checkForInterrupts() 3202SN/A{ 3211858SN/A#if FULL_SYSTEM 3225704Snate@binkert.org if (checkInterrupts(tc)) { 3235647Sgblack@eecs.umich.edu Fault interrupt = interrupts->getInterrupt(tc); 3242SN/A 3253520Sgblack@eecs.umich.edu if (interrupt != NoFault) { 3265835Sgblack@eecs.umich.edu predecoder.reset(); 3275647Sgblack@eecs.umich.edu interrupts->updateIntrInfo(tc); 3283520Sgblack@eecs.umich.edu interrupt->invoke(tc); 3292SN/A } 3302SN/A } 3312SN/A#endif 3322623SN/A} 3332SN/A 3342623SN/A 3355894Sgblack@eecs.umich.eduvoid 3362662Sstever@eecs.umich.eduBaseSimpleCPU::setupFetchRequest(Request *req) 3372623SN/A{ 3384514Ssaidi@eecs.umich.edu Addr threadPC = thread->readPC(); 3394495Sacolyte@umich.edu 3402623SN/A // set up memory request for instruction fetch 3413093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 3424495Sacolyte@umich.edu DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC, 3433093Sksewell@umich.edu thread->readNextPC(),thread->readNextNPC()); 3443093Sksewell@umich.edu#else 3454564Sgblack@eecs.umich.edu DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p\n",threadPC, 3462741Sksewell@umich.edu thread->readNextPC()); 3472741Sksewell@umich.edu#endif 3482623SN/A 3494564Sgblack@eecs.umich.edu Addr fetchPC = (threadPC & PCMask) + fetchOffset; 3506105Ssteve.reinhardt@amd.com req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, threadPC); 3512623SN/A} 3522623SN/A 3532623SN/A 3542623SN/Avoid 3552623SN/ABaseSimpleCPU::preExecute() 3562623SN/A{ 3572SN/A // maintain $r0 semantics 3582683Sktlim@umich.edu thread->setIntReg(ZeroReg, 0); 3592427SN/A#if THE_ISA == ALPHA_ISA 3602683Sktlim@umich.edu thread->setFloatReg(ZeroReg, 0.0); 3612427SN/A#endif // ALPHA_ISA 3622SN/A 3632623SN/A // check for instruction-count-based events 3642623SN/A comInstEventQueue[0]->serviceEvents(numInst); 3652SN/A 3662623SN/A // decode the instruction 3672623SN/A inst = gtoh(inst); 3684377Sgblack@eecs.umich.edu 3695665Sgblack@eecs.umich.edu MicroPC upc = thread->readMicroPC(); 3704377Sgblack@eecs.umich.edu 3715665Sgblack@eecs.umich.edu if (isRomMicroPC(upc)) { 3725665Sgblack@eecs.umich.edu stayAtPC = false; 3735665Sgblack@eecs.umich.edu curStaticInst = microcodeRom.fetchMicroop(upc, curMacroStaticInst); 3745665Sgblack@eecs.umich.edu } else if (!curMacroStaticInst) { 3755665Sgblack@eecs.umich.edu //We're not in the middle of a macro instruction 3764181Sgblack@eecs.umich.edu StaticInstPtr instPtr = NULL; 3774181Sgblack@eecs.umich.edu 3784181Sgblack@eecs.umich.edu //Predecode, ie bundle up an ExtMachInst 3794182Sgblack@eecs.umich.edu //This should go away once the constructor can be set up properly 3804182Sgblack@eecs.umich.edu predecoder.setTC(thread->getTC()); 3814182Sgblack@eecs.umich.edu //If more fetch data is needed, pass it in. 3824593Sgblack@eecs.umich.edu Addr fetchPC = (thread->readPC() & PCMask) + fetchOffset; 3834593Sgblack@eecs.umich.edu //if(predecoder.needMoreBytes()) 3844593Sgblack@eecs.umich.edu predecoder.moreBytes(thread->readPC(), fetchPC, inst); 3854593Sgblack@eecs.umich.edu //else 3864593Sgblack@eecs.umich.edu // predecoder.process(); 3874377Sgblack@eecs.umich.edu 3884377Sgblack@eecs.umich.edu //If an instruction is ready, decode it. Otherwise, we'll have to 3894377Sgblack@eecs.umich.edu //fetch beyond the MachInst at the current pc. 3904377Sgblack@eecs.umich.edu if (predecoder.extMachInstReady()) { 3914377Sgblack@eecs.umich.edu#if THE_ISA == X86_ISA 3924377Sgblack@eecs.umich.edu thread->setNextPC(thread->readPC() + predecoder.getInstSize()); 3934377Sgblack@eecs.umich.edu#endif // X86_ISA 3944377Sgblack@eecs.umich.edu stayAtPC = false; 3954572Sacolyte@umich.edu instPtr = StaticInst::decode(predecoder.getExtMachInst(), 3964572Sacolyte@umich.edu thread->readPC()); 3974377Sgblack@eecs.umich.edu } else { 3984377Sgblack@eecs.umich.edu stayAtPC = true; 3994377Sgblack@eecs.umich.edu fetchOffset += sizeof(MachInst); 4004377Sgblack@eecs.umich.edu } 4014181Sgblack@eecs.umich.edu 4024181Sgblack@eecs.umich.edu //If we decoded an instruction and it's microcoded, start pulling 4034181Sgblack@eecs.umich.edu //out micro ops 4044539Sgblack@eecs.umich.edu if (instPtr && instPtr->isMacroop()) { 4053276Sgblack@eecs.umich.edu curMacroStaticInst = instPtr; 4065665Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst->fetchMicroop(upc); 4073280Sgblack@eecs.umich.edu } else { 4083280Sgblack@eecs.umich.edu curStaticInst = instPtr; 4093276Sgblack@eecs.umich.edu } 4103276Sgblack@eecs.umich.edu } else { 4113276Sgblack@eecs.umich.edu //Read the next micro op from the macro op 4125665Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst->fetchMicroop(upc); 4133276Sgblack@eecs.umich.edu } 4143276Sgblack@eecs.umich.edu 4154181Sgblack@eecs.umich.edu //If we decoded an instruction this "tick", record information about it. 4164181Sgblack@eecs.umich.edu if(curStaticInst) 4174181Sgblack@eecs.umich.edu { 4184522Ssaidi@eecs.umich.edu#if TRACING_ON 4195784Sgblack@eecs.umich.edu traceData = tracer->getInstRecord(curTick, tc, 4205784Sgblack@eecs.umich.edu curStaticInst, thread->readPC(), 4215784Sgblack@eecs.umich.edu curMacroStaticInst, thread->readMicroPC()); 4222470SN/A 4234181Sgblack@eecs.umich.edu DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n", 4244181Sgblack@eecs.umich.edu curStaticInst->getName(), curStaticInst->machInst); 4254522Ssaidi@eecs.umich.edu#endif // TRACING_ON 4262623SN/A 4272623SN/A#if FULL_SYSTEM 4284181Sgblack@eecs.umich.edu thread->setInst(inst); 4292623SN/A#endif // FULL_SYSTEM 4304181Sgblack@eecs.umich.edu } 4312623SN/A} 4322623SN/A 4332623SN/Avoid 4342623SN/ABaseSimpleCPU::postExecute() 4352623SN/A{ 4362623SN/A#if FULL_SYSTEM 4375086Sgblack@eecs.umich.edu if (thread->profile && curStaticInst) { 4383577Sgblack@eecs.umich.edu bool usermode = TheISA::inUserMode(tc); 4392683Sktlim@umich.edu thread->profilePC = usermode ? 1 : thread->readPC(); 4405086Sgblack@eecs.umich.edu ProfileNode *node = thread->profile->consume(tc, curStaticInst); 4412623SN/A if (node) 4422683Sktlim@umich.edu thread->profileNode = node; 4432623SN/A } 4442420SN/A#endif 4452SN/A 4462623SN/A if (curStaticInst->isMemRef()) { 4472623SN/A numMemRefs++; 4482SN/A } 4492SN/A 4502623SN/A if (curStaticInst->isLoad()) { 4512623SN/A ++numLoad; 4522623SN/A comLoadEventQueue[0]->serviceEvents(numLoad); 4532623SN/A } 4542SN/A 4555953Ssaidi@eecs.umich.edu if (CPA::available()) { 4565953Ssaidi@eecs.umich.edu CPA::cpa()->swAutoBegin(tc, thread->readNextPC()); 4575953Ssaidi@eecs.umich.edu } 4585953Ssaidi@eecs.umich.edu 4592683Sktlim@umich.edu traceFunctions(thread->readPC()); 4602644Sstever@eecs.umich.edu 4612644Sstever@eecs.umich.edu if (traceData) { 4624046Sbinkertn@umich.edu traceData->dump(); 4634046Sbinkertn@umich.edu delete traceData; 4644046Sbinkertn@umich.edu traceData = NULL; 4652644Sstever@eecs.umich.edu } 4662623SN/A} 4672SN/A 4682SN/A 4692623SN/Avoid 4702623SN/ABaseSimpleCPU::advancePC(Fault fault) 4712623SN/A{ 4724377Sgblack@eecs.umich.edu //Since we're moving to a new pc, zero out the offset 4734377Sgblack@eecs.umich.edu fetchOffset = 0; 4742090SN/A if (fault != NoFault) { 4753905Ssaidi@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 4765120Sgblack@eecs.umich.edu predecoder.reset(); 4775281Sgblack@eecs.umich.edu fault->invoke(tc); 4784377Sgblack@eecs.umich.edu } else { 4793276Sgblack@eecs.umich.edu //If we're at the last micro op for this instruction 4804539Sgblack@eecs.umich.edu if (curStaticInst && curStaticInst->isLastMicroop()) { 4815665Sgblack@eecs.umich.edu //We should be working with a macro op or be in the ROM 4825665Sgblack@eecs.umich.edu assert(curMacroStaticInst || 4835665Sgblack@eecs.umich.edu isRomMicroPC(thread->readMicroPC())); 4843276Sgblack@eecs.umich.edu //Close out this macro op, and clean up the 4853276Sgblack@eecs.umich.edu //microcode state 4863280Sgblack@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 4875665Sgblack@eecs.umich.edu thread->setMicroPC(normalMicroPC(0)); 4885665Sgblack@eecs.umich.edu thread->setNextMicroPC(normalMicroPC(1)); 4893276Sgblack@eecs.umich.edu } 4903276Sgblack@eecs.umich.edu //If we're still in a macro op 4915665Sgblack@eecs.umich.edu if (curMacroStaticInst || isRomMicroPC(thread->readMicroPC())) { 4923276Sgblack@eecs.umich.edu //Advance the micro pc 4933280Sgblack@eecs.umich.edu thread->setMicroPC(thread->readNextMicroPC()); 4943276Sgblack@eecs.umich.edu //Advance the "next" micro pc. Note that there are no delay 4953276Sgblack@eecs.umich.edu //slots, and micro ops are "word" addressed. 4963280Sgblack@eecs.umich.edu thread->setNextMicroPC(thread->readNextMicroPC() + 1); 4973276Sgblack@eecs.umich.edu } else { 4983276Sgblack@eecs.umich.edu // go to the next instruction 4993276Sgblack@eecs.umich.edu thread->setPC(thread->readNextPC()); 5003276Sgblack@eecs.umich.edu thread->setNextPC(thread->readNextNPC()); 5013276Sgblack@eecs.umich.edu thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst)); 5023276Sgblack@eecs.umich.edu assert(thread->readNextPC() != thread->readNextNPC()); 5033276Sgblack@eecs.umich.edu } 5042SN/A } 5052SN/A} 5062SN/A 5075250Sksewell@umich.edu/*Fault 5085222Sksewell@umich.eduBaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr) 5095222Sksewell@umich.edu{ 5105222Sksewell@umich.edu // translate to physical address 5115222Sksewell@umich.edu Fault fault = NoFault; 5125222Sksewell@umich.edu int CacheID = Op & 0x3; // Lower 3 bits identify Cache 5135222Sksewell@umich.edu int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation 5145222Sksewell@umich.edu if(CacheID > 1) 5155222Sksewell@umich.edu { 5165222Sksewell@umich.edu warn("CacheOps not implemented for secondary/tertiary caches\n"); 5175222Sksewell@umich.edu } 5185222Sksewell@umich.edu else 5195222Sksewell@umich.edu { 5205222Sksewell@umich.edu switch(CacheOP) 5215222Sksewell@umich.edu { // Fill Packet Type 5225222Sksewell@umich.edu case 0: warn("Invalidate Cache Op\n"); 5235222Sksewell@umich.edu break; 5245222Sksewell@umich.edu case 1: warn("Index Load Tag Cache Op\n"); 5255222Sksewell@umich.edu break; 5265222Sksewell@umich.edu case 2: warn("Index Store Tag Cache Op\n"); 5275222Sksewell@umich.edu break; 5285222Sksewell@umich.edu case 4: warn("Hit Invalidate Cache Op\n"); 5295222Sksewell@umich.edu break; 5305222Sksewell@umich.edu case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n"); 5315222Sksewell@umich.edu break; 5325222Sksewell@umich.edu case 6: warn("Hit Writeback\n"); 5335222Sksewell@umich.edu break; 5345222Sksewell@umich.edu case 7: warn("Fetch & Lock Cache Op\n"); 5355222Sksewell@umich.edu break; 5365222Sksewell@umich.edu default: warn("Unimplemented Cache Op\n"); 5375222Sksewell@umich.edu } 5385222Sksewell@umich.edu } 5395222Sksewell@umich.edu return fault; 5405250Sksewell@umich.edu}*/ 541