base.cc revision 5784
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292SN/A */ 302SN/A 312439SN/A#include "arch/utility.hh" 322984Sgblack@eecs.umich.edu#include "arch/faults.hh" 33146SN/A#include "base/cprintf.hh" 34146SN/A#include "base/inifile.hh" 35146SN/A#include "base/loader/symtab.hh" 36146SN/A#include "base/misc.hh" 37146SN/A#include "base/pollevent.hh" 38146SN/A#include "base/range.hh" 391717SN/A#include "base/stats/events.hh" 40146SN/A#include "base/trace.hh" 411717SN/A#include "cpu/base.hh" 42146SN/A#include "cpu/exetrace.hh" 431977SN/A#include "cpu/profile.hh" 442623SN/A#include "cpu/simple/base.hh" 452683Sktlim@umich.edu#include "cpu/simple_thread.hh" 461717SN/A#include "cpu/smt.hh" 47146SN/A#include "cpu/static_inst.hh" 482683Sktlim@umich.edu#include "cpu/thread_context.hh" 493348Sbinkertn@umich.edu#include "mem/packet.hh" 502036SN/A#include "sim/byteswap.hh" 51146SN/A#include "sim/debug.hh" 5256SN/A#include "sim/host.hh" 5356SN/A#include "sim/sim_events.hh" 5456SN/A#include "sim/sim_object.hh" 55695SN/A#include "sim/stats.hh" 562901Ssaidi@eecs.umich.edu#include "sim/system.hh" 572SN/A 581858SN/A#if FULL_SYSTEM 593565Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 603565Sgblack@eecs.umich.edu#include "arch/stacktrace.hh" 612171SN/A#include "arch/tlb.hh" 622170SN/A#include "arch/vtophys.hh" 633562Sgblack@eecs.umich.edu#include "base/remote_gdb.hh" 64146SN/A#else // !FULL_SYSTEM 652462SN/A#include "mem/mem_object.hh" 66146SN/A#endif // FULL_SYSTEM 672SN/A 685529Snate@binkert.org#include "params/BaseSimpleCPU.hh" 695529Snate@binkert.org 702SN/Ausing namespace std; 712449SN/Ausing namespace TheISA; 721355SN/A 735529Snate@binkert.orgBaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p) 744495Sacolyte@umich.edu : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL) 75224SN/A{ 761858SN/A#if FULL_SYSTEM 772683Sktlim@umich.edu thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb); 782420SN/A#else 795529Snate@binkert.org thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0], 804997Sgblack@eecs.umich.edu p->itb, p->dtb, /* asid */ 0); 812420SN/A#endif // !FULL_SYSTEM 822SN/A 834400Srdreslin@umich.edu thread->setStatus(ThreadContext::Unallocated); 842672Sktlim@umich.edu 852683Sktlim@umich.edu tc = thread->getTC(); 862SN/A 872SN/A numInst = 0; 88334SN/A startNumInst = 0; 89140SN/A numLoad = 0; 90334SN/A startNumLoad = 0; 912SN/A lastIcacheStall = 0; 922SN/A lastDcacheStall = 0; 932SN/A 942680Sktlim@umich.edu threadContexts.push_back(tc); 954377Sgblack@eecs.umich.edu 965169Ssaidi@eecs.umich.edu 974377Sgblack@eecs.umich.edu fetchOffset = 0; 984377Sgblack@eecs.umich.edu stayAtPC = false; 992SN/A} 1002SN/A 1012623SN/ABaseSimpleCPU::~BaseSimpleCPU() 1022SN/A{ 1032SN/A} 1042SN/A 105180SN/Avoid 1062623SN/ABaseSimpleCPU::deallocateContext(int thread_num) 107393SN/A{ 108393SN/A // for now, these are equivalent 109393SN/A suspendContext(thread_num); 110393SN/A} 111384SN/A 112384SN/A 113393SN/Avoid 1142623SN/ABaseSimpleCPU::haltContext(int thread_num) 115393SN/A{ 116393SN/A // for now, these are equivalent 117393SN/A suspendContext(thread_num); 118393SN/A} 119384SN/A 120189SN/A 121189SN/Avoid 1222623SN/ABaseSimpleCPU::regStats() 1232SN/A{ 124729SN/A using namespace Stats; 125334SN/A 1262SN/A BaseCPU::regStats(); 1272SN/A 1282SN/A numInsts 1292SN/A .name(name() + ".num_insts") 1302SN/A .desc("Number of instructions executed") 1312SN/A ; 1322SN/A 1332SN/A numMemRefs 1342SN/A .name(name() + ".num_refs") 1352SN/A .desc("Number of memory references") 1362SN/A ; 1372SN/A 1381001SN/A notIdleFraction 1391001SN/A .name(name() + ".not_idle_fraction") 1401001SN/A .desc("Percentage of non-idle cycles") 1411001SN/A ; 1421001SN/A 1432SN/A idleFraction 1442SN/A .name(name() + ".idle_fraction") 1452SN/A .desc("Percentage of idle cycles") 1462SN/A ; 1472SN/A 1482SN/A icacheStallCycles 1492SN/A .name(name() + ".icache_stall_cycles") 1502SN/A .desc("ICache total stall cycles") 1512SN/A .prereq(icacheStallCycles) 1522SN/A ; 1532SN/A 1542SN/A dcacheStallCycles 1552SN/A .name(name() + ".dcache_stall_cycles") 1562SN/A .desc("DCache total stall cycles") 1572SN/A .prereq(dcacheStallCycles) 1582SN/A ; 1592SN/A 1602390SN/A icacheRetryCycles 1612390SN/A .name(name() + ".icache_retry_cycles") 1622390SN/A .desc("ICache total retry cycles") 1632390SN/A .prereq(icacheRetryCycles) 1642390SN/A ; 1652390SN/A 1662390SN/A dcacheRetryCycles 1672390SN/A .name(name() + ".dcache_retry_cycles") 1682390SN/A .desc("DCache total retry cycles") 1692390SN/A .prereq(dcacheRetryCycles) 1702390SN/A ; 1712390SN/A 172385SN/A idleFraction = constant(1.0) - notIdleFraction; 1732SN/A} 1742SN/A 1752SN/Avoid 1762623SN/ABaseSimpleCPU::resetStats() 177334SN/A{ 1782361SN/A// startNumInst = numInst; 1795496Ssaidi@eecs.umich.edu notIdleFraction = (_status != Idle); 180334SN/A} 181334SN/A 182334SN/Avoid 1832623SN/ABaseSimpleCPU::serialize(ostream &os) 1842SN/A{ 1855496Ssaidi@eecs.umich.edu SERIALIZE_ENUM(_status); 186921SN/A BaseCPU::serialize(os); 1872915Sktlim@umich.edu// SERIALIZE_SCALAR(inst); 1882915Sktlim@umich.edu nameOut(os, csprintf("%s.xc.0", name())); 1892683Sktlim@umich.edu thread->serialize(os); 1902SN/A} 1912SN/A 1922SN/Avoid 1932623SN/ABaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1942SN/A{ 1955496Ssaidi@eecs.umich.edu UNSERIALIZE_ENUM(_status); 196921SN/A BaseCPU::unserialize(cp, section); 1972915Sktlim@umich.edu// UNSERIALIZE_SCALAR(inst); 1982915Sktlim@umich.edu thread->unserialize(cp, csprintf("%s.xc.0", section)); 1992SN/A} 2002SN/A 2012SN/Avoid 2022SN/Achange_thread_state(int thread_number, int activate, int priority) 2032SN/A{ 2042SN/A} 2052SN/A 206595SN/AFault 2072623SN/ABaseSimpleCPU::copySrcTranslate(Addr src) 208595SN/A{ 2092390SN/A#if 0 2101080SN/A static bool no_warn = true; 2111080SN/A int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 2121080SN/A // Only support block sizes of 64 atm. 2131080SN/A assert(blk_size == 64); 2141080SN/A int offset = src & (blk_size - 1); 2151080SN/A 2161080SN/A // Make sure block doesn't span page 2171121SN/A if (no_warn && 2182107SN/A (src & PageMask) != ((src + blk_size) & PageMask) && 2191089SN/A (src >> 40) != 0xfffffc) { 2201089SN/A warn("Copied block source spans pages %x.", src); 2211080SN/A no_warn = false; 2221080SN/A } 2231080SN/A 2241080SN/A memReq->reset(src & ~(blk_size - 1), blk_size); 225595SN/A 2262623SN/A // translate to physical address 2272683Sktlim@umich.edu Fault fault = thread->translateDataReadReq(req); 228595SN/A 2292090SN/A if (fault == NoFault) { 2302683Sktlim@umich.edu thread->copySrcAddr = src; 2312683Sktlim@umich.edu thread->copySrcPhysAddr = memReq->paddr + offset; 232595SN/A } else { 2332205SN/A assert(!fault->isAlignmentFault()); 2342205SN/A 2352683Sktlim@umich.edu thread->copySrcAddr = 0; 2362683Sktlim@umich.edu thread->copySrcPhysAddr = 0; 237595SN/A } 238595SN/A return fault; 2392390SN/A#else 2402423SN/A return NoFault; 2412390SN/A#endif 242595SN/A} 243595SN/A 244595SN/AFault 2452623SN/ABaseSimpleCPU::copy(Addr dest) 246595SN/A{ 2472390SN/A#if 0 2481080SN/A static bool no_warn = true; 249595SN/A int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 2501080SN/A // Only support block sizes of 64 atm. 2511080SN/A assert(blk_size == 64); 252595SN/A uint8_t data[blk_size]; 2532683Sktlim@umich.edu //assert(thread->copySrcAddr); 2541080SN/A int offset = dest & (blk_size - 1); 2551080SN/A 2561080SN/A // Make sure block doesn't span page 2571121SN/A if (no_warn && 2582107SN/A (dest & PageMask) != ((dest + blk_size) & PageMask) && 2591089SN/A (dest >> 40) != 0xfffffc) { 2601080SN/A no_warn = false; 2611089SN/A warn("Copied block destination spans pages %x. ", dest); 2621080SN/A } 2631080SN/A 2641080SN/A memReq->reset(dest & ~(blk_size -1), blk_size); 265595SN/A // translate to physical address 2662683Sktlim@umich.edu Fault fault = thread->translateDataWriteReq(req); 2671080SN/A 2682090SN/A if (fault == NoFault) { 2691080SN/A Addr dest_addr = memReq->paddr + offset; 270595SN/A // Need to read straight from memory since we have more than 8 bytes. 2712683Sktlim@umich.edu memReq->paddr = thread->copySrcPhysAddr; 2722683Sktlim@umich.edu thread->mem->read(memReq, data); 273595SN/A memReq->paddr = dest_addr; 2742683Sktlim@umich.edu thread->mem->write(memReq, data); 2751098SN/A if (dcacheInterface) { 2761098SN/A memReq->cmd = Copy; 2771098SN/A memReq->completionEvent = NULL; 2782683Sktlim@umich.edu memReq->paddr = thread->copySrcPhysAddr; 2791098SN/A memReq->dest = dest_addr; 2801098SN/A memReq->size = 64; 2811098SN/A memReq->time = curTick; 2822012SN/A memReq->flags &= ~INST_READ; 2831098SN/A dcacheInterface->access(memReq); 2841098SN/A } 285595SN/A } 2862205SN/A else 2872205SN/A assert(!fault->isAlignmentFault()); 2882205SN/A 289595SN/A return fault; 2902390SN/A#else 2912420SN/A panic("copy not implemented"); 2922423SN/A return NoFault; 2932390SN/A#endif 294595SN/A} 295595SN/A 2961858SN/A#if FULL_SYSTEM 2972SN/AAddr 2982623SN/ABaseSimpleCPU::dbg_vtophys(Addr addr) 2992SN/A{ 3002680Sktlim@umich.edu return vtophys(tc, addr); 3012SN/A} 3022SN/A#endif // FULL_SYSTEM 3032SN/A 3041858SN/A#if FULL_SYSTEM 3052SN/Avoid 3065704Snate@binkert.orgBaseSimpleCPU::postInterrupt(int int_num, int index) 3072SN/A{ 3085704Snate@binkert.org BaseCPU::postInterrupt(int_num, index); 3092SN/A 3102683Sktlim@umich.edu if (thread->status() == ThreadContext::Suspended) { 3114216Ssaidi@eecs.umich.edu DPRINTF(Quiesce,"Suspended Processor awoke\n"); 3122683Sktlim@umich.edu thread->activate(); 3132SN/A } 3142SN/A} 3152SN/A#endif // FULL_SYSTEM 3162SN/A 3172SN/Avoid 3182623SN/ABaseSimpleCPU::checkForInterrupts() 3192SN/A{ 3201858SN/A#if FULL_SYSTEM 3215704Snate@binkert.org if (checkInterrupts(tc)) { 3225647Sgblack@eecs.umich.edu Fault interrupt = interrupts->getInterrupt(tc); 3232SN/A 3243520Sgblack@eecs.umich.edu if (interrupt != NoFault) { 3255647Sgblack@eecs.umich.edu interrupts->updateIntrInfo(tc); 3263520Sgblack@eecs.umich.edu interrupt->invoke(tc); 3272SN/A } 3282SN/A } 3292SN/A#endif 3302623SN/A} 3312SN/A 3322623SN/A 3332623SN/AFault 3342662Sstever@eecs.umich.eduBaseSimpleCPU::setupFetchRequest(Request *req) 3352623SN/A{ 3364514Ssaidi@eecs.umich.edu Addr threadPC = thread->readPC(); 3374495Sacolyte@umich.edu 3382623SN/A // set up memory request for instruction fetch 3393093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 3404495Sacolyte@umich.edu DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC, 3413093Sksewell@umich.edu thread->readNextPC(),thread->readNextNPC()); 3423093Sksewell@umich.edu#else 3434564Sgblack@eecs.umich.edu DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p\n",threadPC, 3442741Sksewell@umich.edu thread->readNextPC()); 3452741Sksewell@umich.edu#endif 3462623SN/A 3474564Sgblack@eecs.umich.edu Addr fetchPC = (threadPC & PCMask) + fetchOffset; 3484564Sgblack@eecs.umich.edu req->setVirt(0, fetchPC, sizeof(MachInst), 0, threadPC); 3492623SN/A 3502683Sktlim@umich.edu Fault fault = thread->translateInstReq(req); 3512623SN/A 3522623SN/A return fault; 3532623SN/A} 3542623SN/A 3552623SN/A 3562623SN/Avoid 3572623SN/ABaseSimpleCPU::preExecute() 3582623SN/A{ 3592SN/A // maintain $r0 semantics 3602683Sktlim@umich.edu thread->setIntReg(ZeroReg, 0); 3612427SN/A#if THE_ISA == ALPHA_ISA 3622683Sktlim@umich.edu thread->setFloatReg(ZeroReg, 0.0); 3632427SN/A#endif // ALPHA_ISA 3642SN/A 3652623SN/A // check for instruction-count-based events 3662623SN/A comInstEventQueue[0]->serviceEvents(numInst); 3672SN/A 3682623SN/A // decode the instruction 3692623SN/A inst = gtoh(inst); 3704377Sgblack@eecs.umich.edu 3715665Sgblack@eecs.umich.edu MicroPC upc = thread->readMicroPC(); 3724377Sgblack@eecs.umich.edu 3735665Sgblack@eecs.umich.edu if (isRomMicroPC(upc)) { 3745665Sgblack@eecs.umich.edu stayAtPC = false; 3755665Sgblack@eecs.umich.edu curStaticInst = microcodeRom.fetchMicroop(upc, curMacroStaticInst); 3765665Sgblack@eecs.umich.edu } else if (!curMacroStaticInst) { 3775665Sgblack@eecs.umich.edu //We're not in the middle of a macro instruction 3784181Sgblack@eecs.umich.edu StaticInstPtr instPtr = NULL; 3794181Sgblack@eecs.umich.edu 3804181Sgblack@eecs.umich.edu //Predecode, ie bundle up an ExtMachInst 3814182Sgblack@eecs.umich.edu //This should go away once the constructor can be set up properly 3824182Sgblack@eecs.umich.edu predecoder.setTC(thread->getTC()); 3834182Sgblack@eecs.umich.edu //If more fetch data is needed, pass it in. 3844593Sgblack@eecs.umich.edu Addr fetchPC = (thread->readPC() & PCMask) + fetchOffset; 3854593Sgblack@eecs.umich.edu //if(predecoder.needMoreBytes()) 3864593Sgblack@eecs.umich.edu predecoder.moreBytes(thread->readPC(), fetchPC, inst); 3874593Sgblack@eecs.umich.edu //else 3884593Sgblack@eecs.umich.edu // predecoder.process(); 3894377Sgblack@eecs.umich.edu 3904377Sgblack@eecs.umich.edu //If an instruction is ready, decode it. Otherwise, we'll have to 3914377Sgblack@eecs.umich.edu //fetch beyond the MachInst at the current pc. 3924377Sgblack@eecs.umich.edu if (predecoder.extMachInstReady()) { 3934377Sgblack@eecs.umich.edu#if THE_ISA == X86_ISA 3944377Sgblack@eecs.umich.edu thread->setNextPC(thread->readPC() + predecoder.getInstSize()); 3954377Sgblack@eecs.umich.edu#endif // X86_ISA 3964377Sgblack@eecs.umich.edu stayAtPC = false; 3974572Sacolyte@umich.edu instPtr = StaticInst::decode(predecoder.getExtMachInst(), 3984572Sacolyte@umich.edu thread->readPC()); 3994377Sgblack@eecs.umich.edu } else { 4004377Sgblack@eecs.umich.edu stayAtPC = true; 4014377Sgblack@eecs.umich.edu fetchOffset += sizeof(MachInst); 4024377Sgblack@eecs.umich.edu } 4034181Sgblack@eecs.umich.edu 4044181Sgblack@eecs.umich.edu //If we decoded an instruction and it's microcoded, start pulling 4054181Sgblack@eecs.umich.edu //out micro ops 4064539Sgblack@eecs.umich.edu if (instPtr && instPtr->isMacroop()) { 4073276Sgblack@eecs.umich.edu curMacroStaticInst = instPtr; 4085665Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst->fetchMicroop(upc); 4093280Sgblack@eecs.umich.edu } else { 4103280Sgblack@eecs.umich.edu curStaticInst = instPtr; 4113276Sgblack@eecs.umich.edu } 4123276Sgblack@eecs.umich.edu } else { 4133276Sgblack@eecs.umich.edu //Read the next micro op from the macro op 4145665Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst->fetchMicroop(upc); 4153276Sgblack@eecs.umich.edu } 4163276Sgblack@eecs.umich.edu 4174181Sgblack@eecs.umich.edu //If we decoded an instruction this "tick", record information about it. 4184181Sgblack@eecs.umich.edu if(curStaticInst) 4194181Sgblack@eecs.umich.edu { 4204522Ssaidi@eecs.umich.edu#if TRACING_ON 4215784Sgblack@eecs.umich.edu traceData = tracer->getInstRecord(curTick, tc, 4225784Sgblack@eecs.umich.edu curStaticInst, thread->readPC(), 4235784Sgblack@eecs.umich.edu curMacroStaticInst, thread->readMicroPC()); 4242470SN/A 4254181Sgblack@eecs.umich.edu DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n", 4264181Sgblack@eecs.umich.edu curStaticInst->getName(), curStaticInst->machInst); 4274522Ssaidi@eecs.umich.edu#endif // TRACING_ON 4282623SN/A 4292623SN/A#if FULL_SYSTEM 4304181Sgblack@eecs.umich.edu thread->setInst(inst); 4312623SN/A#endif // FULL_SYSTEM 4324181Sgblack@eecs.umich.edu } 4332623SN/A} 4342623SN/A 4352623SN/Avoid 4362623SN/ABaseSimpleCPU::postExecute() 4372623SN/A{ 4382623SN/A#if FULL_SYSTEM 4395086Sgblack@eecs.umich.edu if (thread->profile && curStaticInst) { 4403577Sgblack@eecs.umich.edu bool usermode = TheISA::inUserMode(tc); 4412683Sktlim@umich.edu thread->profilePC = usermode ? 1 : thread->readPC(); 4425086Sgblack@eecs.umich.edu ProfileNode *node = thread->profile->consume(tc, curStaticInst); 4432623SN/A if (node) 4442683Sktlim@umich.edu thread->profileNode = node; 4452623SN/A } 4462420SN/A#endif 4472SN/A 4482623SN/A if (curStaticInst->isMemRef()) { 4492623SN/A numMemRefs++; 4502SN/A } 4512SN/A 4522623SN/A if (curStaticInst->isLoad()) { 4532623SN/A ++numLoad; 4542623SN/A comLoadEventQueue[0]->serviceEvents(numLoad); 4552623SN/A } 4562SN/A 4572683Sktlim@umich.edu traceFunctions(thread->readPC()); 4582644Sstever@eecs.umich.edu 4592644Sstever@eecs.umich.edu if (traceData) { 4604046Sbinkertn@umich.edu traceData->dump(); 4614046Sbinkertn@umich.edu delete traceData; 4624046Sbinkertn@umich.edu traceData = NULL; 4632644Sstever@eecs.umich.edu } 4642623SN/A} 4652SN/A 4662SN/A 4672623SN/Avoid 4682623SN/ABaseSimpleCPU::advancePC(Fault fault) 4692623SN/A{ 4704377Sgblack@eecs.umich.edu //Since we're moving to a new pc, zero out the offset 4714377Sgblack@eecs.umich.edu fetchOffset = 0; 4722090SN/A if (fault != NoFault) { 4733905Ssaidi@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 4745120Sgblack@eecs.umich.edu predecoder.reset(); 4755665Sgblack@eecs.umich.edu thread->setMicroPC(normalMicroPC(0)); 4765665Sgblack@eecs.umich.edu thread->setNextMicroPC(normalMicroPC(1)); 4775281Sgblack@eecs.umich.edu fault->invoke(tc); 4784377Sgblack@eecs.umich.edu } else { 4793276Sgblack@eecs.umich.edu //If we're at the last micro op for this instruction 4804539Sgblack@eecs.umich.edu if (curStaticInst && curStaticInst->isLastMicroop()) { 4815665Sgblack@eecs.umich.edu //We should be working with a macro op or be in the ROM 4825665Sgblack@eecs.umich.edu assert(curMacroStaticInst || 4835665Sgblack@eecs.umich.edu isRomMicroPC(thread->readMicroPC())); 4843276Sgblack@eecs.umich.edu //Close out this macro op, and clean up the 4853276Sgblack@eecs.umich.edu //microcode state 4863280Sgblack@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 4875665Sgblack@eecs.umich.edu thread->setMicroPC(normalMicroPC(0)); 4885665Sgblack@eecs.umich.edu thread->setNextMicroPC(normalMicroPC(1)); 4893276Sgblack@eecs.umich.edu } 4903276Sgblack@eecs.umich.edu //If we're still in a macro op 4915665Sgblack@eecs.umich.edu if (curMacroStaticInst || isRomMicroPC(thread->readMicroPC())) { 4923276Sgblack@eecs.umich.edu //Advance the micro pc 4933280Sgblack@eecs.umich.edu thread->setMicroPC(thread->readNextMicroPC()); 4943276Sgblack@eecs.umich.edu //Advance the "next" micro pc. Note that there are no delay 4953276Sgblack@eecs.umich.edu //slots, and micro ops are "word" addressed. 4963280Sgblack@eecs.umich.edu thread->setNextMicroPC(thread->readNextMicroPC() + 1); 4973276Sgblack@eecs.umich.edu } else { 4983276Sgblack@eecs.umich.edu // go to the next instruction 4993276Sgblack@eecs.umich.edu thread->setPC(thread->readNextPC()); 5003276Sgblack@eecs.umich.edu thread->setNextPC(thread->readNextNPC()); 5013276Sgblack@eecs.umich.edu thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst)); 5023276Sgblack@eecs.umich.edu assert(thread->readNextPC() != thread->readNextNPC()); 5033276Sgblack@eecs.umich.edu } 5042SN/A } 5052SN/A} 5062SN/A 5075250Sksewell@umich.edu/*Fault 5085222Sksewell@umich.eduBaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr) 5095222Sksewell@umich.edu{ 5105222Sksewell@umich.edu // translate to physical address 5115222Sksewell@umich.edu Fault fault = NoFault; 5125222Sksewell@umich.edu int CacheID = Op & 0x3; // Lower 3 bits identify Cache 5135222Sksewell@umich.edu int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation 5145222Sksewell@umich.edu if(CacheID > 1) 5155222Sksewell@umich.edu { 5165222Sksewell@umich.edu warn("CacheOps not implemented for secondary/tertiary caches\n"); 5175222Sksewell@umich.edu } 5185222Sksewell@umich.edu else 5195222Sksewell@umich.edu { 5205222Sksewell@umich.edu switch(CacheOP) 5215222Sksewell@umich.edu { // Fill Packet Type 5225222Sksewell@umich.edu case 0: warn("Invalidate Cache Op\n"); 5235222Sksewell@umich.edu break; 5245222Sksewell@umich.edu case 1: warn("Index Load Tag Cache Op\n"); 5255222Sksewell@umich.edu break; 5265222Sksewell@umich.edu case 2: warn("Index Store Tag Cache Op\n"); 5275222Sksewell@umich.edu break; 5285222Sksewell@umich.edu case 4: warn("Hit Invalidate Cache Op\n"); 5295222Sksewell@umich.edu break; 5305222Sksewell@umich.edu case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n"); 5315222Sksewell@umich.edu break; 5325222Sksewell@umich.edu case 6: warn("Hit Writeback\n"); 5335222Sksewell@umich.edu break; 5345222Sksewell@umich.edu case 7: warn("Fetch & Lock Cache Op\n"); 5355222Sksewell@umich.edu break; 5365222Sksewell@umich.edu default: warn("Unimplemented Cache Op\n"); 5375222Sksewell@umich.edu } 5385222Sksewell@umich.edu } 5395222Sksewell@umich.edu return fault; 5405250Sksewell@umich.edu}*/ 541