base.cc revision 4997
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292SN/A */ 302SN/A 312439SN/A#include "arch/utility.hh" 322984Sgblack@eecs.umich.edu#include "arch/faults.hh" 33146SN/A#include "base/cprintf.hh" 34146SN/A#include "base/inifile.hh" 35146SN/A#include "base/loader/symtab.hh" 36146SN/A#include "base/misc.hh" 37146SN/A#include "base/pollevent.hh" 38146SN/A#include "base/range.hh" 391717SN/A#include "base/stats/events.hh" 40146SN/A#include "base/trace.hh" 411717SN/A#include "cpu/base.hh" 42146SN/A#include "cpu/exetrace.hh" 431977SN/A#include "cpu/profile.hh" 442623SN/A#include "cpu/simple/base.hh" 452683Sktlim@umich.edu#include "cpu/simple_thread.hh" 461717SN/A#include "cpu/smt.hh" 47146SN/A#include "cpu/static_inst.hh" 482683Sktlim@umich.edu#include "cpu/thread_context.hh" 493348Sbinkertn@umich.edu#include "mem/packet.hh" 502036SN/A#include "sim/byteswap.hh" 51146SN/A#include "sim/debug.hh" 5256SN/A#include "sim/host.hh" 5356SN/A#include "sim/sim_events.hh" 5456SN/A#include "sim/sim_object.hh" 55695SN/A#include "sim/stats.hh" 562901Ssaidi@eecs.umich.edu#include "sim/system.hh" 572SN/A 581858SN/A#if FULL_SYSTEM 593565Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 603565Sgblack@eecs.umich.edu#include "arch/stacktrace.hh" 612171SN/A#include "arch/tlb.hh" 622170SN/A#include "arch/vtophys.hh" 633562Sgblack@eecs.umich.edu#include "base/remote_gdb.hh" 64146SN/A#else // !FULL_SYSTEM 652462SN/A#include "mem/mem_object.hh" 66146SN/A#endif // FULL_SYSTEM 672SN/A 682SN/Ausing namespace std; 692449SN/Ausing namespace TheISA; 701355SN/A 712623SN/ABaseSimpleCPU::BaseSimpleCPU(Params *p) 724495Sacolyte@umich.edu : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL) 73224SN/A{ 741858SN/A#if FULL_SYSTEM 752683Sktlim@umich.edu thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb); 762420SN/A#else 772683Sktlim@umich.edu thread = new SimpleThread(this, /* thread_num */ 0, p->process, 784997Sgblack@eecs.umich.edu p->itb, p->dtb, /* asid */ 0); 792420SN/A#endif // !FULL_SYSTEM 802SN/A 814400Srdreslin@umich.edu thread->setStatus(ThreadContext::Unallocated); 822672Sktlim@umich.edu 832683Sktlim@umich.edu tc = thread->getTC(); 842SN/A 852SN/A numInst = 0; 86334SN/A startNumInst = 0; 87140SN/A numLoad = 0; 88334SN/A startNumLoad = 0; 892SN/A lastIcacheStall = 0; 902SN/A lastDcacheStall = 0; 912SN/A 922680Sktlim@umich.edu threadContexts.push_back(tc); 934377Sgblack@eecs.umich.edu 944377Sgblack@eecs.umich.edu fetchOffset = 0; 954377Sgblack@eecs.umich.edu stayAtPC = false; 962SN/A} 972SN/A 982623SN/ABaseSimpleCPU::~BaseSimpleCPU() 992SN/A{ 1002SN/A} 1012SN/A 102180SN/Avoid 1032623SN/ABaseSimpleCPU::deallocateContext(int thread_num) 104393SN/A{ 105393SN/A // for now, these are equivalent 106393SN/A suspendContext(thread_num); 107393SN/A} 108384SN/A 109384SN/A 110393SN/Avoid 1112623SN/ABaseSimpleCPU::haltContext(int thread_num) 112393SN/A{ 113393SN/A // for now, these are equivalent 114393SN/A suspendContext(thread_num); 115393SN/A} 116384SN/A 117189SN/A 118189SN/Avoid 1192623SN/ABaseSimpleCPU::regStats() 1202SN/A{ 121729SN/A using namespace Stats; 122334SN/A 1232SN/A BaseCPU::regStats(); 1242SN/A 1252SN/A numInsts 1262SN/A .name(name() + ".num_insts") 1272SN/A .desc("Number of instructions executed") 1282SN/A ; 1292SN/A 1302SN/A numMemRefs 1312SN/A .name(name() + ".num_refs") 1322SN/A .desc("Number of memory references") 1332SN/A ; 1342SN/A 1351001SN/A notIdleFraction 1361001SN/A .name(name() + ".not_idle_fraction") 1371001SN/A .desc("Percentage of non-idle cycles") 1381001SN/A ; 1391001SN/A 1402SN/A idleFraction 1412SN/A .name(name() + ".idle_fraction") 1422SN/A .desc("Percentage of idle cycles") 1432SN/A ; 1442SN/A 1452SN/A icacheStallCycles 1462SN/A .name(name() + ".icache_stall_cycles") 1472SN/A .desc("ICache total stall cycles") 1482SN/A .prereq(icacheStallCycles) 1492SN/A ; 1502SN/A 1512SN/A dcacheStallCycles 1522SN/A .name(name() + ".dcache_stall_cycles") 1532SN/A .desc("DCache total stall cycles") 1542SN/A .prereq(dcacheStallCycles) 1552SN/A ; 1562SN/A 1572390SN/A icacheRetryCycles 1582390SN/A .name(name() + ".icache_retry_cycles") 1592390SN/A .desc("ICache total retry cycles") 1602390SN/A .prereq(icacheRetryCycles) 1612390SN/A ; 1622390SN/A 1632390SN/A dcacheRetryCycles 1642390SN/A .name(name() + ".dcache_retry_cycles") 1652390SN/A .desc("DCache total retry cycles") 1662390SN/A .prereq(dcacheRetryCycles) 1672390SN/A ; 1682390SN/A 169385SN/A idleFraction = constant(1.0) - notIdleFraction; 1702SN/A} 1712SN/A 1722SN/Avoid 1732623SN/ABaseSimpleCPU::resetStats() 174334SN/A{ 1752361SN/A// startNumInst = numInst; 1762623SN/A // notIdleFraction = (_status != Idle); 177334SN/A} 178334SN/A 179334SN/Avoid 1802623SN/ABaseSimpleCPU::serialize(ostream &os) 1812SN/A{ 182921SN/A BaseCPU::serialize(os); 1832915Sktlim@umich.edu// SERIALIZE_SCALAR(inst); 1842915Sktlim@umich.edu nameOut(os, csprintf("%s.xc.0", name())); 1852683Sktlim@umich.edu thread->serialize(os); 1862SN/A} 1872SN/A 1882SN/Avoid 1892623SN/ABaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1902SN/A{ 191921SN/A BaseCPU::unserialize(cp, section); 1922915Sktlim@umich.edu// UNSERIALIZE_SCALAR(inst); 1932915Sktlim@umich.edu thread->unserialize(cp, csprintf("%s.xc.0", section)); 1942SN/A} 1952SN/A 1962SN/Avoid 1972SN/Achange_thread_state(int thread_number, int activate, int priority) 1982SN/A{ 1992SN/A} 2002SN/A 201595SN/AFault 2022623SN/ABaseSimpleCPU::copySrcTranslate(Addr src) 203595SN/A{ 2042390SN/A#if 0 2051080SN/A static bool no_warn = true; 2061080SN/A int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 2071080SN/A // Only support block sizes of 64 atm. 2081080SN/A assert(blk_size == 64); 2091080SN/A int offset = src & (blk_size - 1); 2101080SN/A 2111080SN/A // Make sure block doesn't span page 2121121SN/A if (no_warn && 2132107SN/A (src & PageMask) != ((src + blk_size) & PageMask) && 2141089SN/A (src >> 40) != 0xfffffc) { 2151089SN/A warn("Copied block source spans pages %x.", src); 2161080SN/A no_warn = false; 2171080SN/A } 2181080SN/A 2191080SN/A memReq->reset(src & ~(blk_size - 1), blk_size); 220595SN/A 2212623SN/A // translate to physical address 2222683Sktlim@umich.edu Fault fault = thread->translateDataReadReq(req); 223595SN/A 2242090SN/A if (fault == NoFault) { 2252683Sktlim@umich.edu thread->copySrcAddr = src; 2262683Sktlim@umich.edu thread->copySrcPhysAddr = memReq->paddr + offset; 227595SN/A } else { 2282205SN/A assert(!fault->isAlignmentFault()); 2292205SN/A 2302683Sktlim@umich.edu thread->copySrcAddr = 0; 2312683Sktlim@umich.edu thread->copySrcPhysAddr = 0; 232595SN/A } 233595SN/A return fault; 2342390SN/A#else 2352423SN/A return NoFault; 2362390SN/A#endif 237595SN/A} 238595SN/A 239595SN/AFault 2402623SN/ABaseSimpleCPU::copy(Addr dest) 241595SN/A{ 2422390SN/A#if 0 2431080SN/A static bool no_warn = true; 244595SN/A int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 2451080SN/A // Only support block sizes of 64 atm. 2461080SN/A assert(blk_size == 64); 247595SN/A uint8_t data[blk_size]; 2482683Sktlim@umich.edu //assert(thread->copySrcAddr); 2491080SN/A int offset = dest & (blk_size - 1); 2501080SN/A 2511080SN/A // Make sure block doesn't span page 2521121SN/A if (no_warn && 2532107SN/A (dest & PageMask) != ((dest + blk_size) & PageMask) && 2541089SN/A (dest >> 40) != 0xfffffc) { 2551080SN/A no_warn = false; 2561089SN/A warn("Copied block destination spans pages %x. ", dest); 2571080SN/A } 2581080SN/A 2591080SN/A memReq->reset(dest & ~(blk_size -1), blk_size); 260595SN/A // translate to physical address 2612683Sktlim@umich.edu Fault fault = thread->translateDataWriteReq(req); 2621080SN/A 2632090SN/A if (fault == NoFault) { 2641080SN/A Addr dest_addr = memReq->paddr + offset; 265595SN/A // Need to read straight from memory since we have more than 8 bytes. 2662683Sktlim@umich.edu memReq->paddr = thread->copySrcPhysAddr; 2672683Sktlim@umich.edu thread->mem->read(memReq, data); 268595SN/A memReq->paddr = dest_addr; 2692683Sktlim@umich.edu thread->mem->write(memReq, data); 2701098SN/A if (dcacheInterface) { 2711098SN/A memReq->cmd = Copy; 2721098SN/A memReq->completionEvent = NULL; 2732683Sktlim@umich.edu memReq->paddr = thread->copySrcPhysAddr; 2741098SN/A memReq->dest = dest_addr; 2751098SN/A memReq->size = 64; 2761098SN/A memReq->time = curTick; 2772012SN/A memReq->flags &= ~INST_READ; 2781098SN/A dcacheInterface->access(memReq); 2791098SN/A } 280595SN/A } 2812205SN/A else 2822205SN/A assert(!fault->isAlignmentFault()); 2832205SN/A 284595SN/A return fault; 2852390SN/A#else 2862420SN/A panic("copy not implemented"); 2872423SN/A return NoFault; 2882390SN/A#endif 289595SN/A} 290595SN/A 2911858SN/A#if FULL_SYSTEM 2922SN/AAddr 2932623SN/ABaseSimpleCPU::dbg_vtophys(Addr addr) 2942SN/A{ 2952680Sktlim@umich.edu return vtophys(tc, addr); 2962SN/A} 2972SN/A#endif // FULL_SYSTEM 2982SN/A 2991858SN/A#if FULL_SYSTEM 3002SN/Avoid 3012623SN/ABaseSimpleCPU::post_interrupt(int int_num, int index) 3022SN/A{ 3032SN/A BaseCPU::post_interrupt(int_num, index); 3042SN/A 3052683Sktlim@umich.edu if (thread->status() == ThreadContext::Suspended) { 3064216Ssaidi@eecs.umich.edu DPRINTF(Quiesce,"Suspended Processor awoke\n"); 3072683Sktlim@umich.edu thread->activate(); 3082SN/A } 3092SN/A} 3102SN/A#endif // FULL_SYSTEM 3112SN/A 3122SN/Avoid 3132623SN/ABaseSimpleCPU::checkForInterrupts() 3142SN/A{ 3151858SN/A#if FULL_SYSTEM 3163923Shsul@eecs.umich.edu if (check_interrupts(tc)) { 3173520Sgblack@eecs.umich.edu Fault interrupt = interrupts.getInterrupt(tc); 3182SN/A 3193520Sgblack@eecs.umich.edu if (interrupt != NoFault) { 3203633Sktlim@umich.edu interrupts.updateIntrInfo(tc); 3213520Sgblack@eecs.umich.edu interrupt->invoke(tc); 3222SN/A } 3232SN/A } 3242SN/A#endif 3252623SN/A} 3262SN/A 3272623SN/A 3282623SN/AFault 3292662Sstever@eecs.umich.eduBaseSimpleCPU::setupFetchRequest(Request *req) 3302623SN/A{ 3314514Ssaidi@eecs.umich.edu Addr threadPC = thread->readPC(); 3324495Sacolyte@umich.edu 3332623SN/A // set up memory request for instruction fetch 3343093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 3354495Sacolyte@umich.edu DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC, 3363093Sksewell@umich.edu thread->readNextPC(),thread->readNextNPC()); 3373093Sksewell@umich.edu#else 3384564Sgblack@eecs.umich.edu DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p\n",threadPC, 3392741Sksewell@umich.edu thread->readNextPC()); 3402741Sksewell@umich.edu#endif 3412623SN/A 3424564Sgblack@eecs.umich.edu Addr fetchPC = (threadPC & PCMask) + fetchOffset; 3434564Sgblack@eecs.umich.edu req->setVirt(0, fetchPC, sizeof(MachInst), 0, threadPC); 3442623SN/A 3452683Sktlim@umich.edu Fault fault = thread->translateInstReq(req); 3462623SN/A 3472623SN/A return fault; 3482623SN/A} 3492623SN/A 3502623SN/A 3512623SN/Avoid 3522623SN/ABaseSimpleCPU::preExecute() 3532623SN/A{ 3542SN/A // maintain $r0 semantics 3552683Sktlim@umich.edu thread->setIntReg(ZeroReg, 0); 3562427SN/A#if THE_ISA == ALPHA_ISA 3572683Sktlim@umich.edu thread->setFloatReg(ZeroReg, 0.0); 3582427SN/A#endif // ALPHA_ISA 3592SN/A 3602623SN/A // keep an instruction count 3612623SN/A numInst++; 3622623SN/A numInsts++; 3632SN/A 3642683Sktlim@umich.edu thread->funcExeInst++; 3652SN/A 3662623SN/A // check for instruction-count-based events 3672623SN/A comInstEventQueue[0]->serviceEvents(numInst); 3682SN/A 3692623SN/A // decode the instruction 3702623SN/A inst = gtoh(inst); 3714377Sgblack@eecs.umich.edu 3723276Sgblack@eecs.umich.edu //If we're not in the middle of a macro instruction 3733276Sgblack@eecs.umich.edu if (!curMacroStaticInst) { 3744377Sgblack@eecs.umich.edu 3754181Sgblack@eecs.umich.edu StaticInstPtr instPtr = NULL; 3764181Sgblack@eecs.umich.edu 3774181Sgblack@eecs.umich.edu //Predecode, ie bundle up an ExtMachInst 3784182Sgblack@eecs.umich.edu //This should go away once the constructor can be set up properly 3794182Sgblack@eecs.umich.edu predecoder.setTC(thread->getTC()); 3804182Sgblack@eecs.umich.edu //If more fetch data is needed, pass it in. 3814593Sgblack@eecs.umich.edu Addr fetchPC = (thread->readPC() & PCMask) + fetchOffset; 3824593Sgblack@eecs.umich.edu //if(predecoder.needMoreBytes()) 3834593Sgblack@eecs.umich.edu predecoder.moreBytes(thread->readPC(), fetchPC, inst); 3844593Sgblack@eecs.umich.edu //else 3854593Sgblack@eecs.umich.edu // predecoder.process(); 3864377Sgblack@eecs.umich.edu 3874377Sgblack@eecs.umich.edu //If an instruction is ready, decode it. Otherwise, we'll have to 3884377Sgblack@eecs.umich.edu //fetch beyond the MachInst at the current pc. 3894377Sgblack@eecs.umich.edu if (predecoder.extMachInstReady()) { 3904377Sgblack@eecs.umich.edu#if THE_ISA == X86_ISA 3914377Sgblack@eecs.umich.edu thread->setNextPC(thread->readPC() + predecoder.getInstSize()); 3924377Sgblack@eecs.umich.edu#endif // X86_ISA 3934377Sgblack@eecs.umich.edu stayAtPC = false; 3944572Sacolyte@umich.edu instPtr = StaticInst::decode(predecoder.getExtMachInst(), 3954572Sacolyte@umich.edu thread->readPC()); 3964377Sgblack@eecs.umich.edu } else { 3974377Sgblack@eecs.umich.edu stayAtPC = true; 3984377Sgblack@eecs.umich.edu fetchOffset += sizeof(MachInst); 3994377Sgblack@eecs.umich.edu } 4004181Sgblack@eecs.umich.edu 4014181Sgblack@eecs.umich.edu //If we decoded an instruction and it's microcoded, start pulling 4024181Sgblack@eecs.umich.edu //out micro ops 4034539Sgblack@eecs.umich.edu if (instPtr && instPtr->isMacroop()) { 4043276Sgblack@eecs.umich.edu curMacroStaticInst = instPtr; 4053442Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst-> 4064539Sgblack@eecs.umich.edu fetchMicroop(thread->readMicroPC()); 4073280Sgblack@eecs.umich.edu } else { 4083280Sgblack@eecs.umich.edu curStaticInst = instPtr; 4093276Sgblack@eecs.umich.edu } 4103276Sgblack@eecs.umich.edu } else { 4113276Sgblack@eecs.umich.edu //Read the next micro op from the macro op 4123442Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst-> 4134539Sgblack@eecs.umich.edu fetchMicroop(thread->readMicroPC()); 4143276Sgblack@eecs.umich.edu } 4153276Sgblack@eecs.umich.edu 4164181Sgblack@eecs.umich.edu //If we decoded an instruction this "tick", record information about it. 4174181Sgblack@eecs.umich.edu if(curStaticInst) 4184181Sgblack@eecs.umich.edu { 4194522Ssaidi@eecs.umich.edu#if TRACING_ON 4204776Sgblack@eecs.umich.edu traceData = tracer->getInstRecord(curTick, tc, curStaticInst, 4214181Sgblack@eecs.umich.edu thread->readPC()); 4222470SN/A 4234181Sgblack@eecs.umich.edu DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n", 4244181Sgblack@eecs.umich.edu curStaticInst->getName(), curStaticInst->machInst); 4254522Ssaidi@eecs.umich.edu#endif // TRACING_ON 4262623SN/A 4272623SN/A#if FULL_SYSTEM 4284181Sgblack@eecs.umich.edu thread->setInst(inst); 4292623SN/A#endif // FULL_SYSTEM 4304181Sgblack@eecs.umich.edu } 4312623SN/A} 4322623SN/A 4332623SN/Avoid 4342623SN/ABaseSimpleCPU::postExecute() 4352623SN/A{ 4362623SN/A#if FULL_SYSTEM 4372683Sktlim@umich.edu if (thread->profile) { 4383577Sgblack@eecs.umich.edu bool usermode = TheISA::inUserMode(tc); 4392683Sktlim@umich.edu thread->profilePC = usermode ? 1 : thread->readPC(); 4404572Sacolyte@umich.edu StaticInstPtr si(inst, thread->readPC()); 4414254Sgblack@eecs.umich.edu ProfileNode *node = thread->profile->consume(tc, si); 4422623SN/A if (node) 4432683Sktlim@umich.edu thread->profileNode = node; 4442623SN/A } 4452420SN/A#endif 4462SN/A 4472623SN/A if (curStaticInst->isMemRef()) { 4482623SN/A numMemRefs++; 4492SN/A } 4502SN/A 4512623SN/A if (curStaticInst->isLoad()) { 4522623SN/A ++numLoad; 4532623SN/A comLoadEventQueue[0]->serviceEvents(numLoad); 4542623SN/A } 4552SN/A 4562683Sktlim@umich.edu traceFunctions(thread->readPC()); 4572644Sstever@eecs.umich.edu 4582644Sstever@eecs.umich.edu if (traceData) { 4594046Sbinkertn@umich.edu traceData->dump(); 4604046Sbinkertn@umich.edu delete traceData; 4614046Sbinkertn@umich.edu traceData = NULL; 4622644Sstever@eecs.umich.edu } 4632623SN/A} 4642SN/A 4652SN/A 4662623SN/Avoid 4672623SN/ABaseSimpleCPU::advancePC(Fault fault) 4682623SN/A{ 4694377Sgblack@eecs.umich.edu //Since we're moving to a new pc, zero out the offset 4704377Sgblack@eecs.umich.edu fetchOffset = 0; 4712090SN/A if (fault != NoFault) { 4723905Ssaidi@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 4732680Sktlim@umich.edu fault->invoke(tc); 4743929Ssaidi@eecs.umich.edu thread->setMicroPC(0); 4753929Ssaidi@eecs.umich.edu thread->setNextMicroPC(1); 4764377Sgblack@eecs.umich.edu } else { 4773276Sgblack@eecs.umich.edu //If we're at the last micro op for this instruction 4784539Sgblack@eecs.umich.edu if (curStaticInst && curStaticInst->isLastMicroop()) { 4793276Sgblack@eecs.umich.edu //We should be working with a macro op 4803276Sgblack@eecs.umich.edu assert(curMacroStaticInst); 4813276Sgblack@eecs.umich.edu //Close out this macro op, and clean up the 4823276Sgblack@eecs.umich.edu //microcode state 4833280Sgblack@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 4843276Sgblack@eecs.umich.edu thread->setMicroPC(0); 4853280Sgblack@eecs.umich.edu thread->setNextMicroPC(1); 4863276Sgblack@eecs.umich.edu } 4873276Sgblack@eecs.umich.edu //If we're still in a macro op 4883276Sgblack@eecs.umich.edu if (curMacroStaticInst) { 4893276Sgblack@eecs.umich.edu //Advance the micro pc 4903280Sgblack@eecs.umich.edu thread->setMicroPC(thread->readNextMicroPC()); 4913276Sgblack@eecs.umich.edu //Advance the "next" micro pc. Note that there are no delay 4923276Sgblack@eecs.umich.edu //slots, and micro ops are "word" addressed. 4933280Sgblack@eecs.umich.edu thread->setNextMicroPC(thread->readNextMicroPC() + 1); 4943276Sgblack@eecs.umich.edu } else { 4953276Sgblack@eecs.umich.edu // go to the next instruction 4963276Sgblack@eecs.umich.edu thread->setPC(thread->readNextPC()); 4973276Sgblack@eecs.umich.edu thread->setNextPC(thread->readNextNPC()); 4983276Sgblack@eecs.umich.edu thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst)); 4993276Sgblack@eecs.umich.edu assert(thread->readNextPC() != thread->readNextNPC()); 5003276Sgblack@eecs.umich.edu } 5012SN/A } 5022SN/A 5031858SN/A#if FULL_SYSTEM 5042SN/A Addr oldpc; 5052SN/A do { 5062683Sktlim@umich.edu oldpc = thread->readPC(); 5072680Sktlim@umich.edu system->pcEventQueue.service(tc); 5082683Sktlim@umich.edu } while (oldpc != thread->readPC()); 5092SN/A#endif 5102SN/A} 5112SN/A 512