base.cc revision 4572
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292SN/A */ 302SN/A 312439SN/A#include "arch/utility.hh" 322984Sgblack@eecs.umich.edu#include "arch/faults.hh" 33146SN/A#include "base/cprintf.hh" 34146SN/A#include "base/inifile.hh" 35146SN/A#include "base/loader/symtab.hh" 36146SN/A#include "base/misc.hh" 37146SN/A#include "base/pollevent.hh" 38146SN/A#include "base/range.hh" 391717SN/A#include "base/stats/events.hh" 40146SN/A#include "base/trace.hh" 411717SN/A#include "cpu/base.hh" 42146SN/A#include "cpu/exetrace.hh" 431977SN/A#include "cpu/profile.hh" 442623SN/A#include "cpu/simple/base.hh" 452683Sktlim@umich.edu#include "cpu/simple_thread.hh" 461717SN/A#include "cpu/smt.hh" 47146SN/A#include "cpu/static_inst.hh" 482683Sktlim@umich.edu#include "cpu/thread_context.hh" 493348Sbinkertn@umich.edu#include "mem/packet.hh" 502683Sktlim@umich.edu#include "sim/builder.hh" 512036SN/A#include "sim/byteswap.hh" 52146SN/A#include "sim/debug.hh" 5356SN/A#include "sim/host.hh" 5456SN/A#include "sim/sim_events.hh" 5556SN/A#include "sim/sim_object.hh" 56695SN/A#include "sim/stats.hh" 572901Ssaidi@eecs.umich.edu#include "sim/system.hh" 582SN/A 591858SN/A#if FULL_SYSTEM 603565Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 613565Sgblack@eecs.umich.edu#include "arch/stacktrace.hh" 622171SN/A#include "arch/tlb.hh" 632170SN/A#include "arch/vtophys.hh" 643562Sgblack@eecs.umich.edu#include "base/remote_gdb.hh" 65146SN/A#else // !FULL_SYSTEM 662462SN/A#include "mem/mem_object.hh" 67146SN/A#endif // FULL_SYSTEM 682SN/A 692SN/Ausing namespace std; 702449SN/Ausing namespace TheISA; 711355SN/A 722623SN/ABaseSimpleCPU::BaseSimpleCPU(Params *p) 734495Sacolyte@umich.edu : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL) 74224SN/A{ 751858SN/A#if FULL_SYSTEM 762683Sktlim@umich.edu thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb); 772420SN/A#else 782683Sktlim@umich.edu thread = new SimpleThread(this, /* thread_num */ 0, p->process, 793402Sktlim@umich.edu /* asid */ 0); 802420SN/A#endif // !FULL_SYSTEM 812SN/A 824400Srdreslin@umich.edu thread->setStatus(ThreadContext::Unallocated); 832672Sktlim@umich.edu 842683Sktlim@umich.edu tc = thread->getTC(); 852SN/A 862SN/A numInst = 0; 87334SN/A startNumInst = 0; 88140SN/A numLoad = 0; 89334SN/A startNumLoad = 0; 902SN/A lastIcacheStall = 0; 912SN/A lastDcacheStall = 0; 922SN/A 932680Sktlim@umich.edu threadContexts.push_back(tc); 944377Sgblack@eecs.umich.edu 954377Sgblack@eecs.umich.edu fetchOffset = 0; 964377Sgblack@eecs.umich.edu stayAtPC = false; 972SN/A} 982SN/A 992623SN/ABaseSimpleCPU::~BaseSimpleCPU() 1002SN/A{ 1012SN/A} 1022SN/A 103180SN/Avoid 1042623SN/ABaseSimpleCPU::deallocateContext(int thread_num) 105393SN/A{ 106393SN/A // for now, these are equivalent 107393SN/A suspendContext(thread_num); 108393SN/A} 109384SN/A 110384SN/A 111393SN/Avoid 1122623SN/ABaseSimpleCPU::haltContext(int thread_num) 113393SN/A{ 114393SN/A // for now, these are equivalent 115393SN/A suspendContext(thread_num); 116393SN/A} 117384SN/A 118189SN/A 119189SN/Avoid 1202623SN/ABaseSimpleCPU::regStats() 1212SN/A{ 122729SN/A using namespace Stats; 123334SN/A 1242SN/A BaseCPU::regStats(); 1252SN/A 1262SN/A numInsts 1272SN/A .name(name() + ".num_insts") 1282SN/A .desc("Number of instructions executed") 1292SN/A ; 1302SN/A 1312SN/A numMemRefs 1322SN/A .name(name() + ".num_refs") 1332SN/A .desc("Number of memory references") 1342SN/A ; 1352SN/A 1361001SN/A notIdleFraction 1371001SN/A .name(name() + ".not_idle_fraction") 1381001SN/A .desc("Percentage of non-idle cycles") 1391001SN/A ; 1401001SN/A 1412SN/A idleFraction 1422SN/A .name(name() + ".idle_fraction") 1432SN/A .desc("Percentage of idle cycles") 1442SN/A ; 1452SN/A 1462SN/A icacheStallCycles 1472SN/A .name(name() + ".icache_stall_cycles") 1482SN/A .desc("ICache total stall cycles") 1492SN/A .prereq(icacheStallCycles) 1502SN/A ; 1512SN/A 1522SN/A dcacheStallCycles 1532SN/A .name(name() + ".dcache_stall_cycles") 1542SN/A .desc("DCache total stall cycles") 1552SN/A .prereq(dcacheStallCycles) 1562SN/A ; 1572SN/A 1582390SN/A icacheRetryCycles 1592390SN/A .name(name() + ".icache_retry_cycles") 1602390SN/A .desc("ICache total retry cycles") 1612390SN/A .prereq(icacheRetryCycles) 1622390SN/A ; 1632390SN/A 1642390SN/A dcacheRetryCycles 1652390SN/A .name(name() + ".dcache_retry_cycles") 1662390SN/A .desc("DCache total retry cycles") 1672390SN/A .prereq(dcacheRetryCycles) 1682390SN/A ; 1692390SN/A 170385SN/A idleFraction = constant(1.0) - notIdleFraction; 1712SN/A} 1722SN/A 1732SN/Avoid 1742623SN/ABaseSimpleCPU::resetStats() 175334SN/A{ 1762361SN/A// startNumInst = numInst; 1772623SN/A // notIdleFraction = (_status != Idle); 178334SN/A} 179334SN/A 180334SN/Avoid 1812623SN/ABaseSimpleCPU::serialize(ostream &os) 1822SN/A{ 183921SN/A BaseCPU::serialize(os); 1842915Sktlim@umich.edu// SERIALIZE_SCALAR(inst); 1852915Sktlim@umich.edu nameOut(os, csprintf("%s.xc.0", name())); 1862683Sktlim@umich.edu thread->serialize(os); 1872SN/A} 1882SN/A 1892SN/Avoid 1902623SN/ABaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1912SN/A{ 192921SN/A BaseCPU::unserialize(cp, section); 1932915Sktlim@umich.edu// UNSERIALIZE_SCALAR(inst); 1942915Sktlim@umich.edu thread->unserialize(cp, csprintf("%s.xc.0", section)); 1952SN/A} 1962SN/A 1972SN/Avoid 1982SN/Achange_thread_state(int thread_number, int activate, int priority) 1992SN/A{ 2002SN/A} 2012SN/A 202595SN/AFault 2032623SN/ABaseSimpleCPU::copySrcTranslate(Addr src) 204595SN/A{ 2052390SN/A#if 0 2061080SN/A static bool no_warn = true; 2071080SN/A int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 2081080SN/A // Only support block sizes of 64 atm. 2091080SN/A assert(blk_size == 64); 2101080SN/A int offset = src & (blk_size - 1); 2111080SN/A 2121080SN/A // Make sure block doesn't span page 2131121SN/A if (no_warn && 2142107SN/A (src & PageMask) != ((src + blk_size) & PageMask) && 2151089SN/A (src >> 40) != 0xfffffc) { 2161089SN/A warn("Copied block source spans pages %x.", src); 2171080SN/A no_warn = false; 2181080SN/A } 2191080SN/A 2201080SN/A memReq->reset(src & ~(blk_size - 1), blk_size); 221595SN/A 2222623SN/A // translate to physical address 2232683Sktlim@umich.edu Fault fault = thread->translateDataReadReq(req); 224595SN/A 2252090SN/A if (fault == NoFault) { 2262683Sktlim@umich.edu thread->copySrcAddr = src; 2272683Sktlim@umich.edu thread->copySrcPhysAddr = memReq->paddr + offset; 228595SN/A } else { 2292205SN/A assert(!fault->isAlignmentFault()); 2302205SN/A 2312683Sktlim@umich.edu thread->copySrcAddr = 0; 2322683Sktlim@umich.edu thread->copySrcPhysAddr = 0; 233595SN/A } 234595SN/A return fault; 2352390SN/A#else 2362423SN/A return NoFault; 2372390SN/A#endif 238595SN/A} 239595SN/A 240595SN/AFault 2412623SN/ABaseSimpleCPU::copy(Addr dest) 242595SN/A{ 2432390SN/A#if 0 2441080SN/A static bool no_warn = true; 245595SN/A int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 2461080SN/A // Only support block sizes of 64 atm. 2471080SN/A assert(blk_size == 64); 248595SN/A uint8_t data[blk_size]; 2492683Sktlim@umich.edu //assert(thread->copySrcAddr); 2501080SN/A int offset = dest & (blk_size - 1); 2511080SN/A 2521080SN/A // Make sure block doesn't span page 2531121SN/A if (no_warn && 2542107SN/A (dest & PageMask) != ((dest + blk_size) & PageMask) && 2551089SN/A (dest >> 40) != 0xfffffc) { 2561080SN/A no_warn = false; 2571089SN/A warn("Copied block destination spans pages %x. ", dest); 2581080SN/A } 2591080SN/A 2601080SN/A memReq->reset(dest & ~(blk_size -1), blk_size); 261595SN/A // translate to physical address 2622683Sktlim@umich.edu Fault fault = thread->translateDataWriteReq(req); 2631080SN/A 2642090SN/A if (fault == NoFault) { 2651080SN/A Addr dest_addr = memReq->paddr + offset; 266595SN/A // Need to read straight from memory since we have more than 8 bytes. 2672683Sktlim@umich.edu memReq->paddr = thread->copySrcPhysAddr; 2682683Sktlim@umich.edu thread->mem->read(memReq, data); 269595SN/A memReq->paddr = dest_addr; 2702683Sktlim@umich.edu thread->mem->write(memReq, data); 2711098SN/A if (dcacheInterface) { 2721098SN/A memReq->cmd = Copy; 2731098SN/A memReq->completionEvent = NULL; 2742683Sktlim@umich.edu memReq->paddr = thread->copySrcPhysAddr; 2751098SN/A memReq->dest = dest_addr; 2761098SN/A memReq->size = 64; 2771098SN/A memReq->time = curTick; 2782012SN/A memReq->flags &= ~INST_READ; 2791098SN/A dcacheInterface->access(memReq); 2801098SN/A } 281595SN/A } 2822205SN/A else 2832205SN/A assert(!fault->isAlignmentFault()); 2842205SN/A 285595SN/A return fault; 2862390SN/A#else 2872420SN/A panic("copy not implemented"); 2882423SN/A return NoFault; 2892390SN/A#endif 290595SN/A} 291595SN/A 2921858SN/A#if FULL_SYSTEM 2932SN/AAddr 2942623SN/ABaseSimpleCPU::dbg_vtophys(Addr addr) 2952SN/A{ 2962680Sktlim@umich.edu return vtophys(tc, addr); 2972SN/A} 2982SN/A#endif // FULL_SYSTEM 2992SN/A 3001858SN/A#if FULL_SYSTEM 3012SN/Avoid 3022623SN/ABaseSimpleCPU::post_interrupt(int int_num, int index) 3032SN/A{ 3042SN/A BaseCPU::post_interrupt(int_num, index); 3052SN/A 3062683Sktlim@umich.edu if (thread->status() == ThreadContext::Suspended) { 3074216Ssaidi@eecs.umich.edu DPRINTF(Quiesce,"Suspended Processor awoke\n"); 3082683Sktlim@umich.edu thread->activate(); 3092SN/A } 3102SN/A} 3112SN/A#endif // FULL_SYSTEM 3122SN/A 3132SN/Avoid 3142623SN/ABaseSimpleCPU::checkForInterrupts() 3152SN/A{ 3161858SN/A#if FULL_SYSTEM 3173923Shsul@eecs.umich.edu if (check_interrupts(tc)) { 3183520Sgblack@eecs.umich.edu Fault interrupt = interrupts.getInterrupt(tc); 3192SN/A 3203520Sgblack@eecs.umich.edu if (interrupt != NoFault) { 3213633Sktlim@umich.edu interrupts.updateIntrInfo(tc); 3223520Sgblack@eecs.umich.edu interrupt->invoke(tc); 3232SN/A } 3242SN/A } 3252SN/A#endif 3262623SN/A} 3272SN/A 3282623SN/A 3292623SN/AFault 3302662Sstever@eecs.umich.eduBaseSimpleCPU::setupFetchRequest(Request *req) 3312623SN/A{ 3324514Ssaidi@eecs.umich.edu Addr threadPC = thread->readPC(); 3334495Sacolyte@umich.edu 3342623SN/A // set up memory request for instruction fetch 3353093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 3364495Sacolyte@umich.edu DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC, 3373093Sksewell@umich.edu thread->readNextPC(),thread->readNextNPC()); 3383093Sksewell@umich.edu#else 3394564Sgblack@eecs.umich.edu DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p\n",threadPC, 3402741Sksewell@umich.edu thread->readNextPC()); 3412741Sksewell@umich.edu#endif 3422623SN/A 3434564Sgblack@eecs.umich.edu Addr fetchPC = (threadPC & PCMask) + fetchOffset; 3444564Sgblack@eecs.umich.edu req->setVirt(0, fetchPC, sizeof(MachInst), 0, threadPC); 3452623SN/A 3462683Sktlim@umich.edu Fault fault = thread->translateInstReq(req); 3472623SN/A 3482623SN/A return fault; 3492623SN/A} 3502623SN/A 3512623SN/A 3522623SN/Avoid 3532623SN/ABaseSimpleCPU::preExecute() 3542623SN/A{ 3552SN/A // maintain $r0 semantics 3562683Sktlim@umich.edu thread->setIntReg(ZeroReg, 0); 3572427SN/A#if THE_ISA == ALPHA_ISA 3582683Sktlim@umich.edu thread->setFloatReg(ZeroReg, 0.0); 3592427SN/A#endif // ALPHA_ISA 3602SN/A 3612623SN/A // keep an instruction count 3622623SN/A numInst++; 3632623SN/A numInsts++; 3642SN/A 3652683Sktlim@umich.edu thread->funcExeInst++; 3662SN/A 3672623SN/A // check for instruction-count-based events 3682623SN/A comInstEventQueue[0]->serviceEvents(numInst); 3692SN/A 3702623SN/A // decode the instruction 3712623SN/A inst = gtoh(inst); 3724377Sgblack@eecs.umich.edu 3733276Sgblack@eecs.umich.edu //If we're not in the middle of a macro instruction 3743276Sgblack@eecs.umich.edu if (!curMacroStaticInst) { 3754377Sgblack@eecs.umich.edu 3764181Sgblack@eecs.umich.edu StaticInstPtr instPtr = NULL; 3774181Sgblack@eecs.umich.edu 3784181Sgblack@eecs.umich.edu //Predecode, ie bundle up an ExtMachInst 3794182Sgblack@eecs.umich.edu //This should go away once the constructor can be set up properly 3804182Sgblack@eecs.umich.edu predecoder.setTC(thread->getTC()); 3814182Sgblack@eecs.umich.edu //If more fetch data is needed, pass it in. 3824182Sgblack@eecs.umich.edu if(predecoder.needMoreBytes()) 3834564Sgblack@eecs.umich.edu predecoder.moreBytes(thread->readPC(), 3844564Sgblack@eecs.umich.edu (thread->readPC() & PCMask) + fetchOffset, 0, inst); 3854182Sgblack@eecs.umich.edu else 3864182Sgblack@eecs.umich.edu predecoder.process(); 3874377Sgblack@eecs.umich.edu 3884377Sgblack@eecs.umich.edu //If an instruction is ready, decode it. Otherwise, we'll have to 3894377Sgblack@eecs.umich.edu //fetch beyond the MachInst at the current pc. 3904377Sgblack@eecs.umich.edu if (predecoder.extMachInstReady()) { 3914377Sgblack@eecs.umich.edu#if THE_ISA == X86_ISA 3924377Sgblack@eecs.umich.edu thread->setNextPC(thread->readPC() + predecoder.getInstSize()); 3934377Sgblack@eecs.umich.edu#endif // X86_ISA 3944377Sgblack@eecs.umich.edu stayAtPC = false; 3954572Sacolyte@umich.edu instPtr = StaticInst::decode(predecoder.getExtMachInst(), 3964572Sacolyte@umich.edu thread->readPC()); 3974377Sgblack@eecs.umich.edu } else { 3984377Sgblack@eecs.umich.edu stayAtPC = true; 3994377Sgblack@eecs.umich.edu fetchOffset += sizeof(MachInst); 4004377Sgblack@eecs.umich.edu } 4014181Sgblack@eecs.umich.edu 4024181Sgblack@eecs.umich.edu //If we decoded an instruction and it's microcoded, start pulling 4034181Sgblack@eecs.umich.edu //out micro ops 4044539Sgblack@eecs.umich.edu if (instPtr && instPtr->isMacroop()) { 4053276Sgblack@eecs.umich.edu curMacroStaticInst = instPtr; 4063442Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst-> 4074539Sgblack@eecs.umich.edu fetchMicroop(thread->readMicroPC()); 4083280Sgblack@eecs.umich.edu } else { 4093280Sgblack@eecs.umich.edu curStaticInst = instPtr; 4103276Sgblack@eecs.umich.edu } 4113276Sgblack@eecs.umich.edu } else { 4123276Sgblack@eecs.umich.edu //Read the next micro op from the macro op 4133442Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst-> 4144539Sgblack@eecs.umich.edu fetchMicroop(thread->readMicroPC()); 4153276Sgblack@eecs.umich.edu } 4163276Sgblack@eecs.umich.edu 4174181Sgblack@eecs.umich.edu //If we decoded an instruction this "tick", record information about it. 4184181Sgblack@eecs.umich.edu if(curStaticInst) 4194181Sgblack@eecs.umich.edu { 4204522Ssaidi@eecs.umich.edu#if TRACING_ON 4214181Sgblack@eecs.umich.edu traceData = Trace::getInstRecord(curTick, tc, curStaticInst, 4224181Sgblack@eecs.umich.edu thread->readPC()); 4232470SN/A 4244181Sgblack@eecs.umich.edu DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n", 4254181Sgblack@eecs.umich.edu curStaticInst->getName(), curStaticInst->machInst); 4264522Ssaidi@eecs.umich.edu#endif // TRACING_ON 4272623SN/A 4282623SN/A#if FULL_SYSTEM 4294181Sgblack@eecs.umich.edu thread->setInst(inst); 4302623SN/A#endif // FULL_SYSTEM 4314181Sgblack@eecs.umich.edu } 4322623SN/A} 4332623SN/A 4342623SN/Avoid 4352623SN/ABaseSimpleCPU::postExecute() 4362623SN/A{ 4372623SN/A#if FULL_SYSTEM 4382683Sktlim@umich.edu if (thread->profile) { 4393577Sgblack@eecs.umich.edu bool usermode = TheISA::inUserMode(tc); 4402683Sktlim@umich.edu thread->profilePC = usermode ? 1 : thread->readPC(); 4414572Sacolyte@umich.edu StaticInstPtr si(inst, thread->readPC()); 4424254Sgblack@eecs.umich.edu ProfileNode *node = thread->profile->consume(tc, si); 4432623SN/A if (node) 4442683Sktlim@umich.edu thread->profileNode = node; 4452623SN/A } 4462420SN/A#endif 4472SN/A 4482623SN/A if (curStaticInst->isMemRef()) { 4492623SN/A numMemRefs++; 4502SN/A } 4512SN/A 4522623SN/A if (curStaticInst->isLoad()) { 4532623SN/A ++numLoad; 4542623SN/A comLoadEventQueue[0]->serviceEvents(numLoad); 4552623SN/A } 4562SN/A 4572683Sktlim@umich.edu traceFunctions(thread->readPC()); 4582644Sstever@eecs.umich.edu 4592644Sstever@eecs.umich.edu if (traceData) { 4604046Sbinkertn@umich.edu traceData->dump(); 4614046Sbinkertn@umich.edu delete traceData; 4624046Sbinkertn@umich.edu traceData = NULL; 4632644Sstever@eecs.umich.edu } 4642623SN/A} 4652SN/A 4662SN/A 4672623SN/Avoid 4682623SN/ABaseSimpleCPU::advancePC(Fault fault) 4692623SN/A{ 4704377Sgblack@eecs.umich.edu //Since we're moving to a new pc, zero out the offset 4714377Sgblack@eecs.umich.edu fetchOffset = 0; 4722090SN/A if (fault != NoFault) { 4733905Ssaidi@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 4742680Sktlim@umich.edu fault->invoke(tc); 4753929Ssaidi@eecs.umich.edu thread->setMicroPC(0); 4763929Ssaidi@eecs.umich.edu thread->setNextMicroPC(1); 4774377Sgblack@eecs.umich.edu } else { 4783276Sgblack@eecs.umich.edu //If we're at the last micro op for this instruction 4794539Sgblack@eecs.umich.edu if (curStaticInst && curStaticInst->isLastMicroop()) { 4803276Sgblack@eecs.umich.edu //We should be working with a macro op 4813276Sgblack@eecs.umich.edu assert(curMacroStaticInst); 4823276Sgblack@eecs.umich.edu //Close out this macro op, and clean up the 4833276Sgblack@eecs.umich.edu //microcode state 4843280Sgblack@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 4853276Sgblack@eecs.umich.edu thread->setMicroPC(0); 4863280Sgblack@eecs.umich.edu thread->setNextMicroPC(1); 4873276Sgblack@eecs.umich.edu } 4883276Sgblack@eecs.umich.edu //If we're still in a macro op 4893276Sgblack@eecs.umich.edu if (curMacroStaticInst) { 4903276Sgblack@eecs.umich.edu //Advance the micro pc 4913280Sgblack@eecs.umich.edu thread->setMicroPC(thread->readNextMicroPC()); 4923276Sgblack@eecs.umich.edu //Advance the "next" micro pc. Note that there are no delay 4933276Sgblack@eecs.umich.edu //slots, and micro ops are "word" addressed. 4943280Sgblack@eecs.umich.edu thread->setNextMicroPC(thread->readNextMicroPC() + 1); 4953276Sgblack@eecs.umich.edu } else { 4963276Sgblack@eecs.umich.edu // go to the next instruction 4973276Sgblack@eecs.umich.edu thread->setPC(thread->readNextPC()); 4983276Sgblack@eecs.umich.edu thread->setNextPC(thread->readNextNPC()); 4993276Sgblack@eecs.umich.edu thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst)); 5003276Sgblack@eecs.umich.edu assert(thread->readNextPC() != thread->readNextNPC()); 5013276Sgblack@eecs.umich.edu } 5022SN/A } 5032SN/A 5041858SN/A#if FULL_SYSTEM 5052SN/A Addr oldpc; 5062SN/A do { 5072683Sktlim@umich.edu oldpc = thread->readPC(); 5082680Sktlim@umich.edu system->pcEventQueue.service(tc); 5092683Sktlim@umich.edu } while (oldpc != thread->readPC()); 5102SN/A#endif 5112SN/A} 5122SN/A 513