base.cc revision 4375
12SN/A/*
21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
32SN/A * All rights reserved.
42SN/A *
52SN/A * Redistribution and use in source and binary forms, with or without
62SN/A * modification, are permitted provided that the following conditions are
72SN/A * met: redistributions of source code must retain the above copyright
82SN/A * notice, this list of conditions and the following disclaimer;
92SN/A * redistributions in binary form must reproduce the above copyright
102SN/A * notice, this list of conditions and the following disclaimer in the
112SN/A * documentation and/or other materials provided with the distribution;
122SN/A * neither the name of the copyright holders nor the names of its
132SN/A * contributors may be used to endorse or promote products derived from
142SN/A * this software without specific prior written permission.
152SN/A *
162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt
292SN/A */
302SN/A
312439SN/A#include "arch/utility.hh"
322984Sgblack@eecs.umich.edu#include "arch/faults.hh"
33146SN/A#include "base/cprintf.hh"
34146SN/A#include "base/inifile.hh"
35146SN/A#include "base/loader/symtab.hh"
36146SN/A#include "base/misc.hh"
37146SN/A#include "base/pollevent.hh"
38146SN/A#include "base/range.hh"
391717SN/A#include "base/stats/events.hh"
40146SN/A#include "base/trace.hh"
411717SN/A#include "cpu/base.hh"
42146SN/A#include "cpu/exetrace.hh"
431977SN/A#include "cpu/profile.hh"
442623SN/A#include "cpu/simple/base.hh"
452683Sktlim@umich.edu#include "cpu/simple_thread.hh"
461717SN/A#include "cpu/smt.hh"
47146SN/A#include "cpu/static_inst.hh"
482683Sktlim@umich.edu#include "cpu/thread_context.hh"
493348Sbinkertn@umich.edu#include "mem/packet.hh"
502683Sktlim@umich.edu#include "sim/builder.hh"
512036SN/A#include "sim/byteswap.hh"
52146SN/A#include "sim/debug.hh"
5356SN/A#include "sim/host.hh"
5456SN/A#include "sim/sim_events.hh"
5556SN/A#include "sim/sim_object.hh"
56695SN/A#include "sim/stats.hh"
572901Ssaidi@eecs.umich.edu#include "sim/system.hh"
582SN/A
591858SN/A#if FULL_SYSTEM
603565Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh"
613565Sgblack@eecs.umich.edu#include "arch/stacktrace.hh"
622171SN/A#include "arch/tlb.hh"
632170SN/A#include "arch/vtophys.hh"
643562Sgblack@eecs.umich.edu#include "base/remote_gdb.hh"
65146SN/A#else // !FULL_SYSTEM
662462SN/A#include "mem/mem_object.hh"
67146SN/A#endif // FULL_SYSTEM
682SN/A
692SN/Ausing namespace std;
702449SN/Ausing namespace TheISA;
711355SN/A
722623SN/ABaseSimpleCPU::BaseSimpleCPU(Params *p)
734182Sgblack@eecs.umich.edu    : BaseCPU(p), thread(NULL), predecoder(NULL)
74224SN/A{
751858SN/A#if FULL_SYSTEM
762683Sktlim@umich.edu    thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
772420SN/A#else
782683Sktlim@umich.edu    thread = new SimpleThread(this, /* thread_num */ 0, p->process,
793402Sktlim@umich.edu            /* asid */ 0);
802420SN/A#endif // !FULL_SYSTEM
812SN/A
822683Sktlim@umich.edu    thread->setStatus(ThreadContext::Suspended);
832672Sktlim@umich.edu
842683Sktlim@umich.edu    tc = thread->getTC();
852SN/A
862SN/A    numInst = 0;
87334SN/A    startNumInst = 0;
88140SN/A    numLoad = 0;
89334SN/A    startNumLoad = 0;
902SN/A    lastIcacheStall = 0;
912SN/A    lastDcacheStall = 0;
922SN/A
932680Sktlim@umich.edu    threadContexts.push_back(tc);
942SN/A}
952SN/A
962623SN/ABaseSimpleCPU::~BaseSimpleCPU()
972SN/A{
982SN/A}
992SN/A
100180SN/Avoid
1012623SN/ABaseSimpleCPU::deallocateContext(int thread_num)
102393SN/A{
103393SN/A    // for now, these are equivalent
104393SN/A    suspendContext(thread_num);
105393SN/A}
106384SN/A
107384SN/A
108393SN/Avoid
1092623SN/ABaseSimpleCPU::haltContext(int thread_num)
110393SN/A{
111393SN/A    // for now, these are equivalent
112393SN/A    suspendContext(thread_num);
113393SN/A}
114384SN/A
115189SN/A
116189SN/Avoid
1172623SN/ABaseSimpleCPU::regStats()
1182SN/A{
119729SN/A    using namespace Stats;
120334SN/A
1212SN/A    BaseCPU::regStats();
1222SN/A
1232SN/A    numInsts
1242SN/A        .name(name() + ".num_insts")
1252SN/A        .desc("Number of instructions executed")
1262SN/A        ;
1272SN/A
1282SN/A    numMemRefs
1292SN/A        .name(name() + ".num_refs")
1302SN/A        .desc("Number of memory references")
1312SN/A        ;
1322SN/A
1331001SN/A    notIdleFraction
1341001SN/A        .name(name() + ".not_idle_fraction")
1351001SN/A        .desc("Percentage of non-idle cycles")
1361001SN/A        ;
1371001SN/A
1382SN/A    idleFraction
1392SN/A        .name(name() + ".idle_fraction")
1402SN/A        .desc("Percentage of idle cycles")
1412SN/A        ;
1422SN/A
1432SN/A    icacheStallCycles
1442SN/A        .name(name() + ".icache_stall_cycles")
1452SN/A        .desc("ICache total stall cycles")
1462SN/A        .prereq(icacheStallCycles)
1472SN/A        ;
1482SN/A
1492SN/A    dcacheStallCycles
1502SN/A        .name(name() + ".dcache_stall_cycles")
1512SN/A        .desc("DCache total stall cycles")
1522SN/A        .prereq(dcacheStallCycles)
1532SN/A        ;
1542SN/A
1552390SN/A    icacheRetryCycles
1562390SN/A        .name(name() + ".icache_retry_cycles")
1572390SN/A        .desc("ICache total retry cycles")
1582390SN/A        .prereq(icacheRetryCycles)
1592390SN/A        ;
1602390SN/A
1612390SN/A    dcacheRetryCycles
1622390SN/A        .name(name() + ".dcache_retry_cycles")
1632390SN/A        .desc("DCache total retry cycles")
1642390SN/A        .prereq(dcacheRetryCycles)
1652390SN/A        ;
1662390SN/A
167385SN/A    idleFraction = constant(1.0) - notIdleFraction;
1682SN/A}
1692SN/A
1702SN/Avoid
1712623SN/ABaseSimpleCPU::resetStats()
172334SN/A{
1732361SN/A//    startNumInst = numInst;
1742623SN/A    // notIdleFraction = (_status != Idle);
175334SN/A}
176334SN/A
177334SN/Avoid
1782623SN/ABaseSimpleCPU::serialize(ostream &os)
1792SN/A{
180921SN/A    BaseCPU::serialize(os);
1812915Sktlim@umich.edu//    SERIALIZE_SCALAR(inst);
1822915Sktlim@umich.edu    nameOut(os, csprintf("%s.xc.0", name()));
1832683Sktlim@umich.edu    thread->serialize(os);
1842SN/A}
1852SN/A
1862SN/Avoid
1872623SN/ABaseSimpleCPU::unserialize(Checkpoint *cp, const string &section)
1882SN/A{
189921SN/A    BaseCPU::unserialize(cp, section);
1902915Sktlim@umich.edu//    UNSERIALIZE_SCALAR(inst);
1912915Sktlim@umich.edu    thread->unserialize(cp, csprintf("%s.xc.0", section));
1922SN/A}
1932SN/A
1942SN/Avoid
1952SN/Achange_thread_state(int thread_number, int activate, int priority)
1962SN/A{
1972SN/A}
1982SN/A
199595SN/AFault
2002623SN/ABaseSimpleCPU::copySrcTranslate(Addr src)
201595SN/A{
2022390SN/A#if 0
2031080SN/A    static bool no_warn = true;
2041080SN/A    int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
2051080SN/A    // Only support block sizes of 64 atm.
2061080SN/A    assert(blk_size == 64);
2071080SN/A    int offset = src & (blk_size - 1);
2081080SN/A
2091080SN/A    // Make sure block doesn't span page
2101121SN/A    if (no_warn &&
2112107SN/A        (src & PageMask) != ((src + blk_size) & PageMask) &&
2121089SN/A        (src >> 40) != 0xfffffc) {
2131089SN/A        warn("Copied block source spans pages %x.", src);
2141080SN/A        no_warn = false;
2151080SN/A    }
2161080SN/A
2171080SN/A    memReq->reset(src & ~(blk_size - 1), blk_size);
218595SN/A
2192623SN/A    // translate to physical address
2202683Sktlim@umich.edu    Fault fault = thread->translateDataReadReq(req);
221595SN/A
2222090SN/A    if (fault == NoFault) {
2232683Sktlim@umich.edu        thread->copySrcAddr = src;
2242683Sktlim@umich.edu        thread->copySrcPhysAddr = memReq->paddr + offset;
225595SN/A    } else {
2262205SN/A        assert(!fault->isAlignmentFault());
2272205SN/A
2282683Sktlim@umich.edu        thread->copySrcAddr = 0;
2292683Sktlim@umich.edu        thread->copySrcPhysAddr = 0;
230595SN/A    }
231595SN/A    return fault;
2322390SN/A#else
2332423SN/A    return NoFault;
2342390SN/A#endif
235595SN/A}
236595SN/A
237595SN/AFault
2382623SN/ABaseSimpleCPU::copy(Addr dest)
239595SN/A{
2402390SN/A#if 0
2411080SN/A    static bool no_warn = true;
242595SN/A    int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
2431080SN/A    // Only support block sizes of 64 atm.
2441080SN/A    assert(blk_size == 64);
245595SN/A    uint8_t data[blk_size];
2462683Sktlim@umich.edu    //assert(thread->copySrcAddr);
2471080SN/A    int offset = dest & (blk_size - 1);
2481080SN/A
2491080SN/A    // Make sure block doesn't span page
2501121SN/A    if (no_warn &&
2512107SN/A        (dest & PageMask) != ((dest + blk_size) & PageMask) &&
2521089SN/A        (dest >> 40) != 0xfffffc) {
2531080SN/A        no_warn = false;
2541089SN/A        warn("Copied block destination spans pages %x. ", dest);
2551080SN/A    }
2561080SN/A
2571080SN/A    memReq->reset(dest & ~(blk_size -1), blk_size);
258595SN/A    // translate to physical address
2592683Sktlim@umich.edu    Fault fault = thread->translateDataWriteReq(req);
2601080SN/A
2612090SN/A    if (fault == NoFault) {
2621080SN/A        Addr dest_addr = memReq->paddr + offset;
263595SN/A        // Need to read straight from memory since we have more than 8 bytes.
2642683Sktlim@umich.edu        memReq->paddr = thread->copySrcPhysAddr;
2652683Sktlim@umich.edu        thread->mem->read(memReq, data);
266595SN/A        memReq->paddr = dest_addr;
2672683Sktlim@umich.edu        thread->mem->write(memReq, data);
2681098SN/A        if (dcacheInterface) {
2691098SN/A            memReq->cmd = Copy;
2701098SN/A            memReq->completionEvent = NULL;
2712683Sktlim@umich.edu            memReq->paddr = thread->copySrcPhysAddr;
2721098SN/A            memReq->dest = dest_addr;
2731098SN/A            memReq->size = 64;
2741098SN/A            memReq->time = curTick;
2752012SN/A            memReq->flags &= ~INST_READ;
2761098SN/A            dcacheInterface->access(memReq);
2771098SN/A        }
278595SN/A    }
2792205SN/A    else
2802205SN/A        assert(!fault->isAlignmentFault());
2812205SN/A
282595SN/A    return fault;
2832390SN/A#else
2842420SN/A    panic("copy not implemented");
2852423SN/A    return NoFault;
2862390SN/A#endif
287595SN/A}
288595SN/A
2891858SN/A#if FULL_SYSTEM
2902SN/AAddr
2912623SN/ABaseSimpleCPU::dbg_vtophys(Addr addr)
2922SN/A{
2932680Sktlim@umich.edu    return vtophys(tc, addr);
2942SN/A}
2952SN/A#endif // FULL_SYSTEM
2962SN/A
2971858SN/A#if FULL_SYSTEM
2982SN/Avoid
2992623SN/ABaseSimpleCPU::post_interrupt(int int_num, int index)
3002SN/A{
3012SN/A    BaseCPU::post_interrupt(int_num, index);
3022SN/A
3032683Sktlim@umich.edu    if (thread->status() == ThreadContext::Suspended) {
3044216Ssaidi@eecs.umich.edu                DPRINTF(Quiesce,"Suspended Processor awoke\n");
3052683Sktlim@umich.edu        thread->activate();
3062SN/A    }
3072SN/A}
3082SN/A#endif // FULL_SYSTEM
3092SN/A
3102SN/Avoid
3112623SN/ABaseSimpleCPU::checkForInterrupts()
3122SN/A{
3131858SN/A#if FULL_SYSTEM
3143923Shsul@eecs.umich.edu    if (check_interrupts(tc)) {
3153520Sgblack@eecs.umich.edu        Fault interrupt = interrupts.getInterrupt(tc);
3162SN/A
3173520Sgblack@eecs.umich.edu        if (interrupt != NoFault) {
3183633Sktlim@umich.edu            interrupts.updateIntrInfo(tc);
3193520Sgblack@eecs.umich.edu            interrupt->invoke(tc);
3202SN/A        }
3212SN/A    }
3222SN/A#endif
3232623SN/A}
3242SN/A
3252623SN/A
3262623SN/AFault
3272662Sstever@eecs.umich.eduBaseSimpleCPU::setupFetchRequest(Request *req)
3282623SN/A{
3292623SN/A    // set up memory request for instruction fetch
3303093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT
3313093Sksewell@umich.edu    DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",thread->readPC(),
3323093Sksewell@umich.edu            thread->readNextPC(),thread->readNextNPC());
3333093Sksewell@umich.edu#else
3342741Sksewell@umich.edu    DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",thread->readPC(),
3352741Sksewell@umich.edu            thread->readNextPC());
3362741Sksewell@umich.edu#endif
3372623SN/A
3384375Sgblack@eecs.umich.edu    req->setVirt(0, thread->readPC() & ~3, sizeof(MachInst), 0,
3394375Sgblack@eecs.umich.edu            thread->readPC());
3402623SN/A
3412683Sktlim@umich.edu    Fault fault = thread->translateInstReq(req);
3422623SN/A
3432623SN/A    return fault;
3442623SN/A}
3452623SN/A
3462623SN/A
3472623SN/Avoid
3482623SN/ABaseSimpleCPU::preExecute()
3492623SN/A{
3502SN/A    // maintain $r0 semantics
3512683Sktlim@umich.edu    thread->setIntReg(ZeroReg, 0);
3522427SN/A#if THE_ISA == ALPHA_ISA
3532683Sktlim@umich.edu    thread->setFloatReg(ZeroReg, 0.0);
3542427SN/A#endif // ALPHA_ISA
3552SN/A
3562623SN/A    // keep an instruction count
3572623SN/A    numInst++;
3582623SN/A    numInsts++;
3592SN/A
3602683Sktlim@umich.edu    thread->funcExeInst++;
3612SN/A
3622623SN/A    // check for instruction-count-based events
3632623SN/A    comInstEventQueue[0]->serviceEvents(numInst);
3642SN/A
3652623SN/A    // decode the instruction
3662623SN/A    inst = gtoh(inst);
3673276Sgblack@eecs.umich.edu    //If we're not in the middle of a macro instruction
3683276Sgblack@eecs.umich.edu    if (!curMacroStaticInst) {
3694181Sgblack@eecs.umich.edu        StaticInstPtr instPtr = NULL;
3704181Sgblack@eecs.umich.edu
3714181Sgblack@eecs.umich.edu        //Predecode, ie bundle up an ExtMachInst
3724182Sgblack@eecs.umich.edu        //This should go away once the constructor can be set up properly
3734182Sgblack@eecs.umich.edu        predecoder.setTC(thread->getTC());
3744182Sgblack@eecs.umich.edu        //If more fetch data is needed, pass it in.
3754182Sgblack@eecs.umich.edu        if(predecoder.needMoreBytes())
3764182Sgblack@eecs.umich.edu            predecoder.moreBytes(thread->readPC(), 0, inst);
3774182Sgblack@eecs.umich.edu        else
3784182Sgblack@eecs.umich.edu            predecoder.process();
3794181Sgblack@eecs.umich.edu        //If an instruction is ready, decode it
3804182Sgblack@eecs.umich.edu        if (predecoder.extMachInstReady())
3814182Sgblack@eecs.umich.edu            instPtr = StaticInst::decode(predecoder.getExtMachInst());
3824181Sgblack@eecs.umich.edu
3834181Sgblack@eecs.umich.edu        //If we decoded an instruction and it's microcoded, start pulling
3844181Sgblack@eecs.umich.edu        //out micro ops
3854181Sgblack@eecs.umich.edu        if (instPtr && instPtr->isMacroOp()) {
3863276Sgblack@eecs.umich.edu            curMacroStaticInst = instPtr;
3873442Sgblack@eecs.umich.edu            curStaticInst = curMacroStaticInst->
3883442Sgblack@eecs.umich.edu                fetchMicroOp(thread->readMicroPC());
3893280Sgblack@eecs.umich.edu        } else {
3903280Sgblack@eecs.umich.edu            curStaticInst = instPtr;
3913276Sgblack@eecs.umich.edu        }
3923276Sgblack@eecs.umich.edu    } else {
3933276Sgblack@eecs.umich.edu        //Read the next micro op from the macro op
3943442Sgblack@eecs.umich.edu        curStaticInst = curMacroStaticInst->
3953442Sgblack@eecs.umich.edu            fetchMicroOp(thread->readMicroPC());
3963276Sgblack@eecs.umich.edu    }
3973276Sgblack@eecs.umich.edu
3984181Sgblack@eecs.umich.edu    //If we decoded an instruction this "tick", record information about it.
3994181Sgblack@eecs.umich.edu    if(curStaticInst)
4004181Sgblack@eecs.umich.edu    {
4014181Sgblack@eecs.umich.edu        traceData = Trace::getInstRecord(curTick, tc, curStaticInst,
4024181Sgblack@eecs.umich.edu                                         thread->readPC());
4032470SN/A
4044181Sgblack@eecs.umich.edu        DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n",
4054181Sgblack@eecs.umich.edu                curStaticInst->getName(), curStaticInst->machInst);
4062623SN/A
4072623SN/A#if FULL_SYSTEM
4084181Sgblack@eecs.umich.edu        thread->setInst(inst);
4092623SN/A#endif // FULL_SYSTEM
4104181Sgblack@eecs.umich.edu    }
4112623SN/A}
4122623SN/A
4132623SN/Avoid
4142623SN/ABaseSimpleCPU::postExecute()
4152623SN/A{
4162623SN/A#if FULL_SYSTEM
4172683Sktlim@umich.edu    if (thread->profile) {
4183577Sgblack@eecs.umich.edu        bool usermode = TheISA::inUserMode(tc);
4192683Sktlim@umich.edu        thread->profilePC = usermode ? 1 : thread->readPC();
4204254Sgblack@eecs.umich.edu        StaticInstPtr si(inst);
4214254Sgblack@eecs.umich.edu        ProfileNode *node = thread->profile->consume(tc, si);
4222623SN/A        if (node)
4232683Sktlim@umich.edu            thread->profileNode = node;
4242623SN/A    }
4252420SN/A#endif
4262SN/A
4272623SN/A    if (curStaticInst->isMemRef()) {
4282623SN/A        numMemRefs++;
4292SN/A    }
4302SN/A
4312623SN/A    if (curStaticInst->isLoad()) {
4322623SN/A        ++numLoad;
4332623SN/A        comLoadEventQueue[0]->serviceEvents(numLoad);
4342623SN/A    }
4352SN/A
4362683Sktlim@umich.edu    traceFunctions(thread->readPC());
4372644Sstever@eecs.umich.edu
4382644Sstever@eecs.umich.edu    if (traceData) {
4394046Sbinkertn@umich.edu        traceData->dump();
4404046Sbinkertn@umich.edu        delete traceData;
4414046Sbinkertn@umich.edu        traceData = NULL;
4422644Sstever@eecs.umich.edu    }
4432623SN/A}
4442SN/A
4452SN/A
4462623SN/Avoid
4472623SN/ABaseSimpleCPU::advancePC(Fault fault)
4482623SN/A{
4492090SN/A    if (fault != NoFault) {
4503905Ssaidi@eecs.umich.edu        curMacroStaticInst = StaticInst::nullStaticInstPtr;
4512680Sktlim@umich.edu        fault->invoke(tc);
4523929Ssaidi@eecs.umich.edu        thread->setMicroPC(0);
4533929Ssaidi@eecs.umich.edu        thread->setNextMicroPC(1);
4544182Sgblack@eecs.umich.edu    } else if (predecoder.needMoreBytes()) {
4553276Sgblack@eecs.umich.edu        //If we're at the last micro op for this instruction
4564182Sgblack@eecs.umich.edu        if (curStaticInst && curStaticInst->isLastMicroOp()) {
4573276Sgblack@eecs.umich.edu            //We should be working with a macro op
4583276Sgblack@eecs.umich.edu            assert(curMacroStaticInst);
4593276Sgblack@eecs.umich.edu            //Close out this macro op, and clean up the
4603276Sgblack@eecs.umich.edu            //microcode state
4613280Sgblack@eecs.umich.edu            curMacroStaticInst = StaticInst::nullStaticInstPtr;
4623276Sgblack@eecs.umich.edu            thread->setMicroPC(0);
4633280Sgblack@eecs.umich.edu            thread->setNextMicroPC(1);
4643276Sgblack@eecs.umich.edu        }
4653276Sgblack@eecs.umich.edu        //If we're still in a macro op
4663276Sgblack@eecs.umich.edu        if (curMacroStaticInst) {
4673276Sgblack@eecs.umich.edu            //Advance the micro pc
4683280Sgblack@eecs.umich.edu            thread->setMicroPC(thread->readNextMicroPC());
4693276Sgblack@eecs.umich.edu            //Advance the "next" micro pc. Note that there are no delay
4703276Sgblack@eecs.umich.edu            //slots, and micro ops are "word" addressed.
4713280Sgblack@eecs.umich.edu            thread->setNextMicroPC(thread->readNextMicroPC() + 1);
4723276Sgblack@eecs.umich.edu        } else {
4733276Sgblack@eecs.umich.edu            // go to the next instruction
4743276Sgblack@eecs.umich.edu            thread->setPC(thread->readNextPC());
4753276Sgblack@eecs.umich.edu            thread->setNextPC(thread->readNextNPC());
4763276Sgblack@eecs.umich.edu            thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
4773276Sgblack@eecs.umich.edu            assert(thread->readNextPC() != thread->readNextNPC());
4783276Sgblack@eecs.umich.edu        }
4792SN/A    }
4802SN/A
4811858SN/A#if FULL_SYSTEM
4822SN/A    Addr oldpc;
4832SN/A    do {
4842683Sktlim@umich.edu        oldpc = thread->readPC();
4852680Sktlim@umich.edu        system->pcEventQueue.service(tc);
4862683Sktlim@umich.edu    } while (oldpc != thread->readPC());
4872SN/A#endif
4882SN/A}
4892SN/A
490