base.cc revision 385 
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <cmath>
30#include <cstdio>
31#include <cstdlib>
32#include <iostream>
33#include <iomanip>
34#include <list>
35#include <sstream>
36#include <string>
37
38#include "base/cprintf.hh"
39#include "base/inifile.hh"
40#include "base/loader/symtab.hh"
41#include "base/misc.hh"
42#include "base/pollevent.hh"
43#include "base/range.hh"
44#include "base/trace.hh"
45#include "cpu/base_cpu.hh"
46#include "cpu/exec_context.hh"
47#include "cpu/exetrace.hh"
48#include "cpu/full_cpu/smt.hh"
49#include "cpu/simple_cpu/simple_cpu.hh"
50#include "cpu/static_inst.hh"
51#include "mem/base_mem.hh"
52#include "mem/mem_interface.hh"
53#include "sim/annotation.hh"
54#include "sim/builder.hh"
55#include "sim/debug.hh"
56#include "sim/host.hh"
57#include "sim/sim_events.hh"
58#include "sim/sim_object.hh"
59#include "sim/sim_stats.hh"
60
61#ifdef FULL_SYSTEM
62#include "base/remote_gdb.hh"
63#include "dev/alpha_access.h"
64#include "dev/pciareg.h"
65#include "mem/functional_mem/memory_control.hh"
66#include "mem/functional_mem/physical_memory.hh"
67#include "sim/system.hh"
68#include "targetarch/alpha_memory.hh"
69#include "targetarch/vtophys.hh"
70#else // !FULL_SYSTEM
71#include "eio/eio.hh"
72#include "mem/functional_mem/functional_memory.hh"
73#endif // FULL_SYSTEM
74
75using namespace std;
76
77SimpleCPU::TickEvent::TickEvent(SimpleCPU *c)
78    : Event(&mainEventQueue, 100), cpu(c)
79{
80}
81
82void
83SimpleCPU::TickEvent::process()
84{
85    cpu->tick();
86}
87
88const char *
89SimpleCPU::TickEvent::description()
90{
91    return "SimpleCPU tick event";
92}
93
94
95SimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu)
96    : Event(&mainEventQueue),
97      cpu(_cpu)
98{
99}
100
101void SimpleCPU::CacheCompletionEvent::process()
102{
103    cpu->processCacheCompletion();
104}
105
106const char *
107SimpleCPU::CacheCompletionEvent::description()
108{
109    return "SimpleCPU cache completion event";
110}
111
112#ifdef FULL_SYSTEM
113SimpleCPU::SimpleCPU(const string &_name,
114                     System *_system,
115                     Counter max_insts_any_thread,
116                     Counter max_insts_all_threads,
117                     Counter max_loads_any_thread,
118                     Counter max_loads_all_threads,
119                     AlphaItb *itb, AlphaDtb *dtb,
120                     FunctionalMemory *mem,
121                     MemInterface *icache_interface,
122                     MemInterface *dcache_interface,
123                     Tick freq)
124    : BaseCPU(_name, /* number_of_threads */ 1,
125              max_insts_any_thread, max_insts_all_threads,
126              max_loads_any_thread, max_loads_all_threads,
127              _system, freq),
128#else
129SimpleCPU::SimpleCPU(const string &_name, Process *_process,
130                     Counter max_insts_any_thread,
131                     Counter max_insts_all_threads,
132                     Counter max_loads_any_thread,
133                     Counter max_loads_all_threads,
134                     MemInterface *icache_interface,
135                     MemInterface *dcache_interface)
136    : BaseCPU(_name, /* number_of_threads */ 1,
137              max_insts_any_thread, max_insts_all_threads,
138              max_loads_any_thread, max_loads_all_threads),
139#endif
140      tickEvent(this), xc(NULL), cacheCompletionEvent(this)
141{
142    _status = Idle;
143#ifdef FULL_SYSTEM
144    xc = new ExecContext(this, 0, system, itb, dtb, mem);
145
146    // initialize CPU, including PC
147    TheISA::initCPU(&xc->regs);
148#else
149    xc = new ExecContext(this, /* thread_num */ 0, _process, /* asid */ 0);
150#endif // !FULL_SYSTEM
151
152    icacheInterface = icache_interface;
153    dcacheInterface = dcache_interface;
154
155    memReq = new MemReq();
156    memReq->xc = xc;
157    memReq->asid = 0;
158    memReq->data = new uint8_t[64];
159
160    numInst = 0;
161    startNumInst = 0;
162    numLoad = 0;
163    startNumLoad = 0;
164    lastIcacheStall = 0;
165    lastDcacheStall = 0;
166
167    execContexts.push_back(xc);
168}
169
170SimpleCPU::~SimpleCPU()
171{
172}
173
174void
175SimpleCPU::switchOut()
176{
177    _status = SwitchedOut;
178    if (tickEvent.scheduled())
179        tickEvent.squash();
180}
181
182
183void
184SimpleCPU::takeOverFrom(BaseCPU *oldCPU)
185{
186    BaseCPU::takeOverFrom(oldCPU);
187
188    assert(!tickEvent.scheduled());
189
190    // if any of this CPU's ExecContexts are active, mark the CPU as
191    // running and schedule its tick event.
192    for (int i = 0; i < execContexts.size(); ++i) {
193        ExecContext *xc = execContexts[i];
194        if (xc->status() == ExecContext::Active && _status != Running) {
195            _status = Running;
196            tickEvent.schedule(curTick);
197        }
198    }
199
200    oldCPU->switchOut();
201}
202
203
204void
205SimpleCPU::execCtxStatusChg(int thread_num) {
206    assert(thread_num == 0);
207    assert(xc);
208
209    if (xc->status() == ExecContext::Active)
210        setStatus(Running);
211    else
212        setStatus(Idle);
213}
214
215void
216SimpleCPU::setStatus(Status new_status)
217{
218    Status old_status = status();
219
220    // We should never even get here if the CPU has been switched out.
221    assert(old_status != SwitchedOut);
222
223    _status = new_status;
224
225    switch (status()) {
226      case IcacheMissStall:
227        assert(old_status == Running);
228        lastIcacheStall = curTick;
229        if (tickEvent.scheduled())
230            tickEvent.squash();
231        break;
232
233      case IcacheMissComplete:
234        assert(old_status == IcacheMissStall);
235        if (tickEvent.squashed())
236            tickEvent.reschedule(curTick + 1);
237        else if (!tickEvent.scheduled())
238            tickEvent.schedule(curTick + 1);
239        break;
240
241      case DcacheMissStall:
242        assert(old_status == Running);
243        lastDcacheStall = curTick;
244        if (tickEvent.scheduled())
245            tickEvent.squash();
246        break;
247
248      case Idle:
249        assert(old_status == Running);
250        notIdleFraction--;
251        if (tickEvent.scheduled())
252            tickEvent.squash();
253        break;
254
255      case Running:
256        assert(old_status == Idle ||
257               old_status == DcacheMissStall ||
258               old_status == IcacheMissComplete);
259        if (old_status == Idle)
260            notIdleFraction++;
261
262        if (tickEvent.squashed())
263            tickEvent.reschedule(curTick + 1);
264        else if (!tickEvent.scheduled())
265            tickEvent.schedule(curTick + 1);
266        break;
267
268      default:
269        panic("can't get here");
270    }
271}
272
273void
274SimpleCPU::regStats()
275{
276    using namespace Statistics;
277
278    BaseCPU::regStats();
279
280    numInsts
281        .name(name() + ".num_insts")
282        .desc("Number of instructions executed")
283        ;
284
285    numMemRefs
286        .name(name() + ".num_refs")
287        .desc("Number of memory references")
288        ;
289
290    idleFraction
291        .name(name() + ".idle_fraction")
292        .desc("Percentage of idle cycles")
293        ;
294
295    icacheStallCycles
296        .name(name() + ".icache_stall_cycles")
297        .desc("ICache total stall cycles")
298        .prereq(icacheStallCycles)
299        ;
300
301    dcacheStallCycles
302        .name(name() + ".dcache_stall_cycles")
303        .desc("DCache total stall cycles")
304        .prereq(dcacheStallCycles)
305        ;
306
307    idleFraction = constant(1.0) - notIdleFraction;
308    numInsts = Statistics::scalar(numInst) - Statistics::scalar(startNumInst);
309    simInsts += numInsts;
310}
311
312void
313SimpleCPU::resetStats()
314{
315    startNumInst = numInst;
316    notIdleFraction = (_status != Idle);
317}
318
319void
320SimpleCPU::serialize(ostream &os)
321{
322    SERIALIZE_ENUM(_status);
323    SERIALIZE_SCALAR(inst);
324    nameOut(os, csprintf("%s.xc", name()));
325    xc->serialize(os);
326    nameOut(os, csprintf("%s.tickEvent", name()));
327    tickEvent.serialize(os);
328    nameOut(os, csprintf("%s.cacheCompletionEvent", name()));
329    cacheCompletionEvent.serialize(os);
330}
331
332void
333SimpleCPU::unserialize(Checkpoint *cp, const string &section)
334{
335    UNSERIALIZE_ENUM(_status);
336    UNSERIALIZE_SCALAR(inst);
337    xc->unserialize(cp, csprintf("%s.xc", section));
338    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
339    cacheCompletionEvent
340        .unserialize(cp, csprintf("%s.cacheCompletionEvent", section));
341}
342
343void
344change_thread_state(int thread_number, int activate, int priority)
345{
346}
347
348// precise architected memory state accessor macros
349template <class T>
350Fault
351SimpleCPU::read(Addr addr, T& data, unsigned flags)
352{
353    memReq->reset(addr, sizeof(T), flags);
354
355    // translate to physical address
356    Fault fault = xc->translateDataReadReq(memReq);
357
358    // do functional access
359    if (fault == No_Fault)
360        fault = xc->read(memReq, data);
361
362    if (traceData) {
363        traceData->setAddr(addr);
364        if (fault == No_Fault)
365            traceData->setData(data);
366    }
367
368    // if we have a cache, do cache access too
369    if (fault == No_Fault && dcacheInterface) {
370        memReq->cmd = Read;
371        memReq->completionEvent = NULL;
372        memReq->time = curTick;
373        memReq->flags &= ~UNCACHEABLE;
374        MemAccessResult result = dcacheInterface->access(memReq);
375
376        // Ugly hack to get an event scheduled *only* if the access is
377        // a miss.  We really should add first-class support for this
378        // at some point.
379        if (result != MA_HIT && dcacheInterface->doEvents) {
380            memReq->completionEvent = &cacheCompletionEvent;
381            setStatus(DcacheMissStall);
382        }
383    }
384
385    return fault;
386}
387
388#ifndef DOXYGEN_SHOULD_SKIP_THIS
389
390template
391Fault
392SimpleCPU::read(Addr addr, uint64_t& data, unsigned flags);
393
394template
395Fault
396SimpleCPU::read(Addr addr, uint32_t& data, unsigned flags);
397
398template
399Fault
400SimpleCPU::read(Addr addr, uint16_t& data, unsigned flags);
401
402template
403Fault
404SimpleCPU::read(Addr addr, uint8_t& data, unsigned flags);
405
406#endif //DOXYGEN_SHOULD_SKIP_THIS
407
408template<>
409Fault
410SimpleCPU::read(Addr addr, double& data, unsigned flags)
411{
412    return read(addr, *(uint64_t*)&data, flags);
413}
414
415template<>
416Fault
417SimpleCPU::read(Addr addr, float& data, unsigned flags)
418{
419    return read(addr, *(uint32_t*)&data, flags);
420}
421
422
423template<>
424Fault
425SimpleCPU::read(Addr addr, int32_t& data, unsigned flags)
426{
427    return read(addr, (uint32_t&)data, flags);
428}
429
430
431template <class T>
432Fault
433SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
434{
435    if (traceData) {
436        traceData->setAddr(addr);
437        traceData->setData(data);
438    }
439
440    memReq->reset(addr, sizeof(T), flags);
441
442    // translate to physical address
443    Fault fault = xc->translateDataWriteReq(memReq);
444
445    // do functional access
446    if (fault == No_Fault)
447        fault = xc->write(memReq, data);
448
449    if (fault == No_Fault && dcacheInterface) {
450        memReq->cmd = Write;
451        memcpy(memReq->data,(uint8_t *)&data,memReq->size);
452        memReq->completionEvent = NULL;
453        memReq->time = curTick;
454        memReq->flags &= ~UNCACHEABLE;
455        MemAccessResult result = dcacheInterface->access(memReq);
456
457        // Ugly hack to get an event scheduled *only* if the access is
458        // a miss.  We really should add first-class support for this
459        // at some point.
460        if (result != MA_HIT && dcacheInterface->doEvents) {
461            memReq->completionEvent = &cacheCompletionEvent;
462            setStatus(DcacheMissStall);
463        }
464    }
465
466    if (res && (fault == No_Fault))
467        *res = memReq->result;
468
469    return fault;
470}
471
472
473#ifndef DOXYGEN_SHOULD_SKIP_THIS
474template
475Fault
476SimpleCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res);
477
478template
479Fault
480SimpleCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res);
481
482template
483Fault
484SimpleCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res);
485
486template
487Fault
488SimpleCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res);
489
490#endif //DOXYGEN_SHOULD_SKIP_THIS
491
492template<>
493Fault
494SimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
495{
496    return write(*(uint64_t*)&data, addr, flags, res);
497}
498
499template<>
500Fault
501SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
502{
503    return write(*(uint32_t*)&data, addr, flags, res);
504}
505
506
507template<>
508Fault
509SimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
510{
511    return write((uint32_t)data, addr, flags, res);
512}
513
514
515#ifdef FULL_SYSTEM
516Addr
517SimpleCPU::dbg_vtophys(Addr addr)
518{
519    return vtophys(xc, addr);
520}
521#endif // FULL_SYSTEM
522
523Tick save_cycle = 0;
524
525
526void
527SimpleCPU::processCacheCompletion()
528{
529    switch (status()) {
530      case IcacheMissStall:
531        icacheStallCycles += curTick - lastIcacheStall;
532        setStatus(IcacheMissComplete);
533        break;
534      case DcacheMissStall:
535        dcacheStallCycles += curTick - lastDcacheStall;
536        setStatus(Running);
537        break;
538      case SwitchedOut:
539        // If this CPU has been switched out due to sampling/warm-up,
540        // ignore any further status changes (e.g., due to cache
541        // misses outstanding at the time of the switch).
542        return;
543      default:
544        panic("SimpleCPU::processCacheCompletion: bad state");
545        break;
546    }
547}
548
549#ifdef FULL_SYSTEM
550void
551SimpleCPU::post_interrupt(int int_num, int index)
552{
553    BaseCPU::post_interrupt(int_num, index);
554
555    if (xc->status() == ExecContext::Suspended) {
556                DPRINTF(IPI,"Suspended Processor awoke\n");
557        xc->setStatus(ExecContext::Active);
558        Annotate::Resume(xc);
559    }
560}
561#endif // FULL_SYSTEM
562
563/* start simulation, program loaded, processor precise state initialized */
564void
565SimpleCPU::tick()
566{
567    traceData = NULL;
568
569    Fault fault = No_Fault;
570
571#ifdef FULL_SYSTEM
572    if (AlphaISA::check_interrupts &&
573        xc->cpu->check_interrupts() &&
574        !PC_PAL(xc->regs.pc) &&
575        status() != IcacheMissComplete) {
576        int ipl = 0;
577        int summary = 0;
578        AlphaISA::check_interrupts = 0;
579        IntReg *ipr = xc->regs.ipr;
580
581        if (xc->regs.ipr[TheISA::IPR_SIRR]) {
582            for (int i = TheISA::INTLEVEL_SOFTWARE_MIN;
583                 i < TheISA::INTLEVEL_SOFTWARE_MAX; i++) {
584                if (ipr[TheISA::IPR_SIRR] & (ULL(1) << i)) {
585                    // See table 4-19 of 21164 hardware reference
586                    ipl = (i - TheISA::INTLEVEL_SOFTWARE_MIN) + 1;
587                    summary |= (ULL(1) << i);
588                }
589            }
590        }
591
592        uint64_t interrupts = xc->cpu->intr_status();
593        for (int i = TheISA::INTLEVEL_EXTERNAL_MIN;
594            i < TheISA::INTLEVEL_EXTERNAL_MAX; i++) {
595            if (interrupts & (ULL(1) << i)) {
596                // See table 4-19 of 21164 hardware reference
597                ipl = i;
598                summary |= (ULL(1) << i);
599            }
600        }
601
602        if (ipr[TheISA::IPR_ASTRR])
603            panic("asynchronous traps not implemented\n");
604
605        if (ipl && ipl > xc->regs.ipr[TheISA::IPR_IPLR]) {
606            ipr[TheISA::IPR_ISR] = summary;
607            ipr[TheISA::IPR_INTID] = ipl;
608            xc->ev5_trap(Interrupt_Fault);
609
610            DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
611                    ipr[TheISA::IPR_IPLR], ipl, summary);
612        }
613    }
614#endif
615
616    // maintain $r0 semantics
617    xc->regs.intRegFile[ZeroReg] = 0;
618#ifdef TARGET_ALPHA
619    xc->regs.floatRegFile.d[ZeroReg] = 0.0;
620#endif // TARGET_ALPHA
621
622    if (status() == IcacheMissComplete) {
623        // We've already fetched an instruction and were stalled on an
624        // I-cache miss.  No need to fetch it again.
625
626        setStatus(Running);
627    }
628    else {
629        // Try to fetch an instruction
630
631        // set up memory request for instruction fetch
632#ifdef FULL_SYSTEM
633#define IFETCH_FLAGS(pc)	((pc) & 1) ? PHYSICAL : 0
634#else
635#define IFETCH_FLAGS(pc)	0
636#endif
637
638        memReq->cmd = Read;
639        memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t),
640                     IFETCH_FLAGS(xc->regs.pc));
641
642        fault = xc->translateInstReq(memReq);
643
644        if (fault == No_Fault)
645            fault = xc->mem->read(memReq, inst);
646
647        if (icacheInterface && fault == No_Fault) {
648            memReq->completionEvent = NULL;
649
650            memReq->time = curTick;
651            memReq->flags &= ~UNCACHEABLE;
652            MemAccessResult result = icacheInterface->access(memReq);
653
654            // Ugly hack to get an event scheduled *only* if the access is
655            // a miss.  We really should add first-class support for this
656            // at some point.
657            if (result != MA_HIT && icacheInterface->doEvents) {
658                memReq->completionEvent = &cacheCompletionEvent;
659                setStatus(IcacheMissStall);
660                return;
661            }
662        }
663    }
664
665    // If we've got a valid instruction (i.e., no fault on instruction
666    // fetch), then execute it.
667    if (fault == No_Fault) {
668
669        // keep an instruction count
670        numInst++;
671
672        // check for instruction-count-based events
673        comInsnEventQueue[0]->serviceEvents(numInst);
674
675        // decode the instruction
676        StaticInstPtr<TheISA> si(inst);
677
678        traceData = Trace::getInstRecord(curTick, xc, this, si,
679                                         xc->regs.pc);
680
681#ifdef FULL_SYSTEM
682        xc->regs.opcode = (inst >> 26) & 0x3f;
683        xc->regs.ra = (inst >> 21) & 0x1f;
684#endif // FULL_SYSTEM
685
686        xc->func_exe_insn++;
687
688        fault = si->execute(this, xc, traceData);
689#ifdef FS_MEASURE
690        if (!(xc->misspeculating()) && (xc->system->bin)) {
691            SWContext *ctx = xc->swCtx;
692            if (ctx && !ctx->callStack.empty()) {
693                if (si->isCall()) {
694                    ctx->calls++;
695                }
696                if (si->isReturn()) {
697                     if (ctx->calls == 0) {
698                        fnCall *top = ctx->callStack.top();
699                        DPRINTF(TCPIP, "Removing %s from callstack.\n", top->name);
700                        delete top;
701                        ctx->callStack.pop();
702                        if (ctx->callStack.empty())
703                            xc->system->nonPath->activate();
704                        else
705                            ctx->callStack.top()->myBin->activate();
706
707                        xc->system->dumpState(xc);
708                    } else {
709                        ctx->calls--;
710                    }
711                }
712            }
713        }
714#endif
715        if (si->isMemRef()) {
716            numMemRefs++;
717        }
718
719        if (si->isLoad()) {
720            ++numLoad;
721            comLoadEventQueue[0]->serviceEvents(numLoad);
722        }
723
724        if (traceData)
725            traceData->finalize();
726
727    }	// if (fault == No_Fault)
728
729    if (fault != No_Fault) {
730#ifdef FULL_SYSTEM
731        xc->ev5_trap(fault);
732#else // !FULL_SYSTEM
733        fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc);
734#endif // FULL_SYSTEM
735    }
736    else {
737        // go to the next instruction
738        xc->regs.pc = xc->regs.npc;
739        xc->regs.npc += sizeof(MachInst);
740    }
741
742#ifdef FULL_SYSTEM
743    Addr oldpc;
744    do {
745        oldpc = xc->regs.pc;
746        system->pcEventQueue.service(xc);
747    } while (oldpc != xc->regs.pc);
748#endif
749
750    assert(status() == Running ||
751           status() == Idle ||
752           status() == DcacheMissStall);
753
754    if (status() == Running && !tickEvent.scheduled())
755        tickEvent.schedule(curTick + 1);
756}
757
758
759////////////////////////////////////////////////////////////////////////
760//
761//  SimpleCPU Simulation Object
762//
763BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
764
765    Param<Counter> max_insts_any_thread;
766    Param<Counter> max_insts_all_threads;
767    Param<Counter> max_loads_any_thread;
768    Param<Counter> max_loads_all_threads;
769
770#ifdef FULL_SYSTEM
771    SimObjectParam<AlphaItb *> itb;
772    SimObjectParam<AlphaDtb *> dtb;
773    SimObjectParam<FunctionalMemory *> mem;
774    SimObjectParam<System *> system;
775    Param<int> mult;
776#else
777    SimObjectParam<Process *> workload;
778#endif // FULL_SYSTEM
779
780    SimObjectParam<BaseMem *> icache;
781    SimObjectParam<BaseMem *> dcache;
782
783    Param<bool> defer_registration;
784
785END_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
786
787BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
788
789    INIT_PARAM_DFLT(max_insts_any_thread,
790                    "terminate when any thread reaches this insn count",
791                    0),
792    INIT_PARAM_DFLT(max_insts_all_threads,
793                    "terminate when all threads have reached this insn count",
794                    0),
795    INIT_PARAM_DFLT(max_loads_any_thread,
796                    "terminate when any thread reaches this load count",
797                    0),
798    INIT_PARAM_DFLT(max_loads_all_threads,
799                    "terminate when all threads have reached this load count",
800                    0),
801
802#ifdef FULL_SYSTEM
803    INIT_PARAM(itb, "Instruction TLB"),
804    INIT_PARAM(dtb, "Data TLB"),
805    INIT_PARAM(mem, "memory"),
806    INIT_PARAM(system, "system object"),
807    INIT_PARAM_DFLT(mult, "system clock multiplier", 1),
808#else
809    INIT_PARAM(workload, "processes to run"),
810#endif // FULL_SYSTEM
811
812    INIT_PARAM_DFLT(icache, "L1 instruction cache object", NULL),
813    INIT_PARAM_DFLT(dcache, "L1 data cache object", NULL),
814    INIT_PARAM_DFLT(defer_registration, "defer registration with system "
815                    "(for sampling)", false)
816
817END_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
818
819
820CREATE_SIM_OBJECT(SimpleCPU)
821{
822    SimpleCPU *cpu;
823#ifdef FULL_SYSTEM
824    if (mult != 1)
825        panic("processor clock multiplier must be 1\n");
826
827    cpu = new SimpleCPU(getInstanceName(), system,
828                        max_insts_any_thread, max_insts_all_threads,
829                        max_loads_any_thread, max_loads_all_threads,
830                        itb, dtb, mem,
831                        (icache) ? icache->getInterface() : NULL,
832                        (dcache) ? dcache->getInterface() : NULL,
833                        ticksPerSecond * mult);
834#else
835
836    cpu = new SimpleCPU(getInstanceName(), workload,
837                        max_insts_any_thread, max_insts_all_threads,
838                        max_loads_any_thread, max_loads_all_threads,
839                        (icache) ? icache->getInterface() : NULL,
840                        (dcache) ? dcache->getInterface() : NULL);
841
842#endif // FULL_SYSTEM
843
844    if (!defer_registration) {
845        cpu->registerExecContexts();
846    }
847
848    return cpu;
849}
850
851REGISTER_SIM_OBJECT("SimpleCPU", SimpleCPU)
852