base.cc revision 2935
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292SN/A */ 302SN/A 312439SN/A#include "arch/utility.hh" 32146SN/A#include "base/cprintf.hh" 33146SN/A#include "base/inifile.hh" 34146SN/A#include "base/loader/symtab.hh" 35146SN/A#include "base/misc.hh" 36146SN/A#include "base/pollevent.hh" 37146SN/A#include "base/range.hh" 381717SN/A#include "base/stats/events.hh" 39146SN/A#include "base/trace.hh" 401717SN/A#include "cpu/base.hh" 41146SN/A#include "cpu/exetrace.hh" 421977SN/A#include "cpu/profile.hh" 432623SN/A#include "cpu/simple/base.hh" 442683Sktlim@umich.edu#include "cpu/simple_thread.hh" 451717SN/A#include "cpu/smt.hh" 46146SN/A#include "cpu/static_inst.hh" 472683Sktlim@umich.edu#include "cpu/thread_context.hh" 481917SN/A#include "kern/kernel_stats.hh" 492592SN/A#include "mem/packet_impl.hh" 502683Sktlim@umich.edu#include "sim/builder.hh" 512036SN/A#include "sim/byteswap.hh" 52146SN/A#include "sim/debug.hh" 5356SN/A#include "sim/host.hh" 5456SN/A#include "sim/sim_events.hh" 5556SN/A#include "sim/sim_object.hh" 56695SN/A#include "sim/stats.hh" 572901Ssaidi@eecs.umich.edu#include "sim/system.hh" 582SN/A 591858SN/A#if FULL_SYSTEM 6056SN/A#include "base/remote_gdb.hh" 612171SN/A#include "arch/tlb.hh" 622170SN/A#include "arch/stacktrace.hh" 632170SN/A#include "arch/vtophys.hh" 64146SN/A#else // !FULL_SYSTEM 652462SN/A#include "mem/mem_object.hh" 66146SN/A#endif // FULL_SYSTEM 672SN/A 682SN/Ausing namespace std; 692449SN/Ausing namespace TheISA; 701355SN/A 712623SN/ABaseSimpleCPU::BaseSimpleCPU(Params *p) 722683Sktlim@umich.edu : BaseCPU(p), mem(p->mem), thread(NULL) 73224SN/A{ 741858SN/A#if FULL_SYSTEM 752683Sktlim@umich.edu thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb); 762420SN/A#else 772683Sktlim@umich.edu thread = new SimpleThread(this, /* thread_num */ 0, p->process, 782520SN/A /* asid */ 0, mem); 792420SN/A#endif // !FULL_SYSTEM 802SN/A 812683Sktlim@umich.edu thread->setStatus(ThreadContext::Suspended); 822672Sktlim@umich.edu 832683Sktlim@umich.edu tc = thread->getTC(); 842SN/A 852SN/A numInst = 0; 86334SN/A startNumInst = 0; 87140SN/A numLoad = 0; 88334SN/A startNumLoad = 0; 892SN/A lastIcacheStall = 0; 902SN/A lastDcacheStall = 0; 912SN/A 922680Sktlim@umich.edu threadContexts.push_back(tc); 932SN/A} 942SN/A 952623SN/ABaseSimpleCPU::~BaseSimpleCPU() 962SN/A{ 972SN/A} 982SN/A 99180SN/Avoid 1002623SN/ABaseSimpleCPU::deallocateContext(int thread_num) 101393SN/A{ 102393SN/A // for now, these are equivalent 103393SN/A suspendContext(thread_num); 104393SN/A} 105384SN/A 106384SN/A 107393SN/Avoid 1082623SN/ABaseSimpleCPU::haltContext(int thread_num) 109393SN/A{ 110393SN/A // for now, these are equivalent 111393SN/A suspendContext(thread_num); 112393SN/A} 113384SN/A 114189SN/A 115189SN/Avoid 1162623SN/ABaseSimpleCPU::regStats() 1172SN/A{ 118729SN/A using namespace Stats; 119334SN/A 1202SN/A BaseCPU::regStats(); 1212SN/A 1222SN/A numInsts 1232SN/A .name(name() + ".num_insts") 1242SN/A .desc("Number of instructions executed") 1252SN/A ; 1262SN/A 1272SN/A numMemRefs 1282SN/A .name(name() + ".num_refs") 1292SN/A .desc("Number of memory references") 1302SN/A ; 1312SN/A 1321001SN/A notIdleFraction 1331001SN/A .name(name() + ".not_idle_fraction") 1341001SN/A .desc("Percentage of non-idle cycles") 1351001SN/A ; 1361001SN/A 1372SN/A idleFraction 1382SN/A .name(name() + ".idle_fraction") 1392SN/A .desc("Percentage of idle cycles") 1402SN/A ; 1412SN/A 1422SN/A icacheStallCycles 1432SN/A .name(name() + ".icache_stall_cycles") 1442SN/A .desc("ICache total stall cycles") 1452SN/A .prereq(icacheStallCycles) 1462SN/A ; 1472SN/A 1482SN/A dcacheStallCycles 1492SN/A .name(name() + ".dcache_stall_cycles") 1502SN/A .desc("DCache total stall cycles") 1512SN/A .prereq(dcacheStallCycles) 1522SN/A ; 1532SN/A 1542390SN/A icacheRetryCycles 1552390SN/A .name(name() + ".icache_retry_cycles") 1562390SN/A .desc("ICache total retry cycles") 1572390SN/A .prereq(icacheRetryCycles) 1582390SN/A ; 1592390SN/A 1602390SN/A dcacheRetryCycles 1612390SN/A .name(name() + ".dcache_retry_cycles") 1622390SN/A .desc("DCache total retry cycles") 1632390SN/A .prereq(dcacheRetryCycles) 1642390SN/A ; 1652390SN/A 166385SN/A idleFraction = constant(1.0) - notIdleFraction; 1672SN/A} 1682SN/A 1692SN/Avoid 1702623SN/ABaseSimpleCPU::resetStats() 171334SN/A{ 172334SN/A startNumInst = numInst; 1732623SN/A // notIdleFraction = (_status != Idle); 174334SN/A} 175334SN/A 176334SN/Avoid 1772623SN/ABaseSimpleCPU::serialize(ostream &os) 1782SN/A{ 179921SN/A BaseCPU::serialize(os); 1802915Sktlim@umich.edu// SERIALIZE_SCALAR(inst); 1812915Sktlim@umich.edu nameOut(os, csprintf("%s.xc.0", name())); 1822683Sktlim@umich.edu thread->serialize(os); 1832SN/A} 1842SN/A 1852SN/Avoid 1862623SN/ABaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1872SN/A{ 188921SN/A BaseCPU::unserialize(cp, section); 1892915Sktlim@umich.edu// UNSERIALIZE_SCALAR(inst); 1902915Sktlim@umich.edu thread->unserialize(cp, csprintf("%s.xc.0", section)); 1912SN/A} 1922SN/A 1932SN/Avoid 1942SN/Achange_thread_state(int thread_number, int activate, int priority) 1952SN/A{ 1962SN/A} 1972SN/A 198595SN/AFault 1992623SN/ABaseSimpleCPU::copySrcTranslate(Addr src) 200595SN/A{ 2012390SN/A#if 0 2021080SN/A static bool no_warn = true; 2031080SN/A int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 2041080SN/A // Only support block sizes of 64 atm. 2051080SN/A assert(blk_size == 64); 2061080SN/A int offset = src & (blk_size - 1); 2071080SN/A 2081080SN/A // Make sure block doesn't span page 2091121SN/A if (no_warn && 2102107SN/A (src & PageMask) != ((src + blk_size) & PageMask) && 2111089SN/A (src >> 40) != 0xfffffc) { 2121089SN/A warn("Copied block source spans pages %x.", src); 2131080SN/A no_warn = false; 2141080SN/A } 2151080SN/A 2161080SN/A memReq->reset(src & ~(blk_size - 1), blk_size); 217595SN/A 2182623SN/A // translate to physical address 2192683Sktlim@umich.edu Fault fault = thread->translateDataReadReq(req); 220595SN/A 2212090SN/A if (fault == NoFault) { 2222683Sktlim@umich.edu thread->copySrcAddr = src; 2232683Sktlim@umich.edu thread->copySrcPhysAddr = memReq->paddr + offset; 224595SN/A } else { 2252205SN/A assert(!fault->isAlignmentFault()); 2262205SN/A 2272683Sktlim@umich.edu thread->copySrcAddr = 0; 2282683Sktlim@umich.edu thread->copySrcPhysAddr = 0; 229595SN/A } 230595SN/A return fault; 2312390SN/A#else 2322423SN/A return NoFault; 2332390SN/A#endif 234595SN/A} 235595SN/A 236595SN/AFault 2372623SN/ABaseSimpleCPU::copy(Addr dest) 238595SN/A{ 2392390SN/A#if 0 2401080SN/A static bool no_warn = true; 241595SN/A int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 2421080SN/A // Only support block sizes of 64 atm. 2431080SN/A assert(blk_size == 64); 244595SN/A uint8_t data[blk_size]; 2452683Sktlim@umich.edu //assert(thread->copySrcAddr); 2461080SN/A int offset = dest & (blk_size - 1); 2471080SN/A 2481080SN/A // Make sure block doesn't span page 2491121SN/A if (no_warn && 2502107SN/A (dest & PageMask) != ((dest + blk_size) & PageMask) && 2511089SN/A (dest >> 40) != 0xfffffc) { 2521080SN/A no_warn = false; 2531089SN/A warn("Copied block destination spans pages %x. ", dest); 2541080SN/A } 2551080SN/A 2561080SN/A memReq->reset(dest & ~(blk_size -1), blk_size); 257595SN/A // translate to physical address 2582683Sktlim@umich.edu Fault fault = thread->translateDataWriteReq(req); 2591080SN/A 2602090SN/A if (fault == NoFault) { 2611080SN/A Addr dest_addr = memReq->paddr + offset; 262595SN/A // Need to read straight from memory since we have more than 8 bytes. 2632683Sktlim@umich.edu memReq->paddr = thread->copySrcPhysAddr; 2642683Sktlim@umich.edu thread->mem->read(memReq, data); 265595SN/A memReq->paddr = dest_addr; 2662683Sktlim@umich.edu thread->mem->write(memReq, data); 2671098SN/A if (dcacheInterface) { 2681098SN/A memReq->cmd = Copy; 2691098SN/A memReq->completionEvent = NULL; 2702683Sktlim@umich.edu memReq->paddr = thread->copySrcPhysAddr; 2711098SN/A memReq->dest = dest_addr; 2721098SN/A memReq->size = 64; 2731098SN/A memReq->time = curTick; 2742012SN/A memReq->flags &= ~INST_READ; 2751098SN/A dcacheInterface->access(memReq); 2761098SN/A } 277595SN/A } 2782205SN/A else 2792205SN/A assert(!fault->isAlignmentFault()); 2802205SN/A 281595SN/A return fault; 2822390SN/A#else 2832420SN/A panic("copy not implemented"); 2842423SN/A return NoFault; 2852390SN/A#endif 286595SN/A} 287595SN/A 2881858SN/A#if FULL_SYSTEM 2892SN/AAddr 2902623SN/ABaseSimpleCPU::dbg_vtophys(Addr addr) 2912SN/A{ 2922680Sktlim@umich.edu return vtophys(tc, addr); 2932SN/A} 2942SN/A#endif // FULL_SYSTEM 2952SN/A 2961858SN/A#if FULL_SYSTEM 2972SN/Avoid 2982623SN/ABaseSimpleCPU::post_interrupt(int int_num, int index) 2992SN/A{ 3002SN/A BaseCPU::post_interrupt(int_num, index); 3012SN/A 3022683Sktlim@umich.edu if (thread->status() == ThreadContext::Suspended) { 3032SN/A DPRINTF(IPI,"Suspended Processor awoke\n"); 3042683Sktlim@umich.edu thread->activate(); 3052SN/A } 3062SN/A} 3072SN/A#endif // FULL_SYSTEM 3082SN/A 3092SN/Avoid 3102623SN/ABaseSimpleCPU::checkForInterrupts() 3112SN/A{ 3121858SN/A#if FULL_SYSTEM 3132683Sktlim@umich.edu if (checkInterrupts && check_interrupts() && !thread->inPalMode()) { 3142SN/A int ipl = 0; 3152SN/A int summary = 0; 3161133SN/A checkInterrupts = false; 3172SN/A 3182683Sktlim@umich.edu if (thread->readMiscReg(IPR_SIRR)) { 3192107SN/A for (int i = INTLEVEL_SOFTWARE_MIN; 3202107SN/A i < INTLEVEL_SOFTWARE_MAX; i++) { 3212683Sktlim@umich.edu if (thread->readMiscReg(IPR_SIRR) & (ULL(1) << i)) { 3222SN/A // See table 4-19 of 21164 hardware reference 3232107SN/A ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; 3242SN/A summary |= (ULL(1) << i); 3252SN/A } 3262SN/A } 3272SN/A } 3282SN/A 3292683Sktlim@umich.edu uint64_t interrupts = thread->cpu->intr_status(); 3302107SN/A for (int i = INTLEVEL_EXTERNAL_MIN; 3312107SN/A i < INTLEVEL_EXTERNAL_MAX; i++) { 3322SN/A if (interrupts & (ULL(1) << i)) { 3332SN/A // See table 4-19 of 21164 hardware reference 3342SN/A ipl = i; 3352SN/A summary |= (ULL(1) << i); 3362SN/A } 3372SN/A } 3382SN/A 3392683Sktlim@umich.edu if (thread->readMiscReg(IPR_ASTRR)) 3402SN/A panic("asynchronous traps not implemented\n"); 3412SN/A 3422683Sktlim@umich.edu if (ipl && ipl > thread->readMiscReg(IPR_IPLR)) { 3432683Sktlim@umich.edu thread->setMiscReg(IPR_ISR, summary); 3442683Sktlim@umich.edu thread->setMiscReg(IPR_INTID, ipl); 3452234SN/A 3462680Sktlim@umich.edu Fault(new InterruptFault)->invoke(tc); 3472SN/A 3482SN/A DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", 3492683Sktlim@umich.edu thread->readMiscReg(IPR_IPLR), ipl, summary); 3502SN/A } 3512SN/A } 3522SN/A#endif 3532623SN/A} 3542SN/A 3552623SN/A 3562623SN/AFault 3572662Sstever@eecs.umich.eduBaseSimpleCPU::setupFetchRequest(Request *req) 3582623SN/A{ 3592623SN/A // set up memory request for instruction fetch 3602741Sksewell@umich.edu#if THE_ISA == ALPHA_ISA 3612741Sksewell@umich.edu DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",thread->readPC(), 3622741Sksewell@umich.edu thread->readNextPC()); 3632741Sksewell@umich.edu#else 3642683Sktlim@umich.edu DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",thread->readPC(), 3652683Sktlim@umich.edu thread->readNextPC(),thread->readNextNPC()); 3662741Sksewell@umich.edu#endif 3672623SN/A 3682683Sktlim@umich.edu req->setVirt(0, thread->readPC() & ~3, sizeof(MachInst), 3692683Sktlim@umich.edu (FULL_SYSTEM && (thread->readPC() & 1)) ? PHYSICAL : 0, 3702683Sktlim@umich.edu thread->readPC()); 3712623SN/A 3722683Sktlim@umich.edu Fault fault = thread->translateInstReq(req); 3732623SN/A 3742623SN/A return fault; 3752623SN/A} 3762623SN/A 3772623SN/A 3782623SN/Avoid 3792623SN/ABaseSimpleCPU::preExecute() 3802623SN/A{ 3812SN/A // maintain $r0 semantics 3822683Sktlim@umich.edu thread->setIntReg(ZeroReg, 0); 3832427SN/A#if THE_ISA == ALPHA_ISA 3842683Sktlim@umich.edu thread->setFloatReg(ZeroReg, 0.0); 3852427SN/A#endif // ALPHA_ISA 3862SN/A 3872623SN/A // keep an instruction count 3882623SN/A numInst++; 3892623SN/A numInsts++; 3902SN/A 3912683Sktlim@umich.edu thread->funcExeInst++; 3922SN/A 3932623SN/A // check for instruction-count-based events 3942623SN/A comInstEventQueue[0]->serviceEvents(numInst); 3952SN/A 3962623SN/A // decode the instruction 3972623SN/A inst = gtoh(inst); 3982683Sktlim@umich.edu curStaticInst = StaticInst::decode(makeExtMI(inst, thread->readPC())); 3992470SN/A 4002680Sktlim@umich.edu traceData = Trace::getInstRecord(curTick, tc, this, curStaticInst, 4012683Sktlim@umich.edu thread->readPC()); 4022623SN/A 4032623SN/A DPRINTF(Decode,"Decode: Decoded %s instruction (opcode: 0x%x): 0x%x\n", 4042623SN/A curStaticInst->getName(), curStaticInst->getOpcode(), 4052623SN/A curStaticInst->machInst); 4062623SN/A 4072623SN/A#if FULL_SYSTEM 4082683Sktlim@umich.edu thread->setInst(inst); 4092623SN/A#endif // FULL_SYSTEM 4102623SN/A} 4112623SN/A 4122623SN/Avoid 4132623SN/ABaseSimpleCPU::postExecute() 4142623SN/A{ 4152623SN/A#if FULL_SYSTEM 4162683Sktlim@umich.edu if (thread->profile) { 4172623SN/A bool usermode = 4182683Sktlim@umich.edu (thread->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; 4192683Sktlim@umich.edu thread->profilePC = usermode ? 1 : thread->readPC(); 4202683Sktlim@umich.edu ProfileNode *node = thread->profile->consume(tc, inst); 4212623SN/A if (node) 4222683Sktlim@umich.edu thread->profileNode = node; 4232623SN/A } 4242420SN/A#endif 4252SN/A 4262623SN/A if (curStaticInst->isMemRef()) { 4272623SN/A numMemRefs++; 4282SN/A } 4292SN/A 4302623SN/A if (curStaticInst->isLoad()) { 4312623SN/A ++numLoad; 4322623SN/A comLoadEventQueue[0]->serviceEvents(numLoad); 4332623SN/A } 4342SN/A 4352683Sktlim@umich.edu traceFunctions(thread->readPC()); 4362644Sstever@eecs.umich.edu 4372644Sstever@eecs.umich.edu if (traceData) { 4382644Sstever@eecs.umich.edu traceData->finalize(); 4392644Sstever@eecs.umich.edu } 4402623SN/A} 4412SN/A 4422SN/A 4432623SN/Avoid 4442623SN/ABaseSimpleCPU::advancePC(Fault fault) 4452623SN/A{ 4462090SN/A if (fault != NoFault) { 4472680Sktlim@umich.edu fault->invoke(tc); 4482SN/A } 4492SN/A else { 4502SN/A // go to the next instruction 4512683Sktlim@umich.edu thread->setPC(thread->readNextPC()); 4522623SN/A#if THE_ISA == ALPHA_ISA 4532683Sktlim@umich.edu thread->setNextPC(thread->readNextPC() + sizeof(MachInst)); 4542251SN/A#else 4552683Sktlim@umich.edu thread->setNextPC(thread->readNextNPC()); 4562683Sktlim@umich.edu thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst)); 4572935Sksewell@umich.edu assert(thread->readNextPC() != thread->readNextNPC()); 4582251SN/A#endif 4592251SN/A 4602SN/A } 4612SN/A 4621858SN/A#if FULL_SYSTEM 4632SN/A Addr oldpc; 4642SN/A do { 4652683Sktlim@umich.edu oldpc = thread->readPC(); 4662680Sktlim@umich.edu system->pcEventQueue.service(tc); 4672683Sktlim@umich.edu } while (oldpc != thread->readPC()); 4682SN/A#endif 4692SN/A} 4702SN/A 471