base.cc revision 2741
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292741Sksewell@umich.edu * Korey Sewell 302SN/A */ 312SN/A 322439SN/A#include "arch/utility.hh" 33146SN/A#include "base/cprintf.hh" 34146SN/A#include "base/inifile.hh" 35146SN/A#include "base/loader/symtab.hh" 36146SN/A#include "base/misc.hh" 37146SN/A#include "base/pollevent.hh" 38146SN/A#include "base/range.hh" 391717SN/A#include "base/stats/events.hh" 40146SN/A#include "base/trace.hh" 411717SN/A#include "cpu/base.hh" 42146SN/A#include "cpu/exetrace.hh" 431977SN/A#include "cpu/profile.hh" 441717SN/A#include "cpu/sampler/sampler.hh" 452623SN/A#include "cpu/simple/base.hh" 462683Sktlim@umich.edu#include "cpu/simple_thread.hh" 471717SN/A#include "cpu/smt.hh" 48146SN/A#include "cpu/static_inst.hh" 492683Sktlim@umich.edu#include "cpu/thread_context.hh" 501917SN/A#include "kern/kernel_stats.hh" 512592SN/A#include "mem/packet_impl.hh" 522683Sktlim@umich.edu#include "sim/builder.hh" 532036SN/A#include "sim/byteswap.hh" 54146SN/A#include "sim/debug.hh" 5556SN/A#include "sim/host.hh" 5656SN/A#include "sim/sim_events.hh" 5756SN/A#include "sim/sim_object.hh" 58695SN/A#include "sim/stats.hh" 592SN/A 601858SN/A#if FULL_SYSTEM 6156SN/A#include "base/remote_gdb.hh" 62146SN/A#include "sim/system.hh" 632171SN/A#include "arch/tlb.hh" 642170SN/A#include "arch/stacktrace.hh" 652170SN/A#include "arch/vtophys.hh" 66146SN/A#else // !FULL_SYSTEM 672462SN/A#include "mem/mem_object.hh" 68146SN/A#endif // FULL_SYSTEM 692SN/A 702SN/Ausing namespace std; 712449SN/Ausing namespace TheISA; 721355SN/A 732623SN/ABaseSimpleCPU::BaseSimpleCPU(Params *p) 742683Sktlim@umich.edu : BaseCPU(p), mem(p->mem), thread(NULL) 75224SN/A{ 761858SN/A#if FULL_SYSTEM 772683Sktlim@umich.edu thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb); 782420SN/A#else 792683Sktlim@umich.edu thread = new SimpleThread(this, /* thread_num */ 0, p->process, 802520SN/A /* asid */ 0, mem); 812420SN/A#endif // !FULL_SYSTEM 822SN/A 832683Sktlim@umich.edu thread->setStatus(ThreadContext::Suspended); 842672Sktlim@umich.edu 852683Sktlim@umich.edu tc = thread->getTC(); 862SN/A 872SN/A numInst = 0; 88334SN/A startNumInst = 0; 89140SN/A numLoad = 0; 90334SN/A startNumLoad = 0; 912SN/A lastIcacheStall = 0; 922SN/A lastDcacheStall = 0; 932SN/A 942680Sktlim@umich.edu threadContexts.push_back(tc); 952SN/A} 962SN/A 972623SN/ABaseSimpleCPU::~BaseSimpleCPU() 982SN/A{ 992SN/A} 1002SN/A 101180SN/Avoid 1022623SN/ABaseSimpleCPU::deallocateContext(int thread_num) 103393SN/A{ 104393SN/A // for now, these are equivalent 105393SN/A suspendContext(thread_num); 106393SN/A} 107384SN/A 108384SN/A 109393SN/Avoid 1102623SN/ABaseSimpleCPU::haltContext(int thread_num) 111393SN/A{ 112393SN/A // for now, these are equivalent 113393SN/A suspendContext(thread_num); 114393SN/A} 115384SN/A 116189SN/A 117189SN/Avoid 1182623SN/ABaseSimpleCPU::regStats() 1192SN/A{ 120729SN/A using namespace Stats; 121334SN/A 1222SN/A BaseCPU::regStats(); 1232SN/A 1242SN/A numInsts 1252SN/A .name(name() + ".num_insts") 1262SN/A .desc("Number of instructions executed") 1272SN/A ; 1282SN/A 1292SN/A numMemRefs 1302SN/A .name(name() + ".num_refs") 1312SN/A .desc("Number of memory references") 1322SN/A ; 1332SN/A 1341001SN/A notIdleFraction 1351001SN/A .name(name() + ".not_idle_fraction") 1361001SN/A .desc("Percentage of non-idle cycles") 1371001SN/A ; 1381001SN/A 1392SN/A idleFraction 1402SN/A .name(name() + ".idle_fraction") 1412SN/A .desc("Percentage of idle cycles") 1422SN/A ; 1432SN/A 1442SN/A icacheStallCycles 1452SN/A .name(name() + ".icache_stall_cycles") 1462SN/A .desc("ICache total stall cycles") 1472SN/A .prereq(icacheStallCycles) 1482SN/A ; 1492SN/A 1502SN/A dcacheStallCycles 1512SN/A .name(name() + ".dcache_stall_cycles") 1522SN/A .desc("DCache total stall cycles") 1532SN/A .prereq(dcacheStallCycles) 1542SN/A ; 1552SN/A 1562390SN/A icacheRetryCycles 1572390SN/A .name(name() + ".icache_retry_cycles") 1582390SN/A .desc("ICache total retry cycles") 1592390SN/A .prereq(icacheRetryCycles) 1602390SN/A ; 1612390SN/A 1622390SN/A dcacheRetryCycles 1632390SN/A .name(name() + ".dcache_retry_cycles") 1642390SN/A .desc("DCache total retry cycles") 1652390SN/A .prereq(dcacheRetryCycles) 1662390SN/A ; 1672390SN/A 168385SN/A idleFraction = constant(1.0) - notIdleFraction; 1692SN/A} 1702SN/A 1712SN/Avoid 1722623SN/ABaseSimpleCPU::resetStats() 173334SN/A{ 174334SN/A startNumInst = numInst; 1752623SN/A // notIdleFraction = (_status != Idle); 176334SN/A} 177334SN/A 178334SN/Avoid 1792623SN/ABaseSimpleCPU::serialize(ostream &os) 1802SN/A{ 181921SN/A BaseCPU::serialize(os); 182224SN/A SERIALIZE_SCALAR(inst); 183237SN/A nameOut(os, csprintf("%s.xc", name())); 1842683Sktlim@umich.edu thread->serialize(os); 1852SN/A} 1862SN/A 1872SN/Avoid 1882623SN/ABaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1892SN/A{ 190921SN/A BaseCPU::unserialize(cp, section); 191224SN/A UNSERIALIZE_SCALAR(inst); 1922683Sktlim@umich.edu thread->unserialize(cp, csprintf("%s.xc", section)); 1932SN/A} 1942SN/A 1952SN/Avoid 1962SN/Achange_thread_state(int thread_number, int activate, int priority) 1972SN/A{ 1982SN/A} 1992SN/A 200595SN/AFault 2012623SN/ABaseSimpleCPU::copySrcTranslate(Addr src) 202595SN/A{ 2032390SN/A#if 0 2041080SN/A static bool no_warn = true; 2051080SN/A int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 2061080SN/A // Only support block sizes of 64 atm. 2071080SN/A assert(blk_size == 64); 2081080SN/A int offset = src & (blk_size - 1); 2091080SN/A 2101080SN/A // Make sure block doesn't span page 2111121SN/A if (no_warn && 2122107SN/A (src & PageMask) != ((src + blk_size) & PageMask) && 2131089SN/A (src >> 40) != 0xfffffc) { 2141089SN/A warn("Copied block source spans pages %x.", src); 2151080SN/A no_warn = false; 2161080SN/A } 2171080SN/A 2181080SN/A memReq->reset(src & ~(blk_size - 1), blk_size); 219595SN/A 2202623SN/A // translate to physical address 2212683Sktlim@umich.edu Fault fault = thread->translateDataReadReq(req); 222595SN/A 2232090SN/A if (fault == NoFault) { 2242683Sktlim@umich.edu thread->copySrcAddr = src; 2252683Sktlim@umich.edu thread->copySrcPhysAddr = memReq->paddr + offset; 226595SN/A } else { 2272205SN/A assert(!fault->isAlignmentFault()); 2282205SN/A 2292683Sktlim@umich.edu thread->copySrcAddr = 0; 2302683Sktlim@umich.edu thread->copySrcPhysAddr = 0; 231595SN/A } 232595SN/A return fault; 2332390SN/A#else 2342423SN/A return NoFault; 2352390SN/A#endif 236595SN/A} 237595SN/A 238595SN/AFault 2392623SN/ABaseSimpleCPU::copy(Addr dest) 240595SN/A{ 2412390SN/A#if 0 2421080SN/A static bool no_warn = true; 243595SN/A int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 2441080SN/A // Only support block sizes of 64 atm. 2451080SN/A assert(blk_size == 64); 246595SN/A uint8_t data[blk_size]; 2472683Sktlim@umich.edu //assert(thread->copySrcAddr); 2481080SN/A int offset = dest & (blk_size - 1); 2491080SN/A 2501080SN/A // Make sure block doesn't span page 2511121SN/A if (no_warn && 2522107SN/A (dest & PageMask) != ((dest + blk_size) & PageMask) && 2531089SN/A (dest >> 40) != 0xfffffc) { 2541080SN/A no_warn = false; 2551089SN/A warn("Copied block destination spans pages %x. ", dest); 2561080SN/A } 2571080SN/A 2581080SN/A memReq->reset(dest & ~(blk_size -1), blk_size); 259595SN/A // translate to physical address 2602683Sktlim@umich.edu Fault fault = thread->translateDataWriteReq(req); 2611080SN/A 2622090SN/A if (fault == NoFault) { 2631080SN/A Addr dest_addr = memReq->paddr + offset; 264595SN/A // Need to read straight from memory since we have more than 8 bytes. 2652683Sktlim@umich.edu memReq->paddr = thread->copySrcPhysAddr; 2662683Sktlim@umich.edu thread->mem->read(memReq, data); 267595SN/A memReq->paddr = dest_addr; 2682683Sktlim@umich.edu thread->mem->write(memReq, data); 2691098SN/A if (dcacheInterface) { 2701098SN/A memReq->cmd = Copy; 2711098SN/A memReq->completionEvent = NULL; 2722683Sktlim@umich.edu memReq->paddr = thread->copySrcPhysAddr; 2731098SN/A memReq->dest = dest_addr; 2741098SN/A memReq->size = 64; 2751098SN/A memReq->time = curTick; 2762012SN/A memReq->flags &= ~INST_READ; 2771098SN/A dcacheInterface->access(memReq); 2781098SN/A } 279595SN/A } 2802205SN/A else 2812205SN/A assert(!fault->isAlignmentFault()); 2822205SN/A 283595SN/A return fault; 2842390SN/A#else 2852420SN/A panic("copy not implemented"); 2862423SN/A return NoFault; 2872390SN/A#endif 288595SN/A} 289595SN/A 2901858SN/A#if FULL_SYSTEM 2912SN/AAddr 2922623SN/ABaseSimpleCPU::dbg_vtophys(Addr addr) 2932SN/A{ 2942680Sktlim@umich.edu return vtophys(tc, addr); 2952SN/A} 2962SN/A#endif // FULL_SYSTEM 2972SN/A 2981858SN/A#if FULL_SYSTEM 2992SN/Avoid 3002623SN/ABaseSimpleCPU::post_interrupt(int int_num, int index) 3012SN/A{ 3022SN/A BaseCPU::post_interrupt(int_num, index); 3032SN/A 3042683Sktlim@umich.edu if (thread->status() == ThreadContext::Suspended) { 3052SN/A DPRINTF(IPI,"Suspended Processor awoke\n"); 3062683Sktlim@umich.edu thread->activate(); 3072SN/A } 3082SN/A} 3092SN/A#endif // FULL_SYSTEM 3102SN/A 3112SN/Avoid 3122623SN/ABaseSimpleCPU::checkForInterrupts() 3132SN/A{ 3141858SN/A#if FULL_SYSTEM 3152683Sktlim@umich.edu if (checkInterrupts && check_interrupts() && !thread->inPalMode()) { 3162SN/A int ipl = 0; 3172SN/A int summary = 0; 3181133SN/A checkInterrupts = false; 3192SN/A 3202683Sktlim@umich.edu if (thread->readMiscReg(IPR_SIRR)) { 3212107SN/A for (int i = INTLEVEL_SOFTWARE_MIN; 3222107SN/A i < INTLEVEL_SOFTWARE_MAX; i++) { 3232683Sktlim@umich.edu if (thread->readMiscReg(IPR_SIRR) & (ULL(1) << i)) { 3242SN/A // See table 4-19 of 21164 hardware reference 3252107SN/A ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; 3262SN/A summary |= (ULL(1) << i); 3272SN/A } 3282SN/A } 3292SN/A } 3302SN/A 3312683Sktlim@umich.edu uint64_t interrupts = thread->cpu->intr_status(); 3322107SN/A for (int i = INTLEVEL_EXTERNAL_MIN; 3332107SN/A i < INTLEVEL_EXTERNAL_MAX; i++) { 3342SN/A if (interrupts & (ULL(1) << i)) { 3352SN/A // See table 4-19 of 21164 hardware reference 3362SN/A ipl = i; 3372SN/A summary |= (ULL(1) << i); 3382SN/A } 3392SN/A } 3402SN/A 3412683Sktlim@umich.edu if (thread->readMiscReg(IPR_ASTRR)) 3422SN/A panic("asynchronous traps not implemented\n"); 3432SN/A 3442683Sktlim@umich.edu if (ipl && ipl > thread->readMiscReg(IPR_IPLR)) { 3452683Sktlim@umich.edu thread->setMiscReg(IPR_ISR, summary); 3462683Sktlim@umich.edu thread->setMiscReg(IPR_INTID, ipl); 3472234SN/A 3482680Sktlim@umich.edu Fault(new InterruptFault)->invoke(tc); 3492SN/A 3502SN/A DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", 3512683Sktlim@umich.edu thread->readMiscReg(IPR_IPLR), ipl, summary); 3522SN/A } 3532SN/A } 3542SN/A#endif 3552623SN/A} 3562SN/A 3572623SN/A 3582623SN/AFault 3592662Sstever@eecs.umich.eduBaseSimpleCPU::setupFetchRequest(Request *req) 3602623SN/A{ 3612623SN/A // set up memory request for instruction fetch 3622741Sksewell@umich.edu#if THE_ISA == ALPHA_ISA 3632741Sksewell@umich.edu DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",thread->readPC(), 3642741Sksewell@umich.edu thread->readNextPC()); 3652741Sksewell@umich.edu#else 3662683Sktlim@umich.edu DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",thread->readPC(), 3672683Sktlim@umich.edu thread->readNextPC(),thread->readNextNPC()); 3682741Sksewell@umich.edu#endif 3692623SN/A 3702683Sktlim@umich.edu req->setVirt(0, thread->readPC() & ~3, sizeof(MachInst), 3712683Sktlim@umich.edu (FULL_SYSTEM && (thread->readPC() & 1)) ? PHYSICAL : 0, 3722683Sktlim@umich.edu thread->readPC()); 3732623SN/A 3742683Sktlim@umich.edu Fault fault = thread->translateInstReq(req); 3752623SN/A 3762623SN/A return fault; 3772623SN/A} 3782623SN/A 3792623SN/A 3802623SN/Avoid 3812623SN/ABaseSimpleCPU::preExecute() 3822623SN/A{ 3832SN/A // maintain $r0 semantics 3842683Sktlim@umich.edu thread->setIntReg(ZeroReg, 0); 3852427SN/A#if THE_ISA == ALPHA_ISA 3862683Sktlim@umich.edu thread->setFloatReg(ZeroReg, 0.0); 3872427SN/A#endif // ALPHA_ISA 3882SN/A 3892623SN/A // keep an instruction count 3902623SN/A numInst++; 3912623SN/A numInsts++; 3922SN/A 3932683Sktlim@umich.edu thread->funcExeInst++; 3942SN/A 3952623SN/A // check for instruction-count-based events 3962623SN/A comInstEventQueue[0]->serviceEvents(numInst); 3972SN/A 3982623SN/A // decode the instruction 3992623SN/A inst = gtoh(inst); 4002683Sktlim@umich.edu curStaticInst = StaticInst::decode(makeExtMI(inst, thread->readPC())); 4012470SN/A 4022680Sktlim@umich.edu traceData = Trace::getInstRecord(curTick, tc, this, curStaticInst, 4032683Sktlim@umich.edu thread->readPC()); 4042623SN/A 4052623SN/A DPRINTF(Decode,"Decode: Decoded %s instruction (opcode: 0x%x): 0x%x\n", 4062623SN/A curStaticInst->getName(), curStaticInst->getOpcode(), 4072623SN/A curStaticInst->machInst); 4082623SN/A 4092623SN/A#if FULL_SYSTEM 4102683Sktlim@umich.edu thread->setInst(inst); 4112623SN/A#endif // FULL_SYSTEM 4122623SN/A} 4132623SN/A 4142623SN/Avoid 4152623SN/ABaseSimpleCPU::postExecute() 4162623SN/A{ 4172623SN/A#if FULL_SYSTEM 4182623SN/A if (system->kernelBinning->fnbin) { 4192683Sktlim@umich.edu assert(thread->getKernelStats()); 4202680Sktlim@umich.edu system->kernelBinning->execute(tc, inst); 4212623SN/A } 4222623SN/A 4232683Sktlim@umich.edu if (thread->profile) { 4242623SN/A bool usermode = 4252683Sktlim@umich.edu (thread->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; 4262683Sktlim@umich.edu thread->profilePC = usermode ? 1 : thread->readPC(); 4272683Sktlim@umich.edu ProfileNode *node = thread->profile->consume(tc, inst); 4282623SN/A if (node) 4292683Sktlim@umich.edu thread->profileNode = node; 4302623SN/A } 4312420SN/A#endif 4322SN/A 4332623SN/A if (curStaticInst->isMemRef()) { 4342623SN/A numMemRefs++; 4352SN/A } 4362SN/A 4372623SN/A if (curStaticInst->isLoad()) { 4382623SN/A ++numLoad; 4392623SN/A comLoadEventQueue[0]->serviceEvents(numLoad); 4402623SN/A } 4412SN/A 4422683Sktlim@umich.edu traceFunctions(thread->readPC()); 4432644Sstever@eecs.umich.edu 4442644Sstever@eecs.umich.edu if (traceData) { 4452644Sstever@eecs.umich.edu traceData->finalize(); 4462644Sstever@eecs.umich.edu } 4472623SN/A} 4482SN/A 4492SN/A 4502623SN/Avoid 4512623SN/ABaseSimpleCPU::advancePC(Fault fault) 4522623SN/A{ 4532090SN/A if (fault != NoFault) { 4541858SN/A#if FULL_SYSTEM 4552680Sktlim@umich.edu fault->invoke(tc); 4562SN/A#else // !FULL_SYSTEM 4572683Sktlim@umich.edu fatal("fault (%s) detected @ PC %08p", fault->name(), thread->readPC()); 4582SN/A#endif // FULL_SYSTEM 4592SN/A } 4602SN/A else { 4612SN/A // go to the next instruction 4622683Sktlim@umich.edu thread->setPC(thread->readNextPC()); 4632623SN/A#if THE_ISA == ALPHA_ISA 4642683Sktlim@umich.edu thread->setNextPC(thread->readNextPC() + sizeof(MachInst)); 4652251SN/A#else 4662683Sktlim@umich.edu thread->setNextPC(thread->readNextNPC()); 4672683Sktlim@umich.edu thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst)); 4682251SN/A#endif 4692251SN/A 4702SN/A } 4712SN/A 4721858SN/A#if FULL_SYSTEM 4732SN/A Addr oldpc; 4742SN/A do { 4752683Sktlim@umich.edu oldpc = thread->readPC(); 4762680Sktlim@umich.edu system->pcEventQueue.service(tc); 4772683Sktlim@umich.edu } while (oldpc != thread->readPC()); 4782SN/A#endif 4792SN/A} 4802SN/A 481