base.cc revision 2680
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292SN/A */ 302SN/A 312439SN/A#include "arch/utility.hh" 32146SN/A#include "base/cprintf.hh" 33146SN/A#include "base/inifile.hh" 34146SN/A#include "base/loader/symtab.hh" 35146SN/A#include "base/misc.hh" 36146SN/A#include "base/pollevent.hh" 37146SN/A#include "base/range.hh" 381717SN/A#include "base/stats/events.hh" 39146SN/A#include "base/trace.hh" 401717SN/A#include "cpu/base.hh" 412190SN/A#include "cpu/cpu_exec_context.hh" 422680Sktlim@umich.edu#include "cpu/thread_context.hh" 43146SN/A#include "cpu/exetrace.hh" 441977SN/A#include "cpu/profile.hh" 451717SN/A#include "cpu/sampler/sampler.hh" 462623SN/A#include "cpu/simple/base.hh" 471717SN/A#include "cpu/smt.hh" 48146SN/A#include "cpu/static_inst.hh" 491917SN/A#include "kern/kernel_stats.hh" 502592SN/A#include "mem/packet_impl.hh" 512036SN/A#include "sim/byteswap.hh" 52146SN/A#include "sim/builder.hh" 53146SN/A#include "sim/debug.hh" 5456SN/A#include "sim/host.hh" 5556SN/A#include "sim/sim_events.hh" 5656SN/A#include "sim/sim_object.hh" 57695SN/A#include "sim/stats.hh" 582SN/A 591858SN/A#if FULL_SYSTEM 6056SN/A#include "base/remote_gdb.hh" 61146SN/A#include "sim/system.hh" 622171SN/A#include "arch/tlb.hh" 632170SN/A#include "arch/stacktrace.hh" 642170SN/A#include "arch/vtophys.hh" 65146SN/A#else // !FULL_SYSTEM 662462SN/A#include "mem/mem_object.hh" 67146SN/A#endif // FULL_SYSTEM 682SN/A 692SN/Ausing namespace std; 702449SN/Ausing namespace TheISA; 711355SN/A 722623SN/ABaseSimpleCPU::BaseSimpleCPU(Params *p) 732623SN/A : BaseCPU(p), mem(p->mem), cpuXC(NULL) 74224SN/A{ 751858SN/A#if FULL_SYSTEM 762518SN/A cpuXC = new CPUExecContext(this, 0, p->system, p->itb, p->dtb); 772420SN/A#else 782519SN/A cpuXC = new CPUExecContext(this, /* thread_num */ 0, p->process, 792520SN/A /* asid */ 0, mem); 802420SN/A#endif // !FULL_SYSTEM 812SN/A 822680Sktlim@umich.edu cpuXC->setStatus(ThreadContext::Suspended); 832672Sktlim@umich.edu 842680Sktlim@umich.edu tc = cpuXC->getTC(); 852SN/A 862SN/A numInst = 0; 87334SN/A startNumInst = 0; 88140SN/A numLoad = 0; 89334SN/A startNumLoad = 0; 902SN/A lastIcacheStall = 0; 912SN/A lastDcacheStall = 0; 922SN/A 932680Sktlim@umich.edu threadContexts.push_back(tc); 942SN/A} 952SN/A 962623SN/ABaseSimpleCPU::~BaseSimpleCPU() 972SN/A{ 982SN/A} 992SN/A 100180SN/Avoid 1012623SN/ABaseSimpleCPU::deallocateContext(int thread_num) 102393SN/A{ 103393SN/A // for now, these are equivalent 104393SN/A suspendContext(thread_num); 105393SN/A} 106384SN/A 107384SN/A 108393SN/Avoid 1092623SN/ABaseSimpleCPU::haltContext(int thread_num) 110393SN/A{ 111393SN/A // for now, these are equivalent 112393SN/A suspendContext(thread_num); 113393SN/A} 114384SN/A 115189SN/A 116189SN/Avoid 1172623SN/ABaseSimpleCPU::regStats() 1182SN/A{ 119729SN/A using namespace Stats; 120334SN/A 1212SN/A BaseCPU::regStats(); 1222SN/A 1232SN/A numInsts 1242SN/A .name(name() + ".num_insts") 1252SN/A .desc("Number of instructions executed") 1262SN/A ; 1272SN/A 1282SN/A numMemRefs 1292SN/A .name(name() + ".num_refs") 1302SN/A .desc("Number of memory references") 1312SN/A ; 1322SN/A 1331001SN/A notIdleFraction 1341001SN/A .name(name() + ".not_idle_fraction") 1351001SN/A .desc("Percentage of non-idle cycles") 1361001SN/A ; 1371001SN/A 1382SN/A idleFraction 1392SN/A .name(name() + ".idle_fraction") 1402SN/A .desc("Percentage of idle cycles") 1412SN/A ; 1422SN/A 1432SN/A icacheStallCycles 1442SN/A .name(name() + ".icache_stall_cycles") 1452SN/A .desc("ICache total stall cycles") 1462SN/A .prereq(icacheStallCycles) 1472SN/A ; 1482SN/A 1492SN/A dcacheStallCycles 1502SN/A .name(name() + ".dcache_stall_cycles") 1512SN/A .desc("DCache total stall cycles") 1522SN/A .prereq(dcacheStallCycles) 1532SN/A ; 1542SN/A 1552390SN/A icacheRetryCycles 1562390SN/A .name(name() + ".icache_retry_cycles") 1572390SN/A .desc("ICache total retry cycles") 1582390SN/A .prereq(icacheRetryCycles) 1592390SN/A ; 1602390SN/A 1612390SN/A dcacheRetryCycles 1622390SN/A .name(name() + ".dcache_retry_cycles") 1632390SN/A .desc("DCache total retry cycles") 1642390SN/A .prereq(dcacheRetryCycles) 1652390SN/A ; 1662390SN/A 167385SN/A idleFraction = constant(1.0) - notIdleFraction; 1682SN/A} 1692SN/A 1702SN/Avoid 1712623SN/ABaseSimpleCPU::resetStats() 172334SN/A{ 173334SN/A startNumInst = numInst; 1742623SN/A // notIdleFraction = (_status != Idle); 175334SN/A} 176334SN/A 177334SN/Avoid 1782623SN/ABaseSimpleCPU::serialize(ostream &os) 1792SN/A{ 180921SN/A BaseCPU::serialize(os); 181224SN/A SERIALIZE_SCALAR(inst); 182237SN/A nameOut(os, csprintf("%s.xc", name())); 1832190SN/A cpuXC->serialize(os); 1842SN/A} 1852SN/A 1862SN/Avoid 1872623SN/ABaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1882SN/A{ 189921SN/A BaseCPU::unserialize(cp, section); 190224SN/A UNSERIALIZE_SCALAR(inst); 1912190SN/A cpuXC->unserialize(cp, csprintf("%s.xc", section)); 1922SN/A} 1932SN/A 1942SN/Avoid 1952SN/Achange_thread_state(int thread_number, int activate, int priority) 1962SN/A{ 1972SN/A} 1982SN/A 199595SN/AFault 2002623SN/ABaseSimpleCPU::copySrcTranslate(Addr src) 201595SN/A{ 2022390SN/A#if 0 2031080SN/A static bool no_warn = true; 2041080SN/A int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 2051080SN/A // Only support block sizes of 64 atm. 2061080SN/A assert(blk_size == 64); 2071080SN/A int offset = src & (blk_size - 1); 2081080SN/A 2091080SN/A // Make sure block doesn't span page 2101121SN/A if (no_warn && 2112107SN/A (src & PageMask) != ((src + blk_size) & PageMask) && 2121089SN/A (src >> 40) != 0xfffffc) { 2131089SN/A warn("Copied block source spans pages %x.", src); 2141080SN/A no_warn = false; 2151080SN/A } 2161080SN/A 2171080SN/A memReq->reset(src & ~(blk_size - 1), blk_size); 218595SN/A 2192623SN/A // translate to physical address 2202623SN/A Fault fault = cpuXC->translateDataReadReq(req); 221595SN/A 2222090SN/A if (fault == NoFault) { 2232190SN/A cpuXC->copySrcAddr = src; 2242190SN/A cpuXC->copySrcPhysAddr = memReq->paddr + offset; 225595SN/A } else { 2262205SN/A assert(!fault->isAlignmentFault()); 2272205SN/A 2282190SN/A cpuXC->copySrcAddr = 0; 2292190SN/A cpuXC->copySrcPhysAddr = 0; 230595SN/A } 231595SN/A return fault; 2322390SN/A#else 2332423SN/A return NoFault; 2342390SN/A#endif 235595SN/A} 236595SN/A 237595SN/AFault 2382623SN/ABaseSimpleCPU::copy(Addr dest) 239595SN/A{ 2402390SN/A#if 0 2411080SN/A static bool no_warn = true; 242595SN/A int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 2431080SN/A // Only support block sizes of 64 atm. 2441080SN/A assert(blk_size == 64); 245595SN/A uint8_t data[blk_size]; 2462190SN/A //assert(cpuXC->copySrcAddr); 2471080SN/A int offset = dest & (blk_size - 1); 2481080SN/A 2491080SN/A // Make sure block doesn't span page 2501121SN/A if (no_warn && 2512107SN/A (dest & PageMask) != ((dest + blk_size) & PageMask) && 2521089SN/A (dest >> 40) != 0xfffffc) { 2531080SN/A no_warn = false; 2541089SN/A warn("Copied block destination spans pages %x. ", dest); 2551080SN/A } 2561080SN/A 2571080SN/A memReq->reset(dest & ~(blk_size -1), blk_size); 258595SN/A // translate to physical address 2592422SN/A Fault fault = cpuXC->translateDataWriteReq(req); 2601080SN/A 2612090SN/A if (fault == NoFault) { 2621080SN/A Addr dest_addr = memReq->paddr + offset; 263595SN/A // Need to read straight from memory since we have more than 8 bytes. 2642190SN/A memReq->paddr = cpuXC->copySrcPhysAddr; 2652190SN/A cpuXC->mem->read(memReq, data); 266595SN/A memReq->paddr = dest_addr; 2672190SN/A cpuXC->mem->write(memReq, data); 2681098SN/A if (dcacheInterface) { 2691098SN/A memReq->cmd = Copy; 2701098SN/A memReq->completionEvent = NULL; 2712190SN/A memReq->paddr = cpuXC->copySrcPhysAddr; 2721098SN/A memReq->dest = dest_addr; 2731098SN/A memReq->size = 64; 2741098SN/A memReq->time = curTick; 2752012SN/A memReq->flags &= ~INST_READ; 2761098SN/A dcacheInterface->access(memReq); 2771098SN/A } 278595SN/A } 2792205SN/A else 2802205SN/A assert(!fault->isAlignmentFault()); 2812205SN/A 282595SN/A return fault; 2832390SN/A#else 2842420SN/A panic("copy not implemented"); 2852423SN/A return NoFault; 2862390SN/A#endif 287595SN/A} 288595SN/A 2891858SN/A#if FULL_SYSTEM 2902SN/AAddr 2912623SN/ABaseSimpleCPU::dbg_vtophys(Addr addr) 2922SN/A{ 2932680Sktlim@umich.edu return vtophys(tc, addr); 2942SN/A} 2952SN/A#endif // FULL_SYSTEM 2962SN/A 2971858SN/A#if FULL_SYSTEM 2982SN/Avoid 2992623SN/ABaseSimpleCPU::post_interrupt(int int_num, int index) 3002SN/A{ 3012SN/A BaseCPU::post_interrupt(int_num, index); 3022SN/A 3032680Sktlim@umich.edu if (cpuXC->status() == ThreadContext::Suspended) { 3042SN/A DPRINTF(IPI,"Suspended Processor awoke\n"); 3052190SN/A cpuXC->activate(); 3062SN/A } 3072SN/A} 3082SN/A#endif // FULL_SYSTEM 3092SN/A 3102SN/Avoid 3112623SN/ABaseSimpleCPU::checkForInterrupts() 3122SN/A{ 3131858SN/A#if FULL_SYSTEM 3142626SN/A if (checkInterrupts && check_interrupts() && !cpuXC->inPalMode()) { 3152SN/A int ipl = 0; 3162SN/A int summary = 0; 3171133SN/A checkInterrupts = false; 3182SN/A 3192190SN/A if (cpuXC->readMiscReg(IPR_SIRR)) { 3202107SN/A for (int i = INTLEVEL_SOFTWARE_MIN; 3212107SN/A i < INTLEVEL_SOFTWARE_MAX; i++) { 3222190SN/A if (cpuXC->readMiscReg(IPR_SIRR) & (ULL(1) << i)) { 3232SN/A // See table 4-19 of 21164 hardware reference 3242107SN/A ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; 3252SN/A summary |= (ULL(1) << i); 3262SN/A } 3272SN/A } 3282SN/A } 3292SN/A 3302190SN/A uint64_t interrupts = cpuXC->cpu->intr_status(); 3312107SN/A for (int i = INTLEVEL_EXTERNAL_MIN; 3322107SN/A i < INTLEVEL_EXTERNAL_MAX; i++) { 3332SN/A if (interrupts & (ULL(1) << i)) { 3342SN/A // See table 4-19 of 21164 hardware reference 3352SN/A ipl = i; 3362SN/A summary |= (ULL(1) << i); 3372SN/A } 3382SN/A } 3392SN/A 3402190SN/A if (cpuXC->readMiscReg(IPR_ASTRR)) 3412SN/A panic("asynchronous traps not implemented\n"); 3422SN/A 3432190SN/A if (ipl && ipl > cpuXC->readMiscReg(IPR_IPLR)) { 3442190SN/A cpuXC->setMiscReg(IPR_ISR, summary); 3452190SN/A cpuXC->setMiscReg(IPR_INTID, ipl); 3462234SN/A 3472680Sktlim@umich.edu Fault(new InterruptFault)->invoke(tc); 3482SN/A 3492SN/A DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", 3502190SN/A cpuXC->readMiscReg(IPR_IPLR), ipl, summary); 3512SN/A } 3522SN/A } 3532SN/A#endif 3542623SN/A} 3552SN/A 3562623SN/A 3572623SN/AFault 3582662Sstever@eecs.umich.eduBaseSimpleCPU::setupFetchRequest(Request *req) 3592623SN/A{ 3602623SN/A // set up memory request for instruction fetch 3612623SN/A DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",cpuXC->readPC(), 3622623SN/A cpuXC->readNextPC(),cpuXC->readNextNPC()); 3632623SN/A 3642663Sstever@eecs.umich.edu req->setVirt(0, cpuXC->readPC() & ~3, sizeof(MachInst), 3652663Sstever@eecs.umich.edu (FULL_SYSTEM && (cpuXC->readPC() & 1)) ? PHYSICAL : 0, 3662663Sstever@eecs.umich.edu cpuXC->readPC()); 3672623SN/A 3682662Sstever@eecs.umich.edu Fault fault = cpuXC->translateInstReq(req); 3692623SN/A 3702623SN/A return fault; 3712623SN/A} 3722623SN/A 3732623SN/A 3742623SN/Avoid 3752623SN/ABaseSimpleCPU::preExecute() 3762623SN/A{ 3772SN/A // maintain $r0 semantics 3782190SN/A cpuXC->setIntReg(ZeroReg, 0); 3792427SN/A#if THE_ISA == ALPHA_ISA 3802455SN/A cpuXC->setFloatReg(ZeroReg, 0.0); 3812427SN/A#endif // ALPHA_ISA 3822SN/A 3832623SN/A // keep an instruction count 3842623SN/A numInst++; 3852623SN/A numInsts++; 3862SN/A 3872623SN/A cpuXC->func_exe_inst++; 3882SN/A 3892623SN/A // check for instruction-count-based events 3902623SN/A comInstEventQueue[0]->serviceEvents(numInst); 3912SN/A 3922623SN/A // decode the instruction 3932623SN/A inst = gtoh(inst); 3942623SN/A curStaticInst = StaticInst::decode(makeExtMI(inst, cpuXC->readPC())); 3952470SN/A 3962680Sktlim@umich.edu traceData = Trace::getInstRecord(curTick, tc, this, curStaticInst, 3972623SN/A cpuXC->readPC()); 3982623SN/A 3992623SN/A DPRINTF(Decode,"Decode: Decoded %s instruction (opcode: 0x%x): 0x%x\n", 4002623SN/A curStaticInst->getName(), curStaticInst->getOpcode(), 4012623SN/A curStaticInst->machInst); 4022623SN/A 4032623SN/A#if FULL_SYSTEM 4042623SN/A cpuXC->setInst(inst); 4052623SN/A#endif // FULL_SYSTEM 4062623SN/A} 4072623SN/A 4082623SN/Avoid 4092623SN/ABaseSimpleCPU::postExecute() 4102623SN/A{ 4112623SN/A#if FULL_SYSTEM 4122623SN/A if (system->kernelBinning->fnbin) { 4132671Sktlim@umich.edu assert(cpuXC->getKernelStats()); 4142680Sktlim@umich.edu system->kernelBinning->execute(tc, inst); 4152623SN/A } 4162623SN/A 4172623SN/A if (cpuXC->profile) { 4182623SN/A bool usermode = 4192623SN/A (cpuXC->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; 4202623SN/A cpuXC->profilePC = usermode ? 1 : cpuXC->readPC(); 4212680Sktlim@umich.edu ProfileNode *node = cpuXC->profile->consume(tc, inst); 4222623SN/A if (node) 4232623SN/A cpuXC->profileNode = node; 4242623SN/A } 4252420SN/A#endif 4262SN/A 4272623SN/A if (curStaticInst->isMemRef()) { 4282623SN/A numMemRefs++; 4292SN/A } 4302SN/A 4312623SN/A if (curStaticInst->isLoad()) { 4322623SN/A ++numLoad; 4332623SN/A comLoadEventQueue[0]->serviceEvents(numLoad); 4342623SN/A } 4352SN/A 4362623SN/A traceFunctions(cpuXC->readPC()); 4372644Sstever@eecs.umich.edu 4382644Sstever@eecs.umich.edu if (traceData) { 4392644Sstever@eecs.umich.edu traceData->finalize(); 4402644Sstever@eecs.umich.edu } 4412623SN/A} 4422SN/A 4432SN/A 4442623SN/Avoid 4452623SN/ABaseSimpleCPU::advancePC(Fault fault) 4462623SN/A{ 4472090SN/A if (fault != NoFault) { 4481858SN/A#if FULL_SYSTEM 4492680Sktlim@umich.edu fault->invoke(tc); 4502SN/A#else // !FULL_SYSTEM 4512470SN/A fatal("fault (%s) detected @ PC %08p", fault->name(), cpuXC->readPC()); 4522SN/A#endif // FULL_SYSTEM 4532SN/A } 4542SN/A else { 4552SN/A // go to the next instruction 4562190SN/A cpuXC->setPC(cpuXC->readNextPC()); 4572623SN/A#if THE_ISA == ALPHA_ISA 4582190SN/A cpuXC->setNextPC(cpuXC->readNextPC() + sizeof(MachInst)); 4592251SN/A#else 4602262SN/A cpuXC->setNextPC(cpuXC->readNextNPC()); 4612262SN/A cpuXC->setNextNPC(cpuXC->readNextNPC() + sizeof(MachInst)); 4622251SN/A#endif 4632251SN/A 4642SN/A } 4652SN/A 4661858SN/A#if FULL_SYSTEM 4672SN/A Addr oldpc; 4682SN/A do { 4692190SN/A oldpc = cpuXC->readPC(); 4702680Sktlim@umich.edu system->pcEventQueue.service(tc); 4712190SN/A } while (oldpc != cpuXC->readPC()); 4722SN/A#endif 4732SN/A} 4742SN/A 475