base.cc revision 2671
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292SN/A */ 302SN/A 312439SN/A#include "arch/utility.hh" 32146SN/A#include "base/cprintf.hh" 33146SN/A#include "base/inifile.hh" 34146SN/A#include "base/loader/symtab.hh" 35146SN/A#include "base/misc.hh" 36146SN/A#include "base/pollevent.hh" 37146SN/A#include "base/range.hh" 381717SN/A#include "base/stats/events.hh" 39146SN/A#include "base/trace.hh" 401717SN/A#include "cpu/base.hh" 412190SN/A#include "cpu/cpu_exec_context.hh" 42146SN/A#include "cpu/exec_context.hh" 43146SN/A#include "cpu/exetrace.hh" 441977SN/A#include "cpu/profile.hh" 451717SN/A#include "cpu/sampler/sampler.hh" 462623SN/A#include "cpu/simple/base.hh" 471717SN/A#include "cpu/smt.hh" 48146SN/A#include "cpu/static_inst.hh" 491917SN/A#include "kern/kernel_stats.hh" 502592SN/A#include "mem/packet_impl.hh" 512036SN/A#include "sim/byteswap.hh" 52146SN/A#include "sim/builder.hh" 53146SN/A#include "sim/debug.hh" 5456SN/A#include "sim/host.hh" 5556SN/A#include "sim/sim_events.hh" 5656SN/A#include "sim/sim_object.hh" 57695SN/A#include "sim/stats.hh" 582SN/A 591858SN/A#if FULL_SYSTEM 6056SN/A#include "base/remote_gdb.hh" 61146SN/A#include "sim/system.hh" 622171SN/A#include "arch/tlb.hh" 632170SN/A#include "arch/stacktrace.hh" 642170SN/A#include "arch/vtophys.hh" 65146SN/A#else // !FULL_SYSTEM 662462SN/A#include "mem/mem_object.hh" 67146SN/A#endif // FULL_SYSTEM 682SN/A 692SN/Ausing namespace std; 702449SN/Ausing namespace TheISA; 711355SN/A 722623SN/ABaseSimpleCPU::BaseSimpleCPU(Params *p) 732623SN/A : BaseCPU(p), mem(p->mem), cpuXC(NULL) 74224SN/A{ 751858SN/A#if FULL_SYSTEM 762518SN/A cpuXC = new CPUExecContext(this, 0, p->system, p->itb, p->dtb); 772420SN/A#else 782519SN/A cpuXC = new CPUExecContext(this, /* thread_num */ 0, p->process, 792520SN/A /* asid */ 0, mem); 802420SN/A#endif // !FULL_SYSTEM 812SN/A 822190SN/A xcProxy = cpuXC->getProxy(); 832SN/A 842SN/A numInst = 0; 85334SN/A startNumInst = 0; 86140SN/A numLoad = 0; 87334SN/A startNumLoad = 0; 882SN/A lastIcacheStall = 0; 892SN/A lastDcacheStall = 0; 902SN/A 912190SN/A execContexts.push_back(xcProxy); 922SN/A} 932SN/A 942623SN/ABaseSimpleCPU::~BaseSimpleCPU() 952SN/A{ 962SN/A} 972SN/A 98180SN/Avoid 992623SN/ABaseSimpleCPU::deallocateContext(int thread_num) 100393SN/A{ 101393SN/A // for now, these are equivalent 102393SN/A suspendContext(thread_num); 103393SN/A} 104384SN/A 105384SN/A 106393SN/Avoid 1072623SN/ABaseSimpleCPU::haltContext(int thread_num) 108393SN/A{ 109393SN/A // for now, these are equivalent 110393SN/A suspendContext(thread_num); 111393SN/A} 112384SN/A 113189SN/A 114189SN/Avoid 1152623SN/ABaseSimpleCPU::regStats() 1162SN/A{ 117729SN/A using namespace Stats; 118334SN/A 1192SN/A BaseCPU::regStats(); 1202SN/A 1212SN/A numInsts 1222SN/A .name(name() + ".num_insts") 1232SN/A .desc("Number of instructions executed") 1242SN/A ; 1252SN/A 1262SN/A numMemRefs 1272SN/A .name(name() + ".num_refs") 1282SN/A .desc("Number of memory references") 1292SN/A ; 1302SN/A 1311001SN/A notIdleFraction 1321001SN/A .name(name() + ".not_idle_fraction") 1331001SN/A .desc("Percentage of non-idle cycles") 1341001SN/A ; 1351001SN/A 1362SN/A idleFraction 1372SN/A .name(name() + ".idle_fraction") 1382SN/A .desc("Percentage of idle cycles") 1392SN/A ; 1402SN/A 1412SN/A icacheStallCycles 1422SN/A .name(name() + ".icache_stall_cycles") 1432SN/A .desc("ICache total stall cycles") 1442SN/A .prereq(icacheStallCycles) 1452SN/A ; 1462SN/A 1472SN/A dcacheStallCycles 1482SN/A .name(name() + ".dcache_stall_cycles") 1492SN/A .desc("DCache total stall cycles") 1502SN/A .prereq(dcacheStallCycles) 1512SN/A ; 1522SN/A 1532390SN/A icacheRetryCycles 1542390SN/A .name(name() + ".icache_retry_cycles") 1552390SN/A .desc("ICache total retry cycles") 1562390SN/A .prereq(icacheRetryCycles) 1572390SN/A ; 1582390SN/A 1592390SN/A dcacheRetryCycles 1602390SN/A .name(name() + ".dcache_retry_cycles") 1612390SN/A .desc("DCache total retry cycles") 1622390SN/A .prereq(dcacheRetryCycles) 1632390SN/A ; 1642390SN/A 165385SN/A idleFraction = constant(1.0) - notIdleFraction; 1662SN/A} 1672SN/A 1682SN/Avoid 1692623SN/ABaseSimpleCPU::resetStats() 170334SN/A{ 171334SN/A startNumInst = numInst; 1722623SN/A // notIdleFraction = (_status != Idle); 173334SN/A} 174334SN/A 175334SN/Avoid 1762623SN/ABaseSimpleCPU::serialize(ostream &os) 1772SN/A{ 178921SN/A BaseCPU::serialize(os); 179224SN/A SERIALIZE_SCALAR(inst); 180237SN/A nameOut(os, csprintf("%s.xc", name())); 1812190SN/A cpuXC->serialize(os); 1822SN/A} 1832SN/A 1842SN/Avoid 1852623SN/ABaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1862SN/A{ 187921SN/A BaseCPU::unserialize(cp, section); 188224SN/A UNSERIALIZE_SCALAR(inst); 1892190SN/A cpuXC->unserialize(cp, csprintf("%s.xc", section)); 1902SN/A} 1912SN/A 1922SN/Avoid 1932SN/Achange_thread_state(int thread_number, int activate, int priority) 1942SN/A{ 1952SN/A} 1962SN/A 197595SN/AFault 1982623SN/ABaseSimpleCPU::copySrcTranslate(Addr src) 199595SN/A{ 2002390SN/A#if 0 2011080SN/A static bool no_warn = true; 2021080SN/A int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 2031080SN/A // Only support block sizes of 64 atm. 2041080SN/A assert(blk_size == 64); 2051080SN/A int offset = src & (blk_size - 1); 2061080SN/A 2071080SN/A // Make sure block doesn't span page 2081121SN/A if (no_warn && 2092107SN/A (src & PageMask) != ((src + blk_size) & PageMask) && 2101089SN/A (src >> 40) != 0xfffffc) { 2111089SN/A warn("Copied block source spans pages %x.", src); 2121080SN/A no_warn = false; 2131080SN/A } 2141080SN/A 2151080SN/A memReq->reset(src & ~(blk_size - 1), blk_size); 216595SN/A 2172623SN/A // translate to physical address 2182623SN/A Fault fault = cpuXC->translateDataReadReq(req); 219595SN/A 2202090SN/A if (fault == NoFault) { 2212190SN/A cpuXC->copySrcAddr = src; 2222190SN/A cpuXC->copySrcPhysAddr = memReq->paddr + offset; 223595SN/A } else { 2242205SN/A assert(!fault->isAlignmentFault()); 2252205SN/A 2262190SN/A cpuXC->copySrcAddr = 0; 2272190SN/A cpuXC->copySrcPhysAddr = 0; 228595SN/A } 229595SN/A return fault; 2302390SN/A#else 2312423SN/A return NoFault; 2322390SN/A#endif 233595SN/A} 234595SN/A 235595SN/AFault 2362623SN/ABaseSimpleCPU::copy(Addr dest) 237595SN/A{ 2382390SN/A#if 0 2391080SN/A static bool no_warn = true; 240595SN/A int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 2411080SN/A // Only support block sizes of 64 atm. 2421080SN/A assert(blk_size == 64); 243595SN/A uint8_t data[blk_size]; 2442190SN/A //assert(cpuXC->copySrcAddr); 2451080SN/A int offset = dest & (blk_size - 1); 2461080SN/A 2471080SN/A // Make sure block doesn't span page 2481121SN/A if (no_warn && 2492107SN/A (dest & PageMask) != ((dest + blk_size) & PageMask) && 2501089SN/A (dest >> 40) != 0xfffffc) { 2511080SN/A no_warn = false; 2521089SN/A warn("Copied block destination spans pages %x. ", dest); 2531080SN/A } 2541080SN/A 2551080SN/A memReq->reset(dest & ~(blk_size -1), blk_size); 256595SN/A // translate to physical address 2572422SN/A Fault fault = cpuXC->translateDataWriteReq(req); 2581080SN/A 2592090SN/A if (fault == NoFault) { 2601080SN/A Addr dest_addr = memReq->paddr + offset; 261595SN/A // Need to read straight from memory since we have more than 8 bytes. 2622190SN/A memReq->paddr = cpuXC->copySrcPhysAddr; 2632190SN/A cpuXC->mem->read(memReq, data); 264595SN/A memReq->paddr = dest_addr; 2652190SN/A cpuXC->mem->write(memReq, data); 2661098SN/A if (dcacheInterface) { 2671098SN/A memReq->cmd = Copy; 2681098SN/A memReq->completionEvent = NULL; 2692190SN/A memReq->paddr = cpuXC->copySrcPhysAddr; 2701098SN/A memReq->dest = dest_addr; 2711098SN/A memReq->size = 64; 2721098SN/A memReq->time = curTick; 2732012SN/A memReq->flags &= ~INST_READ; 2741098SN/A dcacheInterface->access(memReq); 2751098SN/A } 276595SN/A } 2772205SN/A else 2782205SN/A assert(!fault->isAlignmentFault()); 2792205SN/A 280595SN/A return fault; 2812390SN/A#else 2822420SN/A panic("copy not implemented"); 2832423SN/A return NoFault; 2842390SN/A#endif 285595SN/A} 286595SN/A 2871858SN/A#if FULL_SYSTEM 2882SN/AAddr 2892623SN/ABaseSimpleCPU::dbg_vtophys(Addr addr) 2902SN/A{ 2912190SN/A return vtophys(xcProxy, addr); 2922SN/A} 2932SN/A#endif // FULL_SYSTEM 2942SN/A 2951858SN/A#if FULL_SYSTEM 2962SN/Avoid 2972623SN/ABaseSimpleCPU::post_interrupt(int int_num, int index) 2982SN/A{ 2992SN/A BaseCPU::post_interrupt(int_num, index); 3002SN/A 3012190SN/A if (cpuXC->status() == ExecContext::Suspended) { 3022SN/A DPRINTF(IPI,"Suspended Processor awoke\n"); 3032190SN/A cpuXC->activate(); 3042SN/A } 3052SN/A} 3062SN/A#endif // FULL_SYSTEM 3072SN/A 3082SN/Avoid 3092623SN/ABaseSimpleCPU::checkForInterrupts() 3102SN/A{ 3111858SN/A#if FULL_SYSTEM 3122626SN/A if (checkInterrupts && check_interrupts() && !cpuXC->inPalMode()) { 3132SN/A int ipl = 0; 3142SN/A int summary = 0; 3151133SN/A checkInterrupts = false; 3162SN/A 3172190SN/A if (cpuXC->readMiscReg(IPR_SIRR)) { 3182107SN/A for (int i = INTLEVEL_SOFTWARE_MIN; 3192107SN/A i < INTLEVEL_SOFTWARE_MAX; i++) { 3202190SN/A if (cpuXC->readMiscReg(IPR_SIRR) & (ULL(1) << i)) { 3212SN/A // See table 4-19 of 21164 hardware reference 3222107SN/A ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; 3232SN/A summary |= (ULL(1) << i); 3242SN/A } 3252SN/A } 3262SN/A } 3272SN/A 3282190SN/A uint64_t interrupts = cpuXC->cpu->intr_status(); 3292107SN/A for (int i = INTLEVEL_EXTERNAL_MIN; 3302107SN/A i < INTLEVEL_EXTERNAL_MAX; i++) { 3312SN/A if (interrupts & (ULL(1) << i)) { 3322SN/A // See table 4-19 of 21164 hardware reference 3332SN/A ipl = i; 3342SN/A summary |= (ULL(1) << i); 3352SN/A } 3362SN/A } 3372SN/A 3382190SN/A if (cpuXC->readMiscReg(IPR_ASTRR)) 3392SN/A panic("asynchronous traps not implemented\n"); 3402SN/A 3412190SN/A if (ipl && ipl > cpuXC->readMiscReg(IPR_IPLR)) { 3422190SN/A cpuXC->setMiscReg(IPR_ISR, summary); 3432190SN/A cpuXC->setMiscReg(IPR_INTID, ipl); 3442234SN/A 3452234SN/A Fault(new InterruptFault)->invoke(xcProxy); 3462SN/A 3472SN/A DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", 3482190SN/A cpuXC->readMiscReg(IPR_IPLR), ipl, summary); 3492SN/A } 3502SN/A } 3512SN/A#endif 3522623SN/A} 3532SN/A 3542623SN/A 3552623SN/AFault 3562662Sstever@eecs.umich.eduBaseSimpleCPU::setupFetchRequest(Request *req) 3572623SN/A{ 3582623SN/A // set up memory request for instruction fetch 3592623SN/A DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",cpuXC->readPC(), 3602623SN/A cpuXC->readNextPC(),cpuXC->readNextNPC()); 3612623SN/A 3622663Sstever@eecs.umich.edu req->setVirt(0, cpuXC->readPC() & ~3, sizeof(MachInst), 3632663Sstever@eecs.umich.edu (FULL_SYSTEM && (cpuXC->readPC() & 1)) ? PHYSICAL : 0, 3642663Sstever@eecs.umich.edu cpuXC->readPC()); 3652623SN/A 3662662Sstever@eecs.umich.edu Fault fault = cpuXC->translateInstReq(req); 3672623SN/A 3682623SN/A return fault; 3692623SN/A} 3702623SN/A 3712623SN/A 3722623SN/Avoid 3732623SN/ABaseSimpleCPU::preExecute() 3742623SN/A{ 3752SN/A // maintain $r0 semantics 3762190SN/A cpuXC->setIntReg(ZeroReg, 0); 3772427SN/A#if THE_ISA == ALPHA_ISA 3782455SN/A cpuXC->setFloatReg(ZeroReg, 0.0); 3792427SN/A#endif // ALPHA_ISA 3802SN/A 3812623SN/A // keep an instruction count 3822623SN/A numInst++; 3832623SN/A numInsts++; 3842SN/A 3852623SN/A cpuXC->func_exe_inst++; 3862SN/A 3872623SN/A // check for instruction-count-based events 3882623SN/A comInstEventQueue[0]->serviceEvents(numInst); 3892SN/A 3902623SN/A // decode the instruction 3912623SN/A inst = gtoh(inst); 3922623SN/A curStaticInst = StaticInst::decode(makeExtMI(inst, cpuXC->readPC())); 3932470SN/A 3942623SN/A traceData = Trace::getInstRecord(curTick, xcProxy, this, curStaticInst, 3952623SN/A cpuXC->readPC()); 3962623SN/A 3972623SN/A DPRINTF(Decode,"Decode: Decoded %s instruction (opcode: 0x%x): 0x%x\n", 3982623SN/A curStaticInst->getName(), curStaticInst->getOpcode(), 3992623SN/A curStaticInst->machInst); 4002623SN/A 4012623SN/A#if FULL_SYSTEM 4022623SN/A cpuXC->setInst(inst); 4032623SN/A#endif // FULL_SYSTEM 4042623SN/A} 4052623SN/A 4062623SN/Avoid 4072623SN/ABaseSimpleCPU::postExecute() 4082623SN/A{ 4092623SN/A#if FULL_SYSTEM 4102623SN/A if (system->kernelBinning->fnbin) { 4112671Sktlim@umich.edu assert(cpuXC->getKernelStats()); 4122623SN/A system->kernelBinning->execute(xcProxy, inst); 4132623SN/A } 4142623SN/A 4152623SN/A if (cpuXC->profile) { 4162623SN/A bool usermode = 4172623SN/A (cpuXC->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; 4182623SN/A cpuXC->profilePC = usermode ? 1 : cpuXC->readPC(); 4192623SN/A ProfileNode *node = cpuXC->profile->consume(xcProxy, inst); 4202623SN/A if (node) 4212623SN/A cpuXC->profileNode = node; 4222623SN/A } 4232420SN/A#endif 4242SN/A 4252623SN/A if (curStaticInst->isMemRef()) { 4262623SN/A numMemRefs++; 4272SN/A } 4282SN/A 4292623SN/A if (curStaticInst->isLoad()) { 4302623SN/A ++numLoad; 4312623SN/A comLoadEventQueue[0]->serviceEvents(numLoad); 4322623SN/A } 4332SN/A 4342623SN/A traceFunctions(cpuXC->readPC()); 4352644Sstever@eecs.umich.edu 4362644Sstever@eecs.umich.edu if (traceData) { 4372644Sstever@eecs.umich.edu traceData->finalize(); 4382644Sstever@eecs.umich.edu } 4392623SN/A} 4402SN/A 4412SN/A 4422623SN/Avoid 4432623SN/ABaseSimpleCPU::advancePC(Fault fault) 4442623SN/A{ 4452090SN/A if (fault != NoFault) { 4461858SN/A#if FULL_SYSTEM 4472234SN/A fault->invoke(xcProxy); 4482SN/A#else // !FULL_SYSTEM 4492470SN/A fatal("fault (%s) detected @ PC %08p", fault->name(), cpuXC->readPC()); 4502SN/A#endif // FULL_SYSTEM 4512SN/A } 4522SN/A else { 4532SN/A // go to the next instruction 4542190SN/A cpuXC->setPC(cpuXC->readNextPC()); 4552623SN/A#if THE_ISA == ALPHA_ISA 4562190SN/A cpuXC->setNextPC(cpuXC->readNextPC() + sizeof(MachInst)); 4572251SN/A#else 4582262SN/A cpuXC->setNextPC(cpuXC->readNextNPC()); 4592262SN/A cpuXC->setNextNPC(cpuXC->readNextNPC() + sizeof(MachInst)); 4602251SN/A#endif 4612251SN/A 4622SN/A } 4632SN/A 4641858SN/A#if FULL_SYSTEM 4652SN/A Addr oldpc; 4662SN/A do { 4672190SN/A oldpc = cpuXC->readPC(); 4682190SN/A system->pcEventQueue.service(xcProxy); 4692190SN/A } while (oldpc != cpuXC->readPC()); 4702SN/A#endif 4712SN/A} 4722SN/A 473