base.cc revision 180 
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <cmath>
30#include <cstdio>
31#include <cstdlib>
32#include <iostream>
33#include <iomanip>
34#include <list>
35#include <sstream>
36#include <string>
37
38#include "base/cprintf.hh"
39#include "base/inifile.hh"
40#include "base/loader/symtab.hh"
41#include "base/misc.hh"
42#include "base/pollevent.hh"
43#include "base/range.hh"
44#include "base/trace.hh"
45#include "cpu/base_cpu.hh"
46#include "cpu/exec_context.hh"
47#include "cpu/exetrace.hh"
48#include "cpu/full_cpu/smt.hh"
49#include "cpu/simple_cpu/simple_cpu.hh"
50#include "cpu/static_inst.hh"
51#include "mem/base_mem.hh"
52#include "mem/mem_interface.hh"
53#include "sim/annotation.hh"
54#include "sim/builder.hh"
55#include "sim/debug.hh"
56#include "sim/host.hh"
57#include "sim/sim_events.hh"
58#include "sim/sim_object.hh"
59#include "sim/sim_stats.hh"
60
61#ifdef FULL_SYSTEM
62#include "base/remote_gdb.hh"
63#include "dev/alpha_access.h"
64#include "dev/pciareg.h"
65#include "mem/functional_mem/memory_control.hh"
66#include "mem/functional_mem/physical_memory.hh"
67#include "sim/system.hh"
68#include "targetarch/alpha_memory.hh"
69#include "targetarch/vtophys.hh"
70#else // !FULL_SYSTEM
71#include "eio/eio.hh"
72#include "mem/functional_mem/functional_memory.hh"
73#include "sim/prog.hh"
74#endif // FULL_SYSTEM
75
76using namespace std;
77
78SimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu)
79    : Event(&mainEventQueue),
80      cpu(_cpu)
81{
82}
83
84void SimpleCPU::CacheCompletionEvent::process()
85{
86    cpu->processCacheCompletion();
87}
88
89const char *
90SimpleCPU::CacheCompletionEvent::description()
91{
92    return "cache completion event";
93}
94
95#ifdef FULL_SYSTEM
96SimpleCPU::SimpleCPU(const string &_name,
97                     System *_system,
98                     Counter max_insts_any_thread,
99                     Counter max_insts_all_threads,
100                     Counter max_loads_any_thread,
101                     Counter max_loads_all_threads,
102                     AlphaItb *itb, AlphaDtb *dtb,
103                     FunctionalMemory *mem,
104                     MemInterface *icache_interface,
105                     MemInterface *dcache_interface,
106                     Tick freq)
107    : BaseCPU(_name, /* number_of_threads */ 1,
108              max_insts_any_thread, max_insts_all_threads,
109              max_loads_any_thread, max_loads_all_threads,
110              _system, freq),
111#else
112SimpleCPU::SimpleCPU(const string &_name, Process *_process,
113                     Counter max_insts_any_thread,
114                     Counter max_insts_all_threads,
115                     Counter max_loads_any_thread,
116                     Counter max_loads_all_threads,
117                     MemInterface *icache_interface,
118                     MemInterface *dcache_interface)
119    : BaseCPU(_name, /* number_of_threads */ 1,
120              max_insts_any_thread, max_insts_all_threads,
121              max_loads_any_thread, max_loads_all_threads),
122#endif
123      tickEvent(this), xc(NULL), cacheCompletionEvent(this)
124{
125    _status = Idle;
126#ifdef FULL_SYSTEM
127    xc = new ExecContext(this, 0, system, itb, dtb, mem);
128
129    TheISA::initCPU(&xc->regs);
130
131    IntReg *ipr = xc->regs.ipr;
132    ipr[TheISA::IPR_MCSR] = 0x6;
133
134    AlphaISA::swap_palshadow(&xc->regs, true);
135
136    fault = Reset_Fault;
137    xc->regs.pc = ipr[TheISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault];
138    xc->regs.npc = xc->regs.pc + sizeof(MachInst);
139#else
140    xc = new ExecContext(this, /* thread_num */ 0, _process, /* asid */ 0);
141    fault = No_Fault;
142#endif // !FULL_SYSTEM
143
144    icacheInterface = icache_interface;
145    dcacheInterface = dcache_interface;
146
147    memReq = new MemReq();
148    memReq->xc = xc;
149    memReq->asid = 0;
150    memReq->data = new uint8_t[64];
151
152    numInst = 0;
153    numLoad = 0;
154    last_idle = 0;
155    lastIcacheStall = 0;
156    lastDcacheStall = 0;
157
158    execContexts.push_back(xc);
159}
160
161SimpleCPU::~SimpleCPU()
162{
163}
164
165
166void
167SimpleCPU::registerExecContexts()
168{
169    BaseCPU::registerExecContexts();
170
171    // if any of this CPU's ExecContexts are active, mark the CPU as
172    // running and schedule its tick event.
173    for (int i = 0; i < execContexts.size(); ++i) {
174        ExecContext *xc = execContexts[i];
175        if (xc->status() == ExecContext::Active && _status != Running) {
176            _status = Running;
177            // this should only happen at initialization time
178            assert(curTick == 0);
179            tickEvent.schedule(0);
180        }
181    }
182}
183
184
185void
186SimpleCPU::switchOut()
187{
188    _status = SwitchedOut;
189    if (tickEvent.scheduled())
190        tickEvent.squash();
191}
192
193
194void
195SimpleCPU::takeOverFrom(BaseCPU *oldCPU)
196{
197    BaseCPU::takeOverFrom(oldCPU);
198
199    assert(!tickEvent.scheduled());
200
201    // if any of this CPU's ExecContexts are active, mark the CPU as
202    // running and schedule its tick event.
203    for (int i = 0; i < execContexts.size(); ++i) {
204        ExecContext *xc = execContexts[i];
205        if (xc->status() == ExecContext::Active && _status != Running) {
206            _status = Running;
207            tickEvent.schedule(curTick + 1);
208        }
209    }
210}
211
212
213void
214SimpleCPU::regStats()
215{
216    BaseCPU::regStats();
217
218    numInsts
219        .name(name() + ".num_insts")
220        .desc("Number of instructions executed")
221        ;
222
223    numMemRefs
224        .name(name() + ".num_refs")
225        .desc("Number of memory references")
226        ;
227
228    idleCycles
229        .name(name() + ".idle_cycles")
230        .desc("Number of idle cycles")
231        ;
232
233    idleFraction
234        .name(name() + ".idle_fraction")
235        .desc("Percentage of idle cycles")
236        ;
237
238    icacheStallCycles
239        .name(name() + ".icache_stall_cycles")
240        .desc("ICache total stall cycles")
241        .prereq(icacheStallCycles)
242        ;
243
244    dcacheStallCycles
245        .name(name() + ".dcache_stall_cycles")
246        .desc("DCache total stall cycles")
247        .prereq(dcacheStallCycles)
248        ;
249
250    idleFraction = idleCycles / simTicks;
251
252    numInsts = Statistics::scalar(numInst);
253    simInsts += numInsts;
254}
255
256void
257SimpleCPU::serialize()
258{
259    nameOut();
260
261#ifdef FULL_SYSTEM
262#if 0
263    // do we need this anymore?? egh
264    childOut("itb", xc->itb);
265    childOut("dtb", xc->dtb);
266    childOut("physmem", physmem);
267#endif
268#endif
269
270    for (int i = 0; i < NumIntRegs; i++) {
271        stringstream buf;
272        ccprintf(buf, "R%02d", i);
273        paramOut(buf.str(), xc->regs.intRegFile[i]);
274    }
275    for (int i = 0; i < NumFloatRegs; i++) {
276        stringstream buf;
277        ccprintf(buf, "F%02d", i);
278        paramOut(buf.str(), xc->regs.floatRegFile.d[i]);
279    }
280    // CPUTraitsType::serializeSpecialRegs(getProxy(), xc->regs);
281}
282
283void
284SimpleCPU::unserialize(IniFile &db, const string &category, ConfigNode *node)
285{
286    string data;
287
288    for (int i = 0; i < NumIntRegs; i++) {
289        stringstream buf;
290        ccprintf(buf, "R%02d", i);
291        db.findDefault(category, buf.str(), data);
292        to_number(data,xc->regs.intRegFile[i]);
293    }
294    for (int i = 0; i < NumFloatRegs; i++) {
295        stringstream buf;
296        ccprintf(buf, "F%02d", i);
297        db.findDefault(category, buf.str(), data);
298        xc->regs.floatRegFile.d[i] = strtod(data.c_str(),NULL);
299    }
300
301    // Read in Special registers
302
303    // CPUTraitsType::unserializeSpecialRegs(db,category,node,xc->regs);
304}
305
306void
307change_thread_state(int thread_number, int activate, int priority)
308{
309}
310
311// precise architected memory state accessor macros
312template <class T>
313Fault
314SimpleCPU::read(Addr addr, T& data, unsigned flags)
315{
316    memReq->reset(addr, sizeof(T), flags);
317
318    // translate to physical address
319    Fault fault = xc->translateDataReadReq(memReq);
320
321    // do functional access
322    if (fault == No_Fault)
323        fault = xc->read(memReq, data);
324
325    if (traceData) {
326        traceData->setAddr(addr);
327        if (fault == No_Fault)
328            traceData->setData(data);
329    }
330
331    // if we have a cache, do cache access too
332    if (fault == No_Fault && dcacheInterface) {
333        memReq->cmd = Read;
334        memReq->completionEvent = NULL;
335        memReq->time = curTick;
336        memReq->flags &= ~UNCACHEABLE;
337        MemAccessResult result = dcacheInterface->access(memReq);
338
339        // Ugly hack to get an event scheduled *only* if the access is
340        // a miss.  We really should add first-class support for this
341        // at some point.
342        if (result != MA_HIT && dcacheInterface->doEvents) {
343            memReq->completionEvent = &cacheCompletionEvent;
344            setStatus(DcacheMissStall);
345        }
346    }
347
348    return fault;
349}
350
351#ifndef DOXYGEN_SHOULD_SKIP_THIS
352
353template
354Fault
355SimpleCPU::read(Addr addr, uint64_t& data, unsigned flags);
356
357template
358Fault
359SimpleCPU::read(Addr addr, uint32_t& data, unsigned flags);
360
361template
362Fault
363SimpleCPU::read(Addr addr, uint16_t& data, unsigned flags);
364
365template
366Fault
367SimpleCPU::read(Addr addr, uint8_t& data, unsigned flags);
368
369#endif //DOXYGEN_SHOULD_SKIP_THIS
370
371template<>
372Fault
373SimpleCPU::read(Addr addr, double& data, unsigned flags)
374{
375    return read(addr, *(uint64_t*)&data, flags);
376}
377
378template<>
379Fault
380SimpleCPU::read(Addr addr, float& data, unsigned flags)
381{
382    return read(addr, *(uint32_t*)&data, flags);
383}
384
385
386template<>
387Fault
388SimpleCPU::read(Addr addr, int32_t& data, unsigned flags)
389{
390    return read(addr, (uint32_t&)data, flags);
391}
392
393
394template <class T>
395Fault
396SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
397{
398    if (traceData) {
399        traceData->setAddr(addr);
400        traceData->setData(data);
401    }
402
403    memReq->reset(addr, sizeof(T), flags);
404
405    // translate to physical address
406    Fault fault = xc->translateDataWriteReq(memReq);
407
408    // do functional access
409    if (fault == No_Fault)
410        fault = xc->write(memReq, data);
411
412    if (fault == No_Fault && dcacheInterface) {
413        memReq->cmd = Write;
414        memcpy(memReq->data,(uint8_t *)&data,memReq->size);
415        memReq->completionEvent = NULL;
416        memReq->time = curTick;
417        memReq->flags &= ~UNCACHEABLE;
418        MemAccessResult result = dcacheInterface->access(memReq);
419
420        // Ugly hack to get an event scheduled *only* if the access is
421        // a miss.  We really should add first-class support for this
422        // at some point.
423        if (result != MA_HIT && dcacheInterface->doEvents) {
424            memReq->completionEvent = &cacheCompletionEvent;
425            setStatus(DcacheMissStall);
426        }
427    }
428
429    if (res && (fault == No_Fault))
430        *res = memReq->result;
431
432    return fault;
433}
434
435
436#ifndef DOXYGEN_SHOULD_SKIP_THIS
437template
438Fault
439SimpleCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res);
440
441template
442Fault
443SimpleCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res);
444
445template
446Fault
447SimpleCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res);
448
449template
450Fault
451SimpleCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res);
452
453#endif //DOXYGEN_SHOULD_SKIP_THIS
454
455template<>
456Fault
457SimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
458{
459    return write(*(uint64_t*)&data, addr, flags, res);
460}
461
462template<>
463Fault
464SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
465{
466    return write(*(uint32_t*)&data, addr, flags, res);
467}
468
469
470template<>
471Fault
472SimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
473{
474    return write((uint32_t)data, addr, flags, res);
475}
476
477
478#ifdef FULL_SYSTEM
479Addr
480SimpleCPU::dbg_vtophys(Addr addr)
481{
482    return vtophys(xc, addr);
483}
484#endif // FULL_SYSTEM
485
486Tick save_cycle = 0;
487
488
489void
490SimpleCPU::processCacheCompletion()
491{
492    switch (status()) {
493      case IcacheMissStall:
494        icacheStallCycles += curTick - lastIcacheStall;
495        setStatus(IcacheMissComplete);
496        break;
497      case DcacheMissStall:
498        dcacheStallCycles += curTick - lastDcacheStall;
499        setStatus(Running);
500        break;
501      case SwitchedOut:
502        // If this CPU has been switched out due to sampling/warm-up,
503        // ignore any further status changes (e.g., due to cache
504        // misses outstanding at the time of the switch).
505        return;
506      default:
507        panic("SimpleCPU::processCacheCompletion: bad state");
508        break;
509    }
510}
511
512#ifdef FULL_SYSTEM
513void
514SimpleCPU::post_interrupt(int int_num, int index)
515{
516    BaseCPU::post_interrupt(int_num, index);
517
518    if (xc->status() == ExecContext::Suspended) {
519                DPRINTF(IPI,"Suspended Processor awoke\n");
520        xc->setStatus(ExecContext::Active);
521        Annotate::Resume(xc);
522    }
523}
524#endif // FULL_SYSTEM
525
526/* start simulation, program loaded, processor precise state initialized */
527void
528SimpleCPU::tick()
529{
530    traceData = NULL;
531
532#ifdef FULL_SYSTEM
533    if (fault == No_Fault && AlphaISA::check_interrupts &&
534        xc->cpu->check_interrupts() &&
535        !PC_PAL(xc->regs.pc) &&
536        status() != IcacheMissComplete) {
537        int ipl = 0;
538        int summary = 0;
539        AlphaISA::check_interrupts = 0;
540        IntReg *ipr = xc->regs.ipr;
541
542        if (xc->regs.ipr[TheISA::IPR_SIRR]) {
543            for (int i = TheISA::INTLEVEL_SOFTWARE_MIN;
544                 i < TheISA::INTLEVEL_SOFTWARE_MAX; i++) {
545                if (ipr[TheISA::IPR_SIRR] & (ULL(1) << i)) {
546                    // See table 4-19 of 21164 hardware reference
547                    ipl = (i - TheISA::INTLEVEL_SOFTWARE_MIN) + 1;
548                    summary |= (ULL(1) << i);
549                }
550            }
551        }
552
553        uint64_t interrupts = xc->cpu->intr_status();
554        for (int i = TheISA::INTLEVEL_EXTERNAL_MIN;
555            i < TheISA::INTLEVEL_EXTERNAL_MAX; i++) {
556            if (interrupts & (ULL(1) << i)) {
557                // See table 4-19 of 21164 hardware reference
558                ipl = i;
559                summary |= (ULL(1) << i);
560            }
561        }
562
563        if (ipr[TheISA::IPR_ASTRR])
564            panic("asynchronous traps not implemented\n");
565
566        if (ipl && ipl > xc->regs.ipr[TheISA::IPR_IPLR]) {
567            ipr[TheISA::IPR_ISR] = summary;
568            ipr[TheISA::IPR_INTID] = ipl;
569            xc->ev5_trap(Interrupt_Fault);
570
571            DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
572                    ipr[TheISA::IPR_IPLR], ipl, summary);
573        }
574    }
575#endif
576
577    // maintain $r0 semantics
578    xc->regs.intRegFile[ZeroReg] = 0;
579#ifdef TARGET_ALPHA
580    xc->regs.floatRegFile.d[ZeroReg] = 0.0;
581#endif // TARGET_ALPHA
582
583    if (status() == IcacheMissComplete) {
584        // We've already fetched an instruction and were stalled on an
585        // I-cache miss.  No need to fetch it again.
586
587        setStatus(Running);
588    }
589    else {
590        // Try to fetch an instruction
591
592        // set up memory request for instruction fetch
593#ifdef FULL_SYSTEM
594#define IFETCH_FLAGS(pc)	((pc) & 1) ? PHYSICAL : 0
595#else
596#define IFETCH_FLAGS(pc)	0
597#endif
598
599        memReq->cmd = Read;
600        memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t),
601                     IFETCH_FLAGS(xc->regs.pc));
602
603        fault = xc->translateInstReq(memReq);
604
605        if (fault == No_Fault)
606            fault = xc->mem->read(memReq, inst);
607
608        if (icacheInterface && fault == No_Fault) {
609            memReq->completionEvent = NULL;
610
611            memReq->time = curTick;
612            memReq->flags &= ~UNCACHEABLE;
613            MemAccessResult result = icacheInterface->access(memReq);
614
615            // Ugly hack to get an event scheduled *only* if the access is
616            // a miss.  We really should add first-class support for this
617            // at some point.
618            if (result != MA_HIT && icacheInterface->doEvents) {
619                memReq->completionEvent = &cacheCompletionEvent;
620                setStatus(IcacheMissStall);
621                return;
622            }
623        }
624    }
625
626    // If we've got a valid instruction (i.e., no fault on instruction
627    // fetch), then execute it.
628    if (fault == No_Fault) {
629
630        // keep an instruction count
631        numInst++;
632
633        // check for instruction-count-based events
634        comInsnEventQueue[0]->serviceEvents(numInst);
635
636        // decode the instruction
637        StaticInstPtr<TheISA> si(inst);
638
639        traceData = Trace::getInstRecord(curTick, xc, this, si,
640                                         xc->regs.pc);
641
642#ifdef FULL_SYSTEM
643        xc->regs.opcode = (inst >> 26) & 0x3f;
644        xc->regs.ra = (inst >> 21) & 0x1f;
645#endif // FULL_SYSTEM
646
647        xc->func_exe_insn++;
648
649        fault = si->execute(this, xc, traceData);
650
651        if (si->isMemRef()) {
652            numMemRefs++;
653        }
654
655        if (si->isLoad()) {
656            ++numLoad;
657            comLoadEventQueue[0]->serviceEvents(numLoad);
658        }
659
660        if (traceData)
661            traceData->finalize();
662
663    }	// if (fault == No_Fault)
664
665    if (fault != No_Fault) {
666#ifdef FULL_SYSTEM
667        xc->ev5_trap(fault);
668#else // !FULL_SYSTEM
669        fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc);
670#endif // FULL_SYSTEM
671    }
672    else {
673        // go to the next instruction
674        xc->regs.pc = xc->regs.npc;
675        xc->regs.npc += sizeof(MachInst);
676    }
677
678#ifdef FULL_SYSTEM
679    Addr oldpc;
680    do {
681        oldpc = xc->regs.pc;
682        system->pcEventQueue.service(xc);
683    } while (oldpc != xc->regs.pc);
684#endif
685
686    assert(status() == Running ||
687           status() == Idle ||
688           status() == DcacheMissStall);
689
690    if (status() == Running && !tickEvent.scheduled())
691        tickEvent.schedule(curTick + 1);
692}
693
694
695////////////////////////////////////////////////////////////////////////
696//
697//  SimpleCPU Simulation Object
698//
699BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
700
701    Param<Counter> max_insts_any_thread;
702    Param<Counter> max_insts_all_threads;
703    Param<Counter> max_loads_any_thread;
704    Param<Counter> max_loads_all_threads;
705
706#ifdef FULL_SYSTEM
707    SimObjectParam<AlphaItb *> itb;
708    SimObjectParam<AlphaDtb *> dtb;
709    SimObjectParam<FunctionalMemory *> mem;
710    SimObjectParam<System *> system;
711    Param<int> mult;
712#else
713    SimObjectParam<Process *> workload;
714#endif // FULL_SYSTEM
715
716    SimObjectParam<BaseMem *> icache;
717    SimObjectParam<BaseMem *> dcache;
718
719    Param<bool> defer_registration;
720
721END_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
722
723BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
724
725    INIT_PARAM_DFLT(max_insts_any_thread,
726                    "terminate when any thread reaches this insn count",
727                    0),
728    INIT_PARAM_DFLT(max_insts_all_threads,
729                    "terminate when all threads have reached this insn count",
730                    0),
731    INIT_PARAM_DFLT(max_loads_any_thread,
732                    "terminate when any thread reaches this load count",
733                    0),
734    INIT_PARAM_DFLT(max_loads_all_threads,
735                    "terminate when all threads have reached this load count",
736                    0),
737
738#ifdef FULL_SYSTEM
739    INIT_PARAM(itb, "Instruction TLB"),
740    INIT_PARAM(dtb, "Data TLB"),
741    INIT_PARAM(mem, "memory"),
742    INIT_PARAM(system, "system object"),
743    INIT_PARAM_DFLT(mult, "system clock multiplier", 1),
744#else
745    INIT_PARAM(workload, "processes to run"),
746#endif // FULL_SYSTEM
747
748    INIT_PARAM_DFLT(icache, "L1 instruction cache object", NULL),
749    INIT_PARAM_DFLT(dcache, "L1 data cache object", NULL),
750    INIT_PARAM_DFLT(defer_registration, "defer registration with system "
751                    "(for sampling)", false)
752
753END_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
754
755
756CREATE_SIM_OBJECT(SimpleCPU)
757{
758    SimpleCPU *cpu;
759#ifdef FULL_SYSTEM
760    if (mult != 1)
761        panic("processor clock multiplier must be 1\n");
762
763    cpu = new SimpleCPU(getInstanceName(), system,
764                        max_insts_any_thread, max_insts_all_threads,
765                        max_loads_any_thread, max_loads_all_threads,
766                        itb, dtb, mem,
767                        (icache) ? icache->getInterface() : NULL,
768                        (dcache) ? dcache->getInterface() : NULL,
769                        ticksPerSecond * mult);
770#else
771
772    cpu = new SimpleCPU(getInstanceName(), workload,
773                        max_insts_any_thread, max_insts_all_threads,
774                        max_loads_any_thread, max_loads_all_threads,
775                        icache->getInterface(), dcache->getInterface());
776
777#endif // FULL_SYSTEM
778
779    if (!defer_registration) {
780        cpu->registerExecContexts();
781    }
782
783    return cpu;
784}
785
786REGISTER_SIM_OBJECT("SimpleCPU", SimpleCPU)
787