base.cc revision 13836
13569Sgblack@eecs.umich.edu/* 23569Sgblack@eecs.umich.edu * Copyright (c) 2010-2012, 2015, 2017 ARM Limited 33569Sgblack@eecs.umich.edu * Copyright (c) 2013 Advanced Micro Devices, Inc. 43569Sgblack@eecs.umich.edu * All rights reserved 53569Sgblack@eecs.umich.edu * 63569Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 73569Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 83569Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 93569Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 103569Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 113569Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 123569Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 133569Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 143569Sgblack@eecs.umich.edu * 153569Sgblack@eecs.umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 163569Sgblack@eecs.umich.edu * All rights reserved. 173569Sgblack@eecs.umich.edu * 183569Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 193569Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 203569Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 213569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 223569Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 233569Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 243569Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 253569Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 263569Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 273569Sgblack@eecs.umich.edu * this software without specific prior written permission. 283804Ssaidi@eecs.umich.edu * 293569Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 303569Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 313918Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 323918Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 333804Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 347678Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356335Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 363569Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 373824Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 383811Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 398229Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 403811Ssaidi@eecs.umich.edu * 418232Snate@binkert.org * Authors: Steve Reinhardt 428232Snate@binkert.org */ 433823Ssaidi@eecs.umich.edu 443823Ssaidi@eecs.umich.edu#include "cpu/simple/base.hh" 458751Sgblack@eecs.umich.edu 464103Ssaidi@eecs.umich.edu#include "arch/kernel_stats.hh" 473569Sgblack@eecs.umich.edu#include "arch/stacktrace.hh" 483804Ssaidi@eecs.umich.edu#include "arch/utility.hh" 493804Ssaidi@eecs.umich.edu#include "arch/vtophys.hh" 504088Sbinkertn@umich.edu#include "base/cp_annotate.hh" 513569Sgblack@eecs.umich.edu#include "base/cprintf.hh" 525034Smilesck@eecs.umich.edu#include "base/inifile.hh" 535358Sgblack@eecs.umich.edu#include "base/loader/symtab.hh" 548374Sksewell@umich.edu#include "base/logging.hh" 553804Ssaidi@eecs.umich.edu#include "base/pollevent.hh" 563804Ssaidi@eecs.umich.edu#include "base/trace.hh" 573804Ssaidi@eecs.umich.edu#include "base/types.hh" 585555Snate@binkert.org#include "config/the_isa.hh" 593569Sgblack@eecs.umich.edu#include "cpu/base.hh" 603804Ssaidi@eecs.umich.edu#include "cpu/checker/cpu.hh" 613918Ssaidi@eecs.umich.edu#include "cpu/checker/thread_context.hh" 623881Ssaidi@eecs.umich.edu#include "cpu/exetrace.hh" 633881Ssaidi@eecs.umich.edu#include "cpu/pred/bpred_unit.hh" 643881Ssaidi@eecs.umich.edu#include "cpu/profile.hh" 654990Sgblack@eecs.umich.edu#include "cpu/simple/exec_context.hh" 664990Sgblack@eecs.umich.edu#include "cpu/simple_thread.hh" 674990Sgblack@eecs.umich.edu#include "cpu/smt.hh" 684990Sgblack@eecs.umich.edu#include "cpu/static_inst.hh" 694990Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 704990Sgblack@eecs.umich.edu#include "debug/Decode.hh" 714990Sgblack@eecs.umich.edu#include "debug/Fetch.hh" 724990Sgblack@eecs.umich.edu#include "debug/Quiesce.hh" 734990Sgblack@eecs.umich.edu#include "mem/mem_object.hh" 746022Sgblack@eecs.umich.edu#include "mem/packet.hh" 756022Sgblack@eecs.umich.edu#include "mem/request.hh" 766022Sgblack@eecs.umich.edu#include "params/BaseSimpleCPU.hh" 773804Ssaidi@eecs.umich.edu#include "sim/byteswap.hh" 783569Sgblack@eecs.umich.edu#include "sim/debug.hh" 793804Ssaidi@eecs.umich.edu#include "sim/faults.hh" 803804Ssaidi@eecs.umich.edu#include "sim/full_system.hh" 813804Ssaidi@eecs.umich.edu#include "sim/sim_events.hh" 823804Ssaidi@eecs.umich.edu#include "sim/sim_object.hh" 833881Ssaidi@eecs.umich.edu#include "sim/stats.hh" 843804Ssaidi@eecs.umich.edu#include "sim/system.hh" 853804Ssaidi@eecs.umich.edu 863804Ssaidi@eecs.umich.eduusing namespace std; 873804Ssaidi@eecs.umich.eduusing namespace TheISA; 883804Ssaidi@eecs.umich.edu 893804Ssaidi@eecs.umich.eduBaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p) 903804Ssaidi@eecs.umich.edu : BaseCPU(p), 913569Sgblack@eecs.umich.edu curThread(0), 923569Sgblack@eecs.umich.edu branchPred(p->branchPred), 933804Ssaidi@eecs.umich.edu traceData(NULL), 943804Ssaidi@eecs.umich.edu inst(), 953826Ssaidi@eecs.umich.edu _status(Idle) 963804Ssaidi@eecs.umich.edu{ 973804Ssaidi@eecs.umich.edu SimpleThread *thread; 983826Ssaidi@eecs.umich.edu 993907Ssaidi@eecs.umich.edu for (unsigned i = 0; i < numThreads; i++) { 1003826Ssaidi@eecs.umich.edu if (FullSystem) { 1013811Ssaidi@eecs.umich.edu thread = new SimpleThread(this, i, p->system, 1023836Ssaidi@eecs.umich.edu p->itb, p->dtb, p->isa[i]); 1033915Ssaidi@eecs.umich.edu } else { 1043907Ssaidi@eecs.umich.edu thread = new SimpleThread(this, i, p->system, p->workload[i], 1053881Ssaidi@eecs.umich.edu p->itb, p->dtb, p->isa[i]); 1063881Ssaidi@eecs.umich.edu } 1073881Ssaidi@eecs.umich.edu threadInfo.push_back(new SimpleExecContext(this, thread)); 1083881Ssaidi@eecs.umich.edu ThreadContext *tc = thread->getTC(); 1093907Ssaidi@eecs.umich.edu threadContexts.push_back(tc); 1103881Ssaidi@eecs.umich.edu } 1115555Snate@binkert.org 1125555Snate@binkert.org if (p->checker) { 1135555Snate@binkert.org if (numThreads != 1) 1143881Ssaidi@eecs.umich.edu fatal("Checker currently does not support SMT"); 1153881Ssaidi@eecs.umich.edu 1163907Ssaidi@eecs.umich.edu BaseCPU *temp_checker = p->checker; 1173907Ssaidi@eecs.umich.edu checker = dynamic_cast<CheckerCPU *>(temp_checker); 1183907Ssaidi@eecs.umich.edu checker->setSystem(p->system); 1193907Ssaidi@eecs.umich.edu // Manipulate thread context 1203907Ssaidi@eecs.umich.edu ThreadContext *cpu_tc = threadContexts[0]; 1213907Ssaidi@eecs.umich.edu threadContexts[0] = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker); 1223907Ssaidi@eecs.umich.edu } else { 1233907Ssaidi@eecs.umich.edu checker = NULL; 1243907Ssaidi@eecs.umich.edu } 1253907Ssaidi@eecs.umich.edu} 1263907Ssaidi@eecs.umich.edu 1273907Ssaidi@eecs.umich.eduvoid 1283907Ssaidi@eecs.umich.eduBaseSimpleCPU::init() 1293907Ssaidi@eecs.umich.edu{ 1303907Ssaidi@eecs.umich.edu BaseCPU::init(); 1313907Ssaidi@eecs.umich.edu 1323907Ssaidi@eecs.umich.edu for (auto tc : threadContexts) { 1333907Ssaidi@eecs.umich.edu // Initialise the ThreadContext's memory proxies 1343907Ssaidi@eecs.umich.edu tc->initMemProxies(tc); 1353907Ssaidi@eecs.umich.edu 1363907Ssaidi@eecs.umich.edu if (FullSystem && !params()->switched_out) { 1373826Ssaidi@eecs.umich.edu // initialize CPU, including PC 1383826Ssaidi@eecs.umich.edu TheISA::initCPU(tc, tc->contextId()); 1393826Ssaidi@eecs.umich.edu } 1403826Ssaidi@eecs.umich.edu } 1413881Ssaidi@eecs.umich.edu} 1423881Ssaidi@eecs.umich.edu 1433881Ssaidi@eecs.umich.eduvoid 1443881Ssaidi@eecs.umich.eduBaseSimpleCPU::checkPcEventQueue() 1453881Ssaidi@eecs.umich.edu{ 1463881Ssaidi@eecs.umich.edu Addr oldpc, pc = threadInfo[curThread]->thread->instAddr(); 1473881Ssaidi@eecs.umich.edu do { 1483881Ssaidi@eecs.umich.edu oldpc = pc; 1493881Ssaidi@eecs.umich.edu system->pcEventQueue.service(threadContexts[curThread]); 1503881Ssaidi@eecs.umich.edu pc = threadInfo[curThread]->thread->instAddr(); 1513881Ssaidi@eecs.umich.edu } while (oldpc != pc); 1523881Ssaidi@eecs.umich.edu} 1533881Ssaidi@eecs.umich.edu 1543881Ssaidi@eecs.umich.eduvoid 1553569Sgblack@eecs.umich.eduBaseSimpleCPU::swapActiveThread() 1563569Sgblack@eecs.umich.edu{ 1573881Ssaidi@eecs.umich.edu if (numThreads > 1) { 1583804Ssaidi@eecs.umich.edu if ((!curStaticInst || !curStaticInst->isDelayedCommit()) && 1593881Ssaidi@eecs.umich.edu !threadInfo[curThread]->stayAtPC) { 1603826Ssaidi@eecs.umich.edu // Swap active threads 1613881Ssaidi@eecs.umich.edu if (!activeThreads.empty()) { 1623881Ssaidi@eecs.umich.edu curThread = activeThreads.front(); 1633881Ssaidi@eecs.umich.edu activeThreads.pop_front(); 1643907Ssaidi@eecs.umich.edu activeThreads.push_back(curThread); 1653907Ssaidi@eecs.umich.edu } 1663929Ssaidi@eecs.umich.edu } 1673929Ssaidi@eecs.umich.edu } 1683907Ssaidi@eecs.umich.edu} 1693907Ssaidi@eecs.umich.edu 1703804Ssaidi@eecs.umich.eduvoid 1713804Ssaidi@eecs.umich.eduBaseSimpleCPU::countInst() 1723881Ssaidi@eecs.umich.edu{ 1733804Ssaidi@eecs.umich.edu SimpleExecContext& t_info = *threadInfo[curThread]; 1743804Ssaidi@eecs.umich.edu 1753804Ssaidi@eecs.umich.edu if (!curStaticInst->isMicroop() || curStaticInst->isLastMicroop()) { 1763804Ssaidi@eecs.umich.edu t_info.numInst++; 1773804Ssaidi@eecs.umich.edu t_info.numInsts++; 1783804Ssaidi@eecs.umich.edu 1793804Ssaidi@eecs.umich.edu system->totalNumInsts++; 1803569Sgblack@eecs.umich.edu t_info.thread->funcExeInst++; 1813863Ssaidi@eecs.umich.edu } 1823863Ssaidi@eecs.umich.edu t_info.numOp++; 1833804Ssaidi@eecs.umich.edu t_info.numOps++; 1845555Snate@binkert.org} 1855555Snate@binkert.org 1863804Ssaidi@eecs.umich.eduCounter 1873804Ssaidi@eecs.umich.eduBaseSimpleCPU::totalInsts() const 1883804Ssaidi@eecs.umich.edu{ 1893804Ssaidi@eecs.umich.edu Counter total_inst = 0; 1903804Ssaidi@eecs.umich.edu for (auto& t_info : threadInfo) { 1913569Sgblack@eecs.umich.edu total_inst += t_info->numInst; 1923804Ssaidi@eecs.umich.edu } 1933804Ssaidi@eecs.umich.edu 1943804Ssaidi@eecs.umich.edu return total_inst; 1955555Snate@binkert.org} 1965555Snate@binkert.org 1973804Ssaidi@eecs.umich.eduCounter 1983804Ssaidi@eecs.umich.eduBaseSimpleCPU::totalOps() const 1993804Ssaidi@eecs.umich.edu{ 2003804Ssaidi@eecs.umich.edu Counter total_op = 0; 2013804Ssaidi@eecs.umich.edu for (auto& t_info : threadInfo) { 2023811Ssaidi@eecs.umich.edu total_op += t_info->numOp; 2033811Ssaidi@eecs.umich.edu } 2043804Ssaidi@eecs.umich.edu 2053804Ssaidi@eecs.umich.edu return total_op; 2065312Sgblack@eecs.umich.edu} 2073804Ssaidi@eecs.umich.edu 2083804Ssaidi@eecs.umich.eduBaseSimpleCPU::~BaseSimpleCPU() 2093804Ssaidi@eecs.umich.edu{ 2103804Ssaidi@eecs.umich.edu} 2113804Ssaidi@eecs.umich.edu 2123804Ssaidi@eecs.umich.eduvoid 2133804Ssaidi@eecs.umich.eduBaseSimpleCPU::haltContext(ThreadID thread_num) 2143811Ssaidi@eecs.umich.edu{ 2153804Ssaidi@eecs.umich.edu // for now, these are equivalent 2163804Ssaidi@eecs.umich.edu suspendContext(thread_num); 2173804Ssaidi@eecs.umich.edu updateCycleCounters(BaseCPU::CPU_STATE_SLEEP); 2183804Ssaidi@eecs.umich.edu} 2193804Ssaidi@eecs.umich.edu 2203826Ssaidi@eecs.umich.edu 2213826Ssaidi@eecs.umich.eduvoid 2224070Ssaidi@eecs.umich.eduBaseSimpleCPU::regStats() 2235555Snate@binkert.org{ 2245555Snate@binkert.org using namespace Stats; 2254070Ssaidi@eecs.umich.edu 2263804Ssaidi@eecs.umich.edu BaseCPU::regStats(); 2273804Ssaidi@eecs.umich.edu 2283804Ssaidi@eecs.umich.edu for (ThreadID tid = 0; tid < numThreads; tid++) { 2293804Ssaidi@eecs.umich.edu SimpleExecContext& t_info = *threadInfo[tid]; 2303804Ssaidi@eecs.umich.edu 2313804Ssaidi@eecs.umich.edu std::string thread_str = name(); 2323804Ssaidi@eecs.umich.edu if (numThreads > 1) 2333804Ssaidi@eecs.umich.edu thread_str += ".thread" + std::to_string(tid); 2343804Ssaidi@eecs.umich.edu 2353804Ssaidi@eecs.umich.edu t_info.numInsts 2363804Ssaidi@eecs.umich.edu .name(thread_str + ".committedInsts") 2373804Ssaidi@eecs.umich.edu .desc("Number of instructions committed") 2383826Ssaidi@eecs.umich.edu ; 2393826Ssaidi@eecs.umich.edu 2403826Ssaidi@eecs.umich.edu t_info.numOps 2413863Ssaidi@eecs.umich.edu .name(thread_str + ".committedOps") 2423826Ssaidi@eecs.umich.edu .desc("Number of ops (including micro ops) committed") 2433826Ssaidi@eecs.umich.edu ; 2443826Ssaidi@eecs.umich.edu 2453826Ssaidi@eecs.umich.edu t_info.numIntAluAccesses 2463826Ssaidi@eecs.umich.edu .name(thread_str + ".num_int_alu_accesses") 2473826Ssaidi@eecs.umich.edu .desc("Number of integer alu accesses") 2483826Ssaidi@eecs.umich.edu ; 2493826Ssaidi@eecs.umich.edu 2503826Ssaidi@eecs.umich.edu t_info.numFpAluAccesses 2513804Ssaidi@eecs.umich.edu .name(thread_str + ".num_fp_alu_accesses") 2523804Ssaidi@eecs.umich.edu .desc("Number of float alu accesses") 2533804Ssaidi@eecs.umich.edu ; 2543804Ssaidi@eecs.umich.edu 2553804Ssaidi@eecs.umich.edu t_info.numVecAluAccesses 2563804Ssaidi@eecs.umich.edu .name(thread_str + ".num_vec_alu_accesses") 2573804Ssaidi@eecs.umich.edu .desc("Number of vector alu accesses") 2583863Ssaidi@eecs.umich.edu ; 2593863Ssaidi@eecs.umich.edu 2603863Ssaidi@eecs.umich.edu t_info.numCallsReturns 2613836Ssaidi@eecs.umich.edu .name(thread_str + ".num_func_calls") 2623836Ssaidi@eecs.umich.edu .desc("number of times a function call or return occured") 2633804Ssaidi@eecs.umich.edu ; 2643804Ssaidi@eecs.umich.edu 2655312Sgblack@eecs.umich.edu t_info.numCondCtrlInsts 2663804Ssaidi@eecs.umich.edu .name(thread_str + ".num_conditional_control_insts") 2673804Ssaidi@eecs.umich.edu .desc("number of instructions that are conditional controls") 2683804Ssaidi@eecs.umich.edu ; 2693804Ssaidi@eecs.umich.edu 2703804Ssaidi@eecs.umich.edu t_info.numIntInsts 2713804Ssaidi@eecs.umich.edu .name(thread_str + ".num_int_insts") 2723804Ssaidi@eecs.umich.edu .desc("number of integer instructions") 2733863Ssaidi@eecs.umich.edu ; 2743804Ssaidi@eecs.umich.edu 2753804Ssaidi@eecs.umich.edu t_info.numFpInsts 2763804Ssaidi@eecs.umich.edu .name(thread_str + ".num_fp_insts") 2773804Ssaidi@eecs.umich.edu .desc("number of float instructions") 2783804Ssaidi@eecs.umich.edu ; 2793881Ssaidi@eecs.umich.edu 2803804Ssaidi@eecs.umich.edu t_info.numVecInsts 2813804Ssaidi@eecs.umich.edu .name(thread_str + ".num_vec_insts") 2823804Ssaidi@eecs.umich.edu .desc("number of vector instructions") 2833804Ssaidi@eecs.umich.edu ; 2843804Ssaidi@eecs.umich.edu 2853804Ssaidi@eecs.umich.edu t_info.numIntRegReads 2863804Ssaidi@eecs.umich.edu .name(thread_str + ".num_int_register_reads") 2873863Ssaidi@eecs.umich.edu .desc("number of times the integer registers were read") 2883863Ssaidi@eecs.umich.edu ; 2893836Ssaidi@eecs.umich.edu 2905555Snate@binkert.org t_info.numIntRegWrites 2913804Ssaidi@eecs.umich.edu .name(thread_str + ".num_int_register_writes") 2923804Ssaidi@eecs.umich.edu .desc("number of times the integer registers were written") 29310231Ssteve.reinhardt@amd.com ; 2943881Ssaidi@eecs.umich.edu 2953881Ssaidi@eecs.umich.edu t_info.numFpRegReads 2963804Ssaidi@eecs.umich.edu .name(thread_str + ".num_fp_register_reads") 2973804Ssaidi@eecs.umich.edu .desc("number of times the floating registers were read") 2983804Ssaidi@eecs.umich.edu ; 2993804Ssaidi@eecs.umich.edu 3003804Ssaidi@eecs.umich.edu t_info.numFpRegWrites 3013804Ssaidi@eecs.umich.edu .name(thread_str + ".num_fp_register_writes") 3023804Ssaidi@eecs.umich.edu .desc("number of times the floating registers were written") 3033804Ssaidi@eecs.umich.edu ; 3043804Ssaidi@eecs.umich.edu 3053804Ssaidi@eecs.umich.edu t_info.numVecRegReads 3063804Ssaidi@eecs.umich.edu .name(thread_str + ".num_vec_register_reads") 3073804Ssaidi@eecs.umich.edu .desc("number of times the vector registers were read") 3083804Ssaidi@eecs.umich.edu ; 3093863Ssaidi@eecs.umich.edu 3103836Ssaidi@eecs.umich.edu t_info.numVecRegWrites 3115555Snate@binkert.org .name(thread_str + ".num_vec_register_writes") 3125288Sgblack@eecs.umich.edu .desc("number of times the vector registers were written") 3135288Sgblack@eecs.umich.edu ; 3145288Sgblack@eecs.umich.edu 3153804Ssaidi@eecs.umich.edu t_info.numCCRegReads 3163804Ssaidi@eecs.umich.edu .name(thread_str + ".num_cc_register_reads") 3173804Ssaidi@eecs.umich.edu .desc("number of times the CC registers were read") 3183804Ssaidi@eecs.umich.edu .flags(nozero) 3193804Ssaidi@eecs.umich.edu ; 3203804Ssaidi@eecs.umich.edu 3213804Ssaidi@eecs.umich.edu t_info.numCCRegWrites 3223804Ssaidi@eecs.umich.edu .name(thread_str + ".num_cc_register_writes") 3233804Ssaidi@eecs.umich.edu .desc("number of times the CC registers were written") 3243804Ssaidi@eecs.umich.edu .flags(nozero) 3253804Ssaidi@eecs.umich.edu ; 3269423SAndreas.Sandberg@arm.com 3273804Ssaidi@eecs.umich.edu t_info.numMemRefs 3283836Ssaidi@eecs.umich.edu .name(thread_str + ".num_mem_refs") 3295555Snate@binkert.org .desc("number of memory refs") 3303836Ssaidi@eecs.umich.edu ; 3315555Snate@binkert.org 33210231Ssteve.reinhardt@amd.com t_info.numStoreInsts 3333881Ssaidi@eecs.umich.edu .name(thread_str + ".num_store_insts") 3343804Ssaidi@eecs.umich.edu .desc("Number of store instructions") 3353907Ssaidi@eecs.umich.edu ; 3363804Ssaidi@eecs.umich.edu 3373804Ssaidi@eecs.umich.edu t_info.numLoadInsts 3383804Ssaidi@eecs.umich.edu .name(thread_str + ".num_load_insts") 3393804Ssaidi@eecs.umich.edu .desc("Number of load instructions") 3403804Ssaidi@eecs.umich.edu ; 3415555Snate@binkert.org 3425555Snate@binkert.org t_info.notIdleFraction 3433881Ssaidi@eecs.umich.edu .name(thread_str + ".not_idle_fraction") 3443881Ssaidi@eecs.umich.edu .desc("Percentage of non-idle cycles") 3453881Ssaidi@eecs.umich.edu ; 3463804Ssaidi@eecs.umich.edu 3473881Ssaidi@eecs.umich.edu t_info.idleFraction 3483881Ssaidi@eecs.umich.edu .name(thread_str + ".idle_fraction") 3493881Ssaidi@eecs.umich.edu .desc("Percentage of idle cycles") 3503881Ssaidi@eecs.umich.edu ; 3513804Ssaidi@eecs.umich.edu 3523804Ssaidi@eecs.umich.edu t_info.numBusyCycles 3533804Ssaidi@eecs.umich.edu .name(thread_str + ".num_busy_cycles") 3545555Snate@binkert.org .desc("Number of busy cycles") 3555555Snate@binkert.org ; 3563804Ssaidi@eecs.umich.edu 3573804Ssaidi@eecs.umich.edu t_info.numIdleCycles 3583881Ssaidi@eecs.umich.edu .name(thread_str + ".num_idle_cycles") 3593881Ssaidi@eecs.umich.edu .desc("Number of idle cycles") 3603804Ssaidi@eecs.umich.edu ; 3613881Ssaidi@eecs.umich.edu 3623881Ssaidi@eecs.umich.edu t_info.icacheStallCycles 3633881Ssaidi@eecs.umich.edu .name(thread_str + ".icache_stall_cycles") 3643804Ssaidi@eecs.umich.edu .desc("ICache total stall cycles") 3653804Ssaidi@eecs.umich.edu .prereq(t_info.icacheStallCycles) 3663804Ssaidi@eecs.umich.edu ; 3673804Ssaidi@eecs.umich.edu 3683804Ssaidi@eecs.umich.edu t_info.dcacheStallCycles 3693804Ssaidi@eecs.umich.edu .name(thread_str + ".dcache_stall_cycles") 3703804Ssaidi@eecs.umich.edu .desc("DCache total stall cycles") 3713804Ssaidi@eecs.umich.edu .prereq(t_info.dcacheStallCycles) 3723804Ssaidi@eecs.umich.edu ; 3733804Ssaidi@eecs.umich.edu 3743804Ssaidi@eecs.umich.edu t_info.statExecutedInstType 3753804Ssaidi@eecs.umich.edu .init(Enums::Num_OpClass) 3763804Ssaidi@eecs.umich.edu .name(thread_str + ".op_class") 3773804Ssaidi@eecs.umich.edu .desc("Class of executed instruction") 3783804Ssaidi@eecs.umich.edu .flags(total | pdf | dist) 3793804Ssaidi@eecs.umich.edu ; 3804990Sgblack@eecs.umich.edu 3813804Ssaidi@eecs.umich.edu for (unsigned i = 0; i < Num_OpClasses; ++i) { 3823804Ssaidi@eecs.umich.edu t_info.statExecutedInstType.subname(i, Enums::OpClassStrings[i]); 3833804Ssaidi@eecs.umich.edu } 3843804Ssaidi@eecs.umich.edu 3853804Ssaidi@eecs.umich.edu t_info.idleFraction = constant(1.0) - t_info.notIdleFraction; 3863804Ssaidi@eecs.umich.edu t_info.numIdleCycles = t_info.idleFraction * numCycles; 3873804Ssaidi@eecs.umich.edu t_info.numBusyCycles = t_info.notIdleFraction * numCycles; 3883804Ssaidi@eecs.umich.edu 3893804Ssaidi@eecs.umich.edu t_info.numBranches 3903804Ssaidi@eecs.umich.edu .name(thread_str + ".Branches") 3913804Ssaidi@eecs.umich.edu .desc("Number of branches fetched") 3923804Ssaidi@eecs.umich.edu .prereq(t_info.numBranches); 3933804Ssaidi@eecs.umich.edu 3943804Ssaidi@eecs.umich.edu t_info.numPredictedBranches 3953804Ssaidi@eecs.umich.edu .name(thread_str + ".predictedBranches") 3963826Ssaidi@eecs.umich.edu .desc("Number of branches predicted as taken") 3974990Sgblack@eecs.umich.edu .prereq(t_info.numPredictedBranches); 3983826Ssaidi@eecs.umich.edu 3993916Ssaidi@eecs.umich.edu t_info.numBranchMispred 4003916Ssaidi@eecs.umich.edu .name(thread_str + ".BranchMispred") 4013916Ssaidi@eecs.umich.edu .desc("Number of branch mispredictions") 4024990Sgblack@eecs.umich.edu .prereq(t_info.numBranchMispred); 4033826Ssaidi@eecs.umich.edu } 4043804Ssaidi@eecs.umich.edu} 4053804Ssaidi@eecs.umich.edu 4066022Sgblack@eecs.umich.eduvoid 4073804Ssaidi@eecs.umich.eduBaseSimpleCPU::resetStats() 4083804Ssaidi@eecs.umich.edu{ 4096022Sgblack@eecs.umich.edu for (auto &thread_info : threadInfo) { 4103811Ssaidi@eecs.umich.edu thread_info->notIdleFraction = (_status != Idle); 4114990Sgblack@eecs.umich.edu } 4124990Sgblack@eecs.umich.edu} 4133804Ssaidi@eecs.umich.edu 4143804Ssaidi@eecs.umich.eduvoid 4153804Ssaidi@eecs.umich.eduBaseSimpleCPU::serializeThread(CheckpointOut &cp, ThreadID tid) const 4166022Sgblack@eecs.umich.edu{ 4173804Ssaidi@eecs.umich.edu assert(_status == Idle || _status == Running); 4184172Ssaidi@eecs.umich.edu 4193833Ssaidi@eecs.umich.edu threadInfo[tid]->thread->serialize(cp); 4203836Ssaidi@eecs.umich.edu} 4213836Ssaidi@eecs.umich.edu 4223836Ssaidi@eecs.umich.eduvoid 4239912Sandreas@sandberg.pp.seBaseSimpleCPU::unserializeThread(CheckpointIn &cp, ThreadID tid) 4243836Ssaidi@eecs.umich.edu{ 4253836Ssaidi@eecs.umich.edu threadInfo[tid]->thread->unserialize(cp); 4263836Ssaidi@eecs.umich.edu} 4273836Ssaidi@eecs.umich.edu 4283836Ssaidi@eecs.umich.eduvoid 4293836Ssaidi@eecs.umich.educhange_thread_state(ThreadID tid, int activate, int priority) 4306022Sgblack@eecs.umich.edu{ 4316022Sgblack@eecs.umich.edu} 4326022Sgblack@eecs.umich.edu 4336022Sgblack@eecs.umich.eduAddr 4345555Snate@binkert.orgBaseSimpleCPU::dbg_vtophys(Addr addr) 4353836Ssaidi@eecs.umich.edu{ 4363836Ssaidi@eecs.umich.edu return vtophys(threadContexts[curThread], addr); 4373836Ssaidi@eecs.umich.edu} 4383836Ssaidi@eecs.umich.edu 4393836Ssaidi@eecs.umich.eduvoid 4403836Ssaidi@eecs.umich.eduBaseSimpleCPU::wakeup(ThreadID tid) 4413836Ssaidi@eecs.umich.edu{ 4423833Ssaidi@eecs.umich.edu getCpuAddrMonitor(tid)->gotWakeup = true; 4433833Ssaidi@eecs.umich.edu 4443833Ssaidi@eecs.umich.edu if (threadInfo[tid]->thread->status() == ThreadContext::Suspended) { 4453833Ssaidi@eecs.umich.edu DPRINTF(Quiesce,"[tid:%d] Suspended Processor awoke\n", tid); 4463833Ssaidi@eecs.umich.edu threadInfo[tid]->thread->activate(); 4473833Ssaidi@eecs.umich.edu } 4483833Ssaidi@eecs.umich.edu} 4493833Ssaidi@eecs.umich.edu 4503833Ssaidi@eecs.umich.eduvoid 4513804Ssaidi@eecs.umich.eduBaseSimpleCPU::checkForInterrupts() 4523804Ssaidi@eecs.umich.edu{ 4533804Ssaidi@eecs.umich.edu SimpleExecContext&t_info = *threadInfo[curThread]; 4543804Ssaidi@eecs.umich.edu SimpleThread* thread = t_info.thread; 4553804Ssaidi@eecs.umich.edu ThreadContext* tc = thread->getTC(); 4563833Ssaidi@eecs.umich.edu 4573833Ssaidi@eecs.umich.edu if (checkInterrupts(tc)) { 4583811Ssaidi@eecs.umich.edu Fault interrupt = interrupts[curThread]->getInterrupt(tc); 4593804Ssaidi@eecs.umich.edu 4603804Ssaidi@eecs.umich.edu if (interrupt != NoFault) { 4613804Ssaidi@eecs.umich.edu t_info.fetchOffset = 0; 4623804Ssaidi@eecs.umich.edu interrupts[curThread]->updateIntrInfo(tc); 4633804Ssaidi@eecs.umich.edu interrupt->invoke(tc); 4643804Ssaidi@eecs.umich.edu thread->decoder.reset(); 4653804Ssaidi@eecs.umich.edu } 4663833Ssaidi@eecs.umich.edu } 4673804Ssaidi@eecs.umich.edu} 4683804Ssaidi@eecs.umich.edu 4693833Ssaidi@eecs.umich.edu 4703836Ssaidi@eecs.umich.eduvoid 4713836Ssaidi@eecs.umich.eduBaseSimpleCPU::setupFetchRequest(const RequestPtr &req) 4726022Sgblack@eecs.umich.edu{ 4733836Ssaidi@eecs.umich.edu SimpleExecContext &t_info = *threadInfo[curThread]; 4743804Ssaidi@eecs.umich.edu SimpleThread* thread = t_info.thread; 4753804Ssaidi@eecs.umich.edu 4763804Ssaidi@eecs.umich.edu Addr instAddr = thread->instAddr(); 4773836Ssaidi@eecs.umich.edu Addr fetchPC = (instAddr & PCMask) + t_info.fetchOffset; 4783836Ssaidi@eecs.umich.edu 4794990Sgblack@eecs.umich.edu // set up memory request for instruction fetch 4803804Ssaidi@eecs.umich.edu DPRINTF(Fetch, "Fetch: Inst PC:%08p, Fetch PC:%08p\n", instAddr, fetchPC); 4813804Ssaidi@eecs.umich.edu 4823804Ssaidi@eecs.umich.edu req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, 4833804Ssaidi@eecs.umich.edu instMasterId(), instAddr); 4843804Ssaidi@eecs.umich.edu} 4853804Ssaidi@eecs.umich.edu 4863804Ssaidi@eecs.umich.edu 4874990Sgblack@eecs.umich.eduvoid 4883804Ssaidi@eecs.umich.eduBaseSimpleCPU::preExecute() 4893804Ssaidi@eecs.umich.edu{ 4903804Ssaidi@eecs.umich.edu SimpleExecContext &t_info = *threadInfo[curThread]; 4913833Ssaidi@eecs.umich.edu SimpleThread* thread = t_info.thread; 4923836Ssaidi@eecs.umich.edu 4933804Ssaidi@eecs.umich.edu // maintain $r0 semantics 4943804Ssaidi@eecs.umich.edu thread->setIntReg(ZeroReg, 0); 4953804Ssaidi@eecs.umich.edu#if THE_ISA == ALPHA_ISA 4963804Ssaidi@eecs.umich.edu thread->setFloatReg(ZeroReg, 0); 4973804Ssaidi@eecs.umich.edu#endif // ALPHA_ISA 4983804Ssaidi@eecs.umich.edu 4993804Ssaidi@eecs.umich.edu // check for instruction-count-based events 5004990Sgblack@eecs.umich.edu comInstEventQueue[curThread]->serviceEvents(t_info.numInst); 5018751Sgblack@eecs.umich.edu system->instEventQueue.serviceEvents(system->totalNumInsts); 5023804Ssaidi@eecs.umich.edu 5038751Sgblack@eecs.umich.edu // decode the instruction 5048751Sgblack@eecs.umich.edu inst = gtoh(inst); 5058751Sgblack@eecs.umich.edu 5068751Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5078751Sgblack@eecs.umich.edu 5088751Sgblack@eecs.umich.edu if (isRomMicroPC(pcState.microPC())) { 5093804Ssaidi@eecs.umich.edu t_info.stayAtPC = false; 5103804Ssaidi@eecs.umich.edu curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(), 5113804Ssaidi@eecs.umich.edu curMacroStaticInst); 5123804Ssaidi@eecs.umich.edu } else if (!curMacroStaticInst) { 5134990Sgblack@eecs.umich.edu //We're not in the middle of a macro instruction 5144990Sgblack@eecs.umich.edu StaticInstPtr instPtr = NULL; 5153804Ssaidi@eecs.umich.edu 5163804Ssaidi@eecs.umich.edu TheISA::Decoder *decoder = &(thread->decoder); 5173804Ssaidi@eecs.umich.edu 5183836Ssaidi@eecs.umich.edu //Predecode, ie bundle up an ExtMachInst 5193836Ssaidi@eecs.umich.edu //If more fetch data is needed, pass it in. 5203836Ssaidi@eecs.umich.edu Addr fetchPC = (pcState.instAddr() & PCMask) + t_info.fetchOffset; 5216022Sgblack@eecs.umich.edu //if (decoder->needMoreBytes()) 5223836Ssaidi@eecs.umich.edu decoder->moreBytes(pcState, fetchPC, inst); 5235555Snate@binkert.org //else 5243836Ssaidi@eecs.umich.edu // decoder->process(); 5253804Ssaidi@eecs.umich.edu 5263804Ssaidi@eecs.umich.edu //Decode an instruction if one is ready. Otherwise, we'll have to 5273804Ssaidi@eecs.umich.edu //fetch beyond the MachInst at the current pc. 5283804Ssaidi@eecs.umich.edu instPtr = decoder->decode(pcState); 5296022Sgblack@eecs.umich.edu if (instPtr) { 5303804Ssaidi@eecs.umich.edu t_info.stayAtPC = false; 5315555Snate@binkert.org thread->pcState(pcState); 5325555Snate@binkert.org } else { 5335555Snate@binkert.org t_info.stayAtPC = true; 5345555Snate@binkert.org t_info.fetchOffset += sizeof(MachInst); 5354172Ssaidi@eecs.umich.edu } 5363836Ssaidi@eecs.umich.edu 5373836Ssaidi@eecs.umich.edu //If we decoded an instruction and it's microcoded, start pulling 5383836Ssaidi@eecs.umich.edu //out micro ops 5399912Sandreas@sandberg.pp.se if (instPtr && instPtr->isMacroop()) { 5403836Ssaidi@eecs.umich.edu curMacroStaticInst = instPtr; 5413836Ssaidi@eecs.umich.edu curStaticInst = 5425570Snate@binkert.org curMacroStaticInst->fetchMicroop(pcState.microPC()); 5433833Ssaidi@eecs.umich.edu } else { 5443836Ssaidi@eecs.umich.edu curStaticInst = instPtr; 5453836Ssaidi@eecs.umich.edu } 5463836Ssaidi@eecs.umich.edu } else { 5473929Ssaidi@eecs.umich.edu //Read the next micro op from the macro op 5483929Ssaidi@eecs.umich.edu curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 5493929Ssaidi@eecs.umich.edu } 5503836Ssaidi@eecs.umich.edu 5513836Ssaidi@eecs.umich.edu //If we decoded an instruction this "tick", record information about it. 5523836Ssaidi@eecs.umich.edu if (curStaticInst) { 5534996Sgblack@eecs.umich.edu#if TRACING_ON 5544996Sgblack@eecs.umich.edu traceData = tracer->getInstRecord(curTick(), thread->getTC(), 5554996Sgblack@eecs.umich.edu curStaticInst, thread->pcState(), curMacroStaticInst); 5564996Sgblack@eecs.umich.edu 5574996Sgblack@eecs.umich.edu DPRINTF(Decode,"Decode: Decoded %s instruction: %#x\n", 5584996Sgblack@eecs.umich.edu curStaticInst->getName(), curStaticInst->machInst); 5594996Sgblack@eecs.umich.edu#endif // TRACING_ON 5604996Sgblack@eecs.umich.edu } 5614996Sgblack@eecs.umich.edu 5624996Sgblack@eecs.umich.edu if (branchPred && curStaticInst && 5634996Sgblack@eecs.umich.edu curStaticInst->isControl()) { 5644996Sgblack@eecs.umich.edu // Use a fake sequence number since we only have one 5654996Sgblack@eecs.umich.edu // instruction in flight at the same time. 5664996Sgblack@eecs.umich.edu const InstSeqNum cur_sn(0); 5674996Sgblack@eecs.umich.edu t_info.predPC = thread->pcState(); 5684996Sgblack@eecs.umich.edu const bool predict_taken( 5694996Sgblack@eecs.umich.edu branchPred->predict(curStaticInst, cur_sn, t_info.predPC, 5704996Sgblack@eecs.umich.edu curThread)); 5714996Sgblack@eecs.umich.edu 5725555Snate@binkert.org if (predict_taken) 5735555Snate@binkert.org ++t_info.numPredictedBranches; 5745736Snate@binkert.org } 5755555Snate@binkert.org} 5765555Snate@binkert.org 5774996Sgblack@eecs.umich.eduvoid 5784996Sgblack@eecs.umich.eduBaseSimpleCPU::postExecute() 5794996Sgblack@eecs.umich.edu{ 5804996Sgblack@eecs.umich.edu SimpleExecContext &t_info = *threadInfo[curThread]; 5814996Sgblack@eecs.umich.edu SimpleThread* thread = t_info.thread; 5824996Sgblack@eecs.umich.edu 5834996Sgblack@eecs.umich.edu assert(curStaticInst); 5844996Sgblack@eecs.umich.edu 5855555Snate@binkert.org TheISA::PCState pc = threadContexts[curThread]->pcState(); 5865555Snate@binkert.org Addr instAddr = pc.instAddr(); 5875736Snate@binkert.org if (FullSystem && thread->profile) { 5885555Snate@binkert.org bool usermode = TheISA::inUserMode(threadContexts[curThread]); 5895555Snate@binkert.org thread->profilePC = usermode ? 1 : instAddr; 5904996Sgblack@eecs.umich.edu ProfileNode *node = thread->profile->consume(threadContexts[curThread], 5914996Sgblack@eecs.umich.edu curStaticInst); 5924996Sgblack@eecs.umich.edu if (node) 5933836Ssaidi@eecs.umich.edu thread->profileNode = node; 5943836Ssaidi@eecs.umich.edu } 5953833Ssaidi@eecs.umich.edu 5963833Ssaidi@eecs.umich.edu if (curStaticInst->isMemRef()) { 5973833Ssaidi@eecs.umich.edu t_info.numMemRefs++; 5983833Ssaidi@eecs.umich.edu } 5993833Ssaidi@eecs.umich.edu 6003833Ssaidi@eecs.umich.edu if (curStaticInst->isLoad()) { 6013833Ssaidi@eecs.umich.edu ++t_info.numLoad; 6023833Ssaidi@eecs.umich.edu comLoadEventQueue[curThread]->serviceEvents(t_info.numLoad); 6033916Ssaidi@eecs.umich.edu } 6043833Ssaidi@eecs.umich.edu 6053804Ssaidi@eecs.umich.edu if (CPA::available()) { 6063832Ssaidi@eecs.umich.edu CPA::cpa()->swAutoBegin(threadContexts[curThread], pc.nextInstAddr()); 6073832Ssaidi@eecs.umich.edu } 6083804Ssaidi@eecs.umich.edu 6093804Ssaidi@eecs.umich.edu if (curStaticInst->isControl()) { 6103804Ssaidi@eecs.umich.edu ++t_info.numBranches; 6113833Ssaidi@eecs.umich.edu } 6125555Snate@binkert.org 6133804Ssaidi@eecs.umich.edu /* Power model statistics */ 6143804Ssaidi@eecs.umich.edu //integer alu accesses 6153804Ssaidi@eecs.umich.edu if (curStaticInst->isInteger()){ 6163804Ssaidi@eecs.umich.edu t_info.numIntAluAccesses++; 6173804Ssaidi@eecs.umich.edu t_info.numIntInsts++; 6183804Ssaidi@eecs.umich.edu } 6193804Ssaidi@eecs.umich.edu 6203804Ssaidi@eecs.umich.edu //float alu accesses 6213804Ssaidi@eecs.umich.edu if (curStaticInst->isFloating()){ 6223833Ssaidi@eecs.umich.edu t_info.numFpAluAccesses++; 6233804Ssaidi@eecs.umich.edu t_info.numFpInsts++; 6243910Ssaidi@eecs.umich.edu } 6253804Ssaidi@eecs.umich.edu 6267741Sgblack@eecs.umich.edu //vector alu accesses 6273804Ssaidi@eecs.umich.edu if (curStaticInst->isVector()){ 6284990Sgblack@eecs.umich.edu t_info.numVecAluAccesses++; 6293804Ssaidi@eecs.umich.edu t_info.numVecInsts++; 6303804Ssaidi@eecs.umich.edu } 6313910Ssaidi@eecs.umich.edu 6327741Sgblack@eecs.umich.edu //number of function calls/returns to get window accesses 6334990Sgblack@eecs.umich.edu if (curStaticInst->isCall() || curStaticInst->isReturn()){ 6343804Ssaidi@eecs.umich.edu t_info.numCallsReturns++; 6353804Ssaidi@eecs.umich.edu } 6363804Ssaidi@eecs.umich.edu 6377741Sgblack@eecs.umich.edu //the number of branch predictions that will be made 6383910Ssaidi@eecs.umich.edu if (curStaticInst->isCondCtrl()){ 6393910Ssaidi@eecs.umich.edu t_info.numCondCtrlInsts++; 6407741Sgblack@eecs.umich.edu } 6413910Ssaidi@eecs.umich.edu 6423910Ssaidi@eecs.umich.edu //result bus acceses 6437741Sgblack@eecs.umich.edu if (curStaticInst->isLoad()){ 6443910Ssaidi@eecs.umich.edu t_info.numLoadInsts++; 6453910Ssaidi@eecs.umich.edu } 6463910Ssaidi@eecs.umich.edu 6473910Ssaidi@eecs.umich.edu if (curStaticInst->isStore() || curStaticInst->isAtomic()){ 6483910Ssaidi@eecs.umich.edu t_info.numStoreInsts++; 6493910Ssaidi@eecs.umich.edu } 6503902Ssaidi@eecs.umich.edu /* End power model statistics */ 6513804Ssaidi@eecs.umich.edu 6523926Ssaidi@eecs.umich.edu t_info.statExecutedInstType[curStaticInst->opClass()]++; 6537741Sgblack@eecs.umich.edu 6543804Ssaidi@eecs.umich.edu if (FullSystem) 6554989Sgblack@eecs.umich.edu traceFunctions(instAddr); 6564989Sgblack@eecs.umich.edu 6577741Sgblack@eecs.umich.edu if (traceData) { 6587741Sgblack@eecs.umich.edu traceData->dump(); 6597741Sgblack@eecs.umich.edu delete traceData; 6604989Sgblack@eecs.umich.edu traceData = NULL; 6613856Ssaidi@eecs.umich.edu } 6627741Sgblack@eecs.umich.edu 6633804Ssaidi@eecs.umich.edu // Call CPU instruction commit probes 6644103Ssaidi@eecs.umich.edu probeInstCommit(curStaticInst, instAddr); 6657741Sgblack@eecs.umich.edu} 6664191Ssaidi@eecs.umich.edu 6674191Ssaidi@eecs.umich.eduvoid 6687741Sgblack@eecs.umich.eduBaseSimpleCPU::advancePC(const Fault &fault) 6694103Ssaidi@eecs.umich.edu{ 6707741Sgblack@eecs.umich.edu SimpleExecContext &t_info = *threadInfo[curThread]; 6713804Ssaidi@eecs.umich.edu SimpleThread* thread = t_info.thread; 6727741Sgblack@eecs.umich.edu 6733804Ssaidi@eecs.umich.edu const bool branching(thread->pcState().branching()); 6747741Sgblack@eecs.umich.edu 6753824Ssaidi@eecs.umich.edu //Since we're moving to a new pc, zero out the offset 6767741Sgblack@eecs.umich.edu t_info.fetchOffset = 0; 6773825Ssaidi@eecs.umich.edu if (fault != NoFault) { 6783823Ssaidi@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 6797741Sgblack@eecs.umich.edu fault->invoke(threadContexts[curThread], curStaticInst); 6807741Sgblack@eecs.umich.edu thread->decoder.reset(); 6813823Ssaidi@eecs.umich.edu } else { 6823804Ssaidi@eecs.umich.edu if (curStaticInst) { 6833804Ssaidi@eecs.umich.edu if (curStaticInst->isLastMicroop()) 6843826Ssaidi@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 6854996Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 6864990Sgblack@eecs.umich.edu TheISA::advancePC(pcState, curStaticInst); 6873826Ssaidi@eecs.umich.edu thread->pcState(pcState); 6883826Ssaidi@eecs.umich.edu } 6893826Ssaidi@eecs.umich.edu } 6903826Ssaidi@eecs.umich.edu 6913826Ssaidi@eecs.umich.edu if (branchPred && curStaticInst && curStaticInst->isControl()) { 6923826Ssaidi@eecs.umich.edu // Use a fake sequence number since we only have one 6933826Ssaidi@eecs.umich.edu // instruction in flight at the same time. 6944990Sgblack@eecs.umich.edu const InstSeqNum cur_sn(0); 6953826Ssaidi@eecs.umich.edu 6963826Ssaidi@eecs.umich.edu if (t_info.predPC == thread->pcState()) { 6973826Ssaidi@eecs.umich.edu // Correctly predicted branch 6987741Sgblack@eecs.umich.edu branchPred->update(cur_sn, curThread); 6993804Ssaidi@eecs.umich.edu } else { 7003804Ssaidi@eecs.umich.edu // Mis-predicted branch 7015555Snate@binkert.org branchPred->squash(cur_sn, thread->pcState(), branching, curThread); 7023804Ssaidi@eecs.umich.edu ++t_info.numBranchMispred; 7037741Sgblack@eecs.umich.edu } 7043836Ssaidi@eecs.umich.edu } 7053804Ssaidi@eecs.umich.edu} 7063804Ssaidi@eecs.umich.edu 7073804Ssaidi@eecs.umich.eduvoid 7083836Ssaidi@eecs.umich.eduBaseSimpleCPU::startup() 7093804Ssaidi@eecs.umich.edu{ 7103804Ssaidi@eecs.umich.edu BaseCPU::startup(); 7114990Sgblack@eecs.umich.edu for (auto& t_info : threadInfo) 7123811Ssaidi@eecs.umich.edu t_info->thread->startup(); 7138751Sgblack@eecs.umich.edu} 7143804Ssaidi@eecs.umich.edu