base.cc revision 1121 
1/*
2 * Copyright (c) 2002-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <cmath>
30#include <cstdio>
31#include <cstdlib>
32#include <iostream>
33#include <iomanip>
34#include <list>
35#include <sstream>
36#include <string>
37
38#include "base/cprintf.hh"
39#include "base/inifile.hh"
40#include "base/loader/symtab.hh"
41#include "base/misc.hh"
42#include "base/pollevent.hh"
43#include "base/range.hh"
44#include "base/trace.hh"
45#include "base/stats/events.hh"
46#include "cpu/base_cpu.hh"
47#include "cpu/exec_context.hh"
48#include "cpu/exetrace.hh"
49#include "cpu/full_cpu/smt.hh"
50#include "cpu/simple_cpu/simple_cpu.hh"
51#include "cpu/static_inst.hh"
52#include "mem/base_mem.hh"
53#include "mem/mem_interface.hh"
54#include "sim/builder.hh"
55#include "sim/debug.hh"
56#include "sim/host.hh"
57#include "sim/sim_events.hh"
58#include "sim/sim_object.hh"
59#include "sim/stats.hh"
60
61#ifdef FULL_SYSTEM
62#include "base/remote_gdb.hh"
63#include "dev/alpha_access.h"
64#include "dev/pciareg.h"
65#include "mem/functional_mem/memory_control.hh"
66#include "mem/functional_mem/physical_memory.hh"
67#include "sim/system.hh"
68#include "targetarch/alpha_memory.hh"
69#include "targetarch/vtophys.hh"
70#else // !FULL_SYSTEM
71#include "eio/eio.hh"
72#include "mem/functional_mem/functional_memory.hh"
73#endif // FULL_SYSTEM
74
75using namespace std;
76
77SimpleCPU::TickEvent::TickEvent(SimpleCPU *c)
78    : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), multiplier(1)
79{
80}
81
82void
83SimpleCPU::TickEvent::process()
84{
85    int count = multiplier;
86    do {
87        cpu->tick();
88    } while (--count > 0 && cpu->status() == Running);
89}
90
91const char *
92SimpleCPU::TickEvent::description()
93{
94    return "SimpleCPU tick event";
95}
96
97
98SimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu)
99    : Event(&mainEventQueue),
100      cpu(_cpu)
101{
102}
103
104void SimpleCPU::CacheCompletionEvent::process()
105{
106    cpu->processCacheCompletion();
107}
108
109const char *
110SimpleCPU::CacheCompletionEvent::description()
111{
112    return "SimpleCPU cache completion event";
113}
114
115#ifdef FULL_SYSTEM
116SimpleCPU::SimpleCPU(const string &_name,
117                     System *_system,
118                     Counter max_insts_any_thread,
119                     Counter max_insts_all_threads,
120                     Counter max_loads_any_thread,
121                     Counter max_loads_all_threads,
122                     AlphaITB *itb, AlphaDTB *dtb,
123                     FunctionalMemory *mem,
124                     MemInterface *icache_interface,
125                     MemInterface *dcache_interface,
126                     bool _def_reg, Tick freq)
127    : BaseCPU(_name, /* number_of_threads */ 1,
128              max_insts_any_thread, max_insts_all_threads,
129              max_loads_any_thread, max_loads_all_threads,
130              _system, freq),
131#else
132SimpleCPU::SimpleCPU(const string &_name, Process *_process,
133                     Counter max_insts_any_thread,
134                     Counter max_insts_all_threads,
135                     Counter max_loads_any_thread,
136                     Counter max_loads_all_threads,
137                     MemInterface *icache_interface,
138                     MemInterface *dcache_interface,
139                     bool _def_reg)
140    : BaseCPU(_name, /* number_of_threads */ 1,
141              max_insts_any_thread, max_insts_all_threads,
142              max_loads_any_thread, max_loads_all_threads),
143#endif
144      tickEvent(this), xc(NULL), defer_registration(_def_reg),
145      cacheCompletionEvent(this)
146{
147    _status = Idle;
148#ifdef FULL_SYSTEM
149    xc = new ExecContext(this, 0, system, itb, dtb, mem);
150
151    // initialize CPU, including PC
152    TheISA::initCPU(&xc->regs);
153#else
154    xc = new ExecContext(this, /* thread_num */ 0, _process, /* asid */ 0);
155#endif // !FULL_SYSTEM
156
157    icacheInterface = icache_interface;
158    dcacheInterface = dcache_interface;
159
160    memReq = new MemReq();
161    memReq->xc = xc;
162    memReq->asid = 0;
163    memReq->data = new uint8_t[64];
164
165    numInst = 0;
166    startNumInst = 0;
167    numLoad = 0;
168    startNumLoad = 0;
169    lastIcacheStall = 0;
170    lastDcacheStall = 0;
171
172    execContexts.push_back(xc);
173}
174
175SimpleCPU::~SimpleCPU()
176{
177}
178
179void SimpleCPU::init()
180{
181    if (!defer_registration) {
182        this->registerExecContexts();
183    }
184}
185
186void
187SimpleCPU::switchOut()
188{
189    _status = SwitchedOut;
190    if (tickEvent.scheduled())
191        tickEvent.squash();
192}
193
194
195void
196SimpleCPU::takeOverFrom(BaseCPU *oldCPU)
197{
198    BaseCPU::takeOverFrom(oldCPU);
199
200    assert(!tickEvent.scheduled());
201
202    // if any of this CPU's ExecContexts are active, mark the CPU as
203    // running and schedule its tick event.
204    for (int i = 0; i < execContexts.size(); ++i) {
205        ExecContext *xc = execContexts[i];
206        if (xc->status() == ExecContext::Active && _status != Running) {
207            _status = Running;
208            tickEvent.schedule(curTick);
209        }
210    }
211
212    oldCPU->switchOut();
213}
214
215
216void
217SimpleCPU::activateContext(int thread_num, int delay)
218{
219    assert(thread_num == 0);
220    assert(xc);
221
222    assert(_status == Idle);
223    notIdleFraction++;
224    scheduleTickEvent(delay);
225    _status = Running;
226}
227
228
229void
230SimpleCPU::suspendContext(int thread_num)
231{
232    assert(thread_num == 0);
233    assert(xc);
234
235    assert(_status == Running);
236    notIdleFraction--;
237    unscheduleTickEvent();
238    _status = Idle;
239}
240
241
242void
243SimpleCPU::deallocateContext(int thread_num)
244{
245    // for now, these are equivalent
246    suspendContext(thread_num);
247}
248
249
250void
251SimpleCPU::haltContext(int thread_num)
252{
253    // for now, these are equivalent
254    suspendContext(thread_num);
255}
256
257
258void
259SimpleCPU::regStats()
260{
261    using namespace Stats;
262
263    BaseCPU::regStats();
264
265    numInsts
266        .name(name() + ".num_insts")
267        .desc("Number of instructions executed")
268        ;
269
270    numMemRefs
271        .name(name() + ".num_refs")
272        .desc("Number of memory references")
273        ;
274
275    notIdleFraction
276        .name(name() + ".not_idle_fraction")
277        .desc("Percentage of non-idle cycles")
278        ;
279
280    idleFraction
281        .name(name() + ".idle_fraction")
282        .desc("Percentage of idle cycles")
283        ;
284
285    icacheStallCycles
286        .name(name() + ".icache_stall_cycles")
287        .desc("ICache total stall cycles")
288        .prereq(icacheStallCycles)
289        ;
290
291    dcacheStallCycles
292        .name(name() + ".dcache_stall_cycles")
293        .desc("DCache total stall cycles")
294        .prereq(dcacheStallCycles)
295        ;
296
297    idleFraction = constant(1.0) - notIdleFraction;
298}
299
300void
301SimpleCPU::resetStats()
302{
303    startNumInst = numInst;
304    notIdleFraction = (_status != Idle);
305}
306
307void
308SimpleCPU::serialize(ostream &os)
309{
310    BaseCPU::serialize(os);
311    SERIALIZE_ENUM(_status);
312    SERIALIZE_SCALAR(inst);
313    nameOut(os, csprintf("%s.xc", name()));
314    xc->serialize(os);
315    nameOut(os, csprintf("%s.tickEvent", name()));
316    tickEvent.serialize(os);
317    nameOut(os, csprintf("%s.cacheCompletionEvent", name()));
318    cacheCompletionEvent.serialize(os);
319}
320
321void
322SimpleCPU::unserialize(Checkpoint *cp, const string &section)
323{
324    BaseCPU::unserialize(cp, section);
325    UNSERIALIZE_ENUM(_status);
326    UNSERIALIZE_SCALAR(inst);
327    xc->unserialize(cp, csprintf("%s.xc", section));
328    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
329    cacheCompletionEvent
330        .unserialize(cp, csprintf("%s.cacheCompletionEvent", section));
331}
332
333void
334change_thread_state(int thread_number, int activate, int priority)
335{
336}
337
338Fault
339SimpleCPU::copySrcTranslate(Addr src)
340{
341    static bool no_warn = true;
342    int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
343    // Only support block sizes of 64 atm.
344    assert(blk_size == 64);
345    int offset = src & (blk_size - 1);
346
347    // Make sure block doesn't span page
348    if (no_warn &&
349        (src & TheISA::PageMask) != ((src + blk_size) & TheISA::PageMask) &&
350        (src >> 40) != 0xfffffc) {
351        warn("Copied block source spans pages %x.", src);
352        no_warn = false;
353    }
354
355    memReq->reset(src & ~(blk_size - 1), blk_size);
356
357    // translate to physical address
358    Fault fault = xc->translateDataReadReq(memReq);
359
360    assert(fault != Alignment_Fault);
361
362    if (fault == No_Fault) {
363        xc->copySrcAddr = src;
364        xc->copySrcPhysAddr = memReq->paddr + offset;
365    } else {
366        xc->copySrcAddr = 0;
367        xc->copySrcPhysAddr = 0;
368    }
369    return fault;
370}
371
372Fault
373SimpleCPU::copy(Addr dest)
374{
375    static bool no_warn = true;
376    int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
377    // Only support block sizes of 64 atm.
378    assert(blk_size == 64);
379    uint8_t data[blk_size];
380    //assert(xc->copySrcAddr);
381    int offset = dest & (blk_size - 1);
382
383    // Make sure block doesn't span page
384    if (no_warn &&
385        (dest & TheISA::PageMask) != ((dest + blk_size) & TheISA::PageMask) &&
386        (dest >> 40) != 0xfffffc) {
387        no_warn = false;
388        warn("Copied block destination spans pages %x. ", dest);
389    }
390
391    memReq->reset(dest & ~(blk_size -1), blk_size);
392    // translate to physical address
393    Fault fault = xc->translateDataWriteReq(memReq);
394
395    assert(fault != Alignment_Fault);
396
397    if (fault == No_Fault) {
398        Addr dest_addr = memReq->paddr + offset;
399        // Need to read straight from memory since we have more than 8 bytes.
400        memReq->paddr = xc->copySrcPhysAddr;
401        xc->mem->read(memReq, data);
402        memReq->paddr = dest_addr;
403        xc->mem->write(memReq, data);
404        if (dcacheInterface) {
405            memReq->cmd = Copy;
406            memReq->completionEvent = NULL;
407            memReq->paddr = xc->copySrcPhysAddr;
408            memReq->dest = dest_addr;
409            memReq->size = 64;
410            memReq->time = curTick;
411            dcacheInterface->access(memReq);
412        }
413    }
414    return fault;
415}
416
417// precise architected memory state accessor macros
418template <class T>
419Fault
420SimpleCPU::read(Addr addr, T &data, unsigned flags)
421{
422    memReq->reset(addr, sizeof(T), flags);
423
424    // translate to physical address
425    Fault fault = xc->translateDataReadReq(memReq);
426
427    // do functional access
428    if (fault == No_Fault)
429        fault = xc->read(memReq, data);
430
431    if (traceData) {
432        traceData->setAddr(addr);
433        if (fault == No_Fault)
434            traceData->setData(data);
435    }
436
437    // if we have a cache, do cache access too
438    if (fault == No_Fault && dcacheInterface) {
439        memReq->cmd = Read;
440        memReq->completionEvent = NULL;
441        memReq->time = curTick;
442        MemAccessResult result = dcacheInterface->access(memReq);
443
444        // Ugly hack to get an event scheduled *only* if the access is
445        // a miss.  We really should add first-class support for this
446        // at some point.
447        if (result != MA_HIT && dcacheInterface->doEvents()) {
448            memReq->completionEvent = &cacheCompletionEvent;
449            lastDcacheStall = curTick;
450            unscheduleTickEvent();
451            _status = DcacheMissStall;
452        }
453    }
454
455    if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
456        recordEvent("Uncached Read");
457
458    return fault;
459}
460
461#ifndef DOXYGEN_SHOULD_SKIP_THIS
462
463template
464Fault
465SimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
466
467template
468Fault
469SimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
470
471template
472Fault
473SimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
474
475template
476Fault
477SimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
478
479#endif //DOXYGEN_SHOULD_SKIP_THIS
480
481template<>
482Fault
483SimpleCPU::read(Addr addr, double &data, unsigned flags)
484{
485    return read(addr, *(uint64_t*)&data, flags);
486}
487
488template<>
489Fault
490SimpleCPU::read(Addr addr, float &data, unsigned flags)
491{
492    return read(addr, *(uint32_t*)&data, flags);
493}
494
495
496template<>
497Fault
498SimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
499{
500    return read(addr, (uint32_t&)data, flags);
501}
502
503
504template <class T>
505Fault
506SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
507{
508    if (traceData) {
509        traceData->setAddr(addr);
510        traceData->setData(data);
511    }
512
513    memReq->reset(addr, sizeof(T), flags);
514
515    // translate to physical address
516    Fault fault = xc->translateDataWriteReq(memReq);
517
518    // do functional access
519    if (fault == No_Fault)
520        fault = xc->write(memReq, data);
521
522    if (fault == No_Fault && dcacheInterface) {
523        memReq->cmd = Write;
524        memcpy(memReq->data,(uint8_t *)&data,memReq->size);
525        memReq->completionEvent = NULL;
526        memReq->time = curTick;
527        MemAccessResult result = dcacheInterface->access(memReq);
528
529        // Ugly hack to get an event scheduled *only* if the access is
530        // a miss.  We really should add first-class support for this
531        // at some point.
532        if (result != MA_HIT && dcacheInterface->doEvents()) {
533            memReq->completionEvent = &cacheCompletionEvent;
534            lastDcacheStall = curTick;
535            unscheduleTickEvent();
536            _status = DcacheMissStall;
537        }
538    }
539
540    if (res && (fault == No_Fault))
541        *res = memReq->result;
542
543    if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
544        recordEvent("Uncached Write");
545
546    return fault;
547}
548
549
550#ifndef DOXYGEN_SHOULD_SKIP_THIS
551template
552Fault
553SimpleCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res);
554
555template
556Fault
557SimpleCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res);
558
559template
560Fault
561SimpleCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res);
562
563template
564Fault
565SimpleCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res);
566
567#endif //DOXYGEN_SHOULD_SKIP_THIS
568
569template<>
570Fault
571SimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
572{
573    return write(*(uint64_t*)&data, addr, flags, res);
574}
575
576template<>
577Fault
578SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
579{
580    return write(*(uint32_t*)&data, addr, flags, res);
581}
582
583
584template<>
585Fault
586SimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
587{
588    return write((uint32_t)data, addr, flags, res);
589}
590
591
592#ifdef FULL_SYSTEM
593Addr
594SimpleCPU::dbg_vtophys(Addr addr)
595{
596    return vtophys(xc, addr);
597}
598#endif // FULL_SYSTEM
599
600Tick save_cycle = 0;
601
602
603void
604SimpleCPU::processCacheCompletion()
605{
606    switch (status()) {
607      case IcacheMissStall:
608        icacheStallCycles += curTick - lastIcacheStall;
609        _status = IcacheMissComplete;
610        scheduleTickEvent(1);
611        break;
612      case DcacheMissStall:
613        dcacheStallCycles += curTick - lastDcacheStall;
614        _status = Running;
615        scheduleTickEvent(1);
616        break;
617      case SwitchedOut:
618        // If this CPU has been switched out due to sampling/warm-up,
619        // ignore any further status changes (e.g., due to cache
620        // misses outstanding at the time of the switch).
621        return;
622      default:
623        panic("SimpleCPU::processCacheCompletion: bad state");
624        break;
625    }
626}
627
628#ifdef FULL_SYSTEM
629void
630SimpleCPU::post_interrupt(int int_num, int index)
631{
632    BaseCPU::post_interrupt(int_num, index);
633
634    if (xc->status() == ExecContext::Suspended) {
635                DPRINTF(IPI,"Suspended Processor awoke\n");
636        xc->activate();
637    }
638}
639#endif // FULL_SYSTEM
640
641/* start simulation, program loaded, processor precise state initialized */
642void
643SimpleCPU::tick()
644{
645    numCycles++;
646
647    traceData = NULL;
648
649    Fault fault = No_Fault;
650
651#ifdef FULL_SYSTEM
652    if (AlphaISA::check_interrupts &&
653        xc->cpu->check_interrupts() &&
654        !PC_PAL(xc->regs.pc) &&
655        status() != IcacheMissComplete) {
656        int ipl = 0;
657        int summary = 0;
658        AlphaISA::check_interrupts = 0;
659        IntReg *ipr = xc->regs.ipr;
660
661        if (xc->regs.ipr[TheISA::IPR_SIRR]) {
662            for (int i = TheISA::INTLEVEL_SOFTWARE_MIN;
663                 i < TheISA::INTLEVEL_SOFTWARE_MAX; i++) {
664                if (ipr[TheISA::IPR_SIRR] & (ULL(1) << i)) {
665                    // See table 4-19 of 21164 hardware reference
666                    ipl = (i - TheISA::INTLEVEL_SOFTWARE_MIN) + 1;
667                    summary |= (ULL(1) << i);
668                }
669            }
670        }
671
672        uint64_t interrupts = xc->cpu->intr_status();
673        for (int i = TheISA::INTLEVEL_EXTERNAL_MIN;
674            i < TheISA::INTLEVEL_EXTERNAL_MAX; i++) {
675            if (interrupts & (ULL(1) << i)) {
676                // See table 4-19 of 21164 hardware reference
677                ipl = i;
678                summary |= (ULL(1) << i);
679            }
680        }
681
682        if (ipr[TheISA::IPR_ASTRR])
683            panic("asynchronous traps not implemented\n");
684
685        if (ipl && ipl > xc->regs.ipr[TheISA::IPR_IPLR]) {
686            ipr[TheISA::IPR_ISR] = summary;
687            ipr[TheISA::IPR_INTID] = ipl;
688            xc->ev5_trap(Interrupt_Fault);
689
690            DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
691                    ipr[TheISA::IPR_IPLR], ipl, summary);
692        }
693    }
694#endif
695
696    // maintain $r0 semantics
697    xc->regs.intRegFile[ZeroReg] = 0;
698#ifdef TARGET_ALPHA
699    xc->regs.floatRegFile.d[ZeroReg] = 0.0;
700#endif // TARGET_ALPHA
701
702    if (status() == IcacheMissComplete) {
703        // We've already fetched an instruction and were stalled on an
704        // I-cache miss.  No need to fetch it again.
705
706        // Set status to running; tick event will get rescheduled if
707        // necessary at end of tick() function.
708        _status = Running;
709    }
710    else {
711        // Try to fetch an instruction
712
713        // set up memory request for instruction fetch
714#ifdef FULL_SYSTEM
715#define IFETCH_FLAGS(pc)	((pc) & 1) ? PHYSICAL : 0
716#else
717#define IFETCH_FLAGS(pc)	0
718#endif
719
720        memReq->cmd = Read;
721        memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t),
722                     IFETCH_FLAGS(xc->regs.pc));
723
724        fault = xc->translateInstReq(memReq);
725
726        if (fault == No_Fault)
727            fault = xc->mem->read(memReq, inst);
728
729        if (icacheInterface && fault == No_Fault) {
730            memReq->completionEvent = NULL;
731
732            memReq->time = curTick;
733            MemAccessResult result = icacheInterface->access(memReq);
734
735            // Ugly hack to get an event scheduled *only* if the access is
736            // a miss.  We really should add first-class support for this
737            // at some point.
738            if (result != MA_HIT && icacheInterface->doEvents()) {
739                memReq->completionEvent = &cacheCompletionEvent;
740                lastIcacheStall = curTick;
741                unscheduleTickEvent();
742                _status = IcacheMissStall;
743                return;
744            }
745        }
746    }
747
748    // If we've got a valid instruction (i.e., no fault on instruction
749    // fetch), then execute it.
750    if (fault == No_Fault) {
751
752        // keep an instruction count
753        numInst++;
754        numInsts++;
755
756        // check for instruction-count-based events
757        comInstEventQueue[0]->serviceEvents(numInst);
758
759        // decode the instruction
760    inst = htoa(inst);
761        StaticInstPtr<TheISA> si(inst);
762
763        traceData = Trace::getInstRecord(curTick, xc, this, si,
764                                         xc->regs.pc);
765
766#ifdef FULL_SYSTEM
767        xc->setInst(inst);
768#endif // FULL_SYSTEM
769
770        xc->func_exe_inst++;
771
772        fault = si->execute(this, traceData);
773
774#ifdef FULL_SYSTEM
775        if (xc->fnbin)
776            xc->execute(si.get());
777#endif
778
779        if (si->isMemRef()) {
780            numMemRefs++;
781        }
782
783        if (si->isLoad()) {
784            ++numLoad;
785            comLoadEventQueue[0]->serviceEvents(numLoad);
786        }
787
788        if (traceData)
789            traceData->finalize();
790
791    }	// if (fault == No_Fault)
792
793    if (fault != No_Fault) {
794#ifdef FULL_SYSTEM
795        xc->ev5_trap(fault);
796#else // !FULL_SYSTEM
797        fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc);
798#endif // FULL_SYSTEM
799    }
800    else {
801        // go to the next instruction
802        xc->regs.pc = xc->regs.npc;
803        xc->regs.npc += sizeof(MachInst);
804    }
805
806#ifdef FULL_SYSTEM
807    Addr oldpc;
808    do {
809        oldpc = xc->regs.pc;
810        system->pcEventQueue.service(xc);
811    } while (oldpc != xc->regs.pc);
812#endif
813
814    assert(status() == Running ||
815           status() == Idle ||
816           status() == DcacheMissStall);
817
818    if (status() == Running && !tickEvent.scheduled())
819        tickEvent.schedule(curTick + 1);
820}
821
822
823////////////////////////////////////////////////////////////////////////
824//
825//  SimpleCPU Simulation Object
826//
827BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
828
829    Param<Counter> max_insts_any_thread;
830    Param<Counter> max_insts_all_threads;
831    Param<Counter> max_loads_any_thread;
832    Param<Counter> max_loads_all_threads;
833
834#ifdef FULL_SYSTEM
835    SimObjectParam<AlphaITB *> itb;
836    SimObjectParam<AlphaDTB *> dtb;
837    SimObjectParam<FunctionalMemory *> mem;
838    SimObjectParam<System *> system;
839    Param<int> mult;
840#else
841    SimObjectParam<Process *> workload;
842#endif // FULL_SYSTEM
843
844    SimObjectParam<BaseMem *> icache;
845    SimObjectParam<BaseMem *> dcache;
846
847    Param<bool> defer_registration;
848    Param<int> multiplier;
849
850END_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
851
852BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
853
854    INIT_PARAM_DFLT(max_insts_any_thread,
855                    "terminate when any thread reaches this inst count",
856                    0),
857    INIT_PARAM_DFLT(max_insts_all_threads,
858                    "terminate when all threads have reached this inst count",
859                    0),
860    INIT_PARAM_DFLT(max_loads_any_thread,
861                    "terminate when any thread reaches this load count",
862                    0),
863    INIT_PARAM_DFLT(max_loads_all_threads,
864                    "terminate when all threads have reached this load count",
865                    0),
866
867#ifdef FULL_SYSTEM
868    INIT_PARAM(itb, "Instruction TLB"),
869    INIT_PARAM(dtb, "Data TLB"),
870    INIT_PARAM(mem, "memory"),
871    INIT_PARAM(system, "system object"),
872    INIT_PARAM_DFLT(mult, "system clock multiplier", 1),
873#else
874    INIT_PARAM(workload, "processes to run"),
875#endif // FULL_SYSTEM
876
877    INIT_PARAM_DFLT(icache, "L1 instruction cache object", NULL),
878    INIT_PARAM_DFLT(dcache, "L1 data cache object", NULL),
879    INIT_PARAM_DFLT(defer_registration, "defer registration with system "
880                    "(for sampling)", false),
881
882    INIT_PARAM_DFLT(multiplier, "clock multiplier", 1)
883
884END_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
885
886
887CREATE_SIM_OBJECT(SimpleCPU)
888{
889    SimpleCPU *cpu;
890#ifdef FULL_SYSTEM
891    if (mult != 1)
892        panic("processor clock multiplier must be 1\n");
893
894    cpu = new SimpleCPU(getInstanceName(), system,
895                        max_insts_any_thread, max_insts_all_threads,
896                        max_loads_any_thread, max_loads_all_threads,
897                        itb, dtb, mem,
898                        (icache) ? icache->getInterface() : NULL,
899                        (dcache) ? dcache->getInterface() : NULL,
900                        defer_registration,
901                        ticksPerSecond * mult);
902#else
903
904    cpu = new SimpleCPU(getInstanceName(), workload,
905                        max_insts_any_thread, max_insts_all_threads,
906                        max_loads_any_thread, max_loads_all_threads,
907                        (icache) ? icache->getInterface() : NULL,
908                        (dcache) ? dcache->getInterface() : NULL,
909                        defer_registration);
910
911#endif // FULL_SYSTEM
912
913    cpu->setTickMultiplier(multiplier);
914
915    return cpu;
916}
917
918REGISTER_SIM_OBJECT("SimpleCPU", SimpleCPU)
919
920