base.cc revision 10345
12SN/A/* 29448SAndreas.Sandberg@ARM.com * Copyright (c) 2010-2012 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47338SAli.Saidi@ARM.com * All rights reserved 57338SAli.Saidi@ARM.com * 67338SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 77338SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 87338SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 97338SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 107338SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 117338SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 127338SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 137338SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 147338SAli.Saidi@ARM.com * 151762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422SN/A */ 432SN/A 448779Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 458779Sgblack@eecs.umich.edu#include "arch/stacktrace.hh" 468779Sgblack@eecs.umich.edu#include "arch/tlb.hh" 472439SN/A#include "arch/utility.hh" 488779Sgblack@eecs.umich.edu#include "arch/vtophys.hh" 498229Snate@binkert.org#include "base/loader/symtab.hh" 506216Snate@binkert.org#include "base/cp_annotate.hh" 51146SN/A#include "base/cprintf.hh" 52146SN/A#include "base/inifile.hh" 53146SN/A#include "base/misc.hh" 54146SN/A#include "base/pollevent.hh" 55146SN/A#include "base/trace.hh" 566216Snate@binkert.org#include "base/types.hh" 576658Snate@binkert.org#include "config/the_isa.hh" 588229Snate@binkert.org#include "cpu/simple/base.hh" 591717SN/A#include "cpu/base.hh" 608887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 618887Sgeoffrey.blake@arm.com#include "cpu/checker/thread_context.hh" 62146SN/A#include "cpu/exetrace.hh" 6310061Sandreas@sandberg.pp.se#include "cpu/pred/bpred_unit.hh" 641977SN/A#include "cpu/profile.hh" 652683Sktlim@umich.edu#include "cpu/simple_thread.hh" 661717SN/A#include "cpu/smt.hh" 67146SN/A#include "cpu/static_inst.hh" 682683Sktlim@umich.edu#include "cpu/thread_context.hh" 698232Snate@binkert.org#include "debug/Decode.hh" 708232Snate@binkert.org#include "debug/Fetch.hh" 718232Snate@binkert.org#include "debug/Quiesce.hh" 728779Sgblack@eecs.umich.edu#include "mem/mem_object.hh" 733348Sbinkertn@umich.edu#include "mem/packet.hh" 746105Ssteve.reinhardt@amd.com#include "mem/request.hh" 756216Snate@binkert.org#include "params/BaseSimpleCPU.hh" 762036SN/A#include "sim/byteswap.hh" 77146SN/A#include "sim/debug.hh" 788817Sgblack@eecs.umich.edu#include "sim/faults.hh" 798793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 8056SN/A#include "sim/sim_events.hh" 8156SN/A#include "sim/sim_object.hh" 82695SN/A#include "sim/stats.hh" 832901Ssaidi@eecs.umich.edu#include "sim/system.hh" 842SN/A 852SN/Ausing namespace std; 862449SN/Ausing namespace TheISA; 871355SN/A 885529Snate@binkert.orgBaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p) 8910061Sandreas@sandberg.pp.se : BaseCPU(p), 9010061Sandreas@sandberg.pp.se branchPred(p->branchPred), 9110061Sandreas@sandberg.pp.se traceData(NULL), thread(NULL) 92224SN/A{ 938793Sgblack@eecs.umich.edu if (FullSystem) 949384SAndreas.Sandberg@arm.com thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb, 959384SAndreas.Sandberg@arm.com p->isa[0]); 968793Sgblack@eecs.umich.edu else 978820Sgblack@eecs.umich.edu thread = new SimpleThread(this, /* thread_num */ 0, p->system, 989384SAndreas.Sandberg@arm.com p->workload[0], p->itb, p->dtb, p->isa[0]); 992SN/A 1006029Ssteve.reinhardt@amd.com thread->setStatus(ThreadContext::Halted); 1012672Sktlim@umich.edu 1022683Sktlim@umich.edu tc = thread->getTC(); 1032SN/A 1048733Sgeoffrey.blake@arm.com if (p->checker) { 1058733Sgeoffrey.blake@arm.com BaseCPU *temp_checker = p->checker; 1068733Sgeoffrey.blake@arm.com checker = dynamic_cast<CheckerCPU *>(temp_checker); 1078733Sgeoffrey.blake@arm.com checker->setSystem(p->system); 1088733Sgeoffrey.blake@arm.com // Manipulate thread context 1098733Sgeoffrey.blake@arm.com ThreadContext *cpu_tc = tc; 1108733Sgeoffrey.blake@arm.com tc = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker); 1118733Sgeoffrey.blake@arm.com } else { 1128733Sgeoffrey.blake@arm.com checker = NULL; 1138733Sgeoffrey.blake@arm.com } 1148733Sgeoffrey.blake@arm.com 1152SN/A numInst = 0; 116334SN/A startNumInst = 0; 1178834Satgutier@umich.edu numOp = 0; 1188834Satgutier@umich.edu startNumOp = 0; 119140SN/A numLoad = 0; 120334SN/A startNumLoad = 0; 1212SN/A lastIcacheStall = 0; 1222SN/A lastDcacheStall = 0; 1232SN/A 1242680Sktlim@umich.edu threadContexts.push_back(tc); 1254377Sgblack@eecs.umich.edu 1265169Ssaidi@eecs.umich.edu 1274377Sgblack@eecs.umich.edu fetchOffset = 0; 1284377Sgblack@eecs.umich.edu stayAtPC = false; 1292SN/A} 1302SN/A 1312623SN/ABaseSimpleCPU::~BaseSimpleCPU() 1322SN/A{ 1332SN/A} 1342SN/A 135180SN/Avoid 1368737Skoansin.tan@gmail.comBaseSimpleCPU::deallocateContext(ThreadID thread_num) 137393SN/A{ 138393SN/A // for now, these are equivalent 139393SN/A suspendContext(thread_num); 140393SN/A} 141384SN/A 142384SN/A 143393SN/Avoid 1448737Skoansin.tan@gmail.comBaseSimpleCPU::haltContext(ThreadID thread_num) 145393SN/A{ 146393SN/A // for now, these are equivalent 147393SN/A suspendContext(thread_num); 148393SN/A} 149384SN/A 150189SN/A 151189SN/Avoid 1522623SN/ABaseSimpleCPU::regStats() 1532SN/A{ 154729SN/A using namespace Stats; 155334SN/A 1562SN/A BaseCPU::regStats(); 1572SN/A 1582SN/A numInsts 1598834Satgutier@umich.edu .name(name() + ".committedInsts") 1608834Satgutier@umich.edu .desc("Number of instructions committed") 1618834Satgutier@umich.edu ; 1628834Satgutier@umich.edu 1638834Satgutier@umich.edu numOps 1648834Satgutier@umich.edu .name(name() + ".committedOps") 1658834Satgutier@umich.edu .desc("Number of ops (including micro ops) committed") 1662SN/A ; 1672SN/A 1687897Shestness@cs.utexas.edu numIntAluAccesses 1697897Shestness@cs.utexas.edu .name(name() + ".num_int_alu_accesses") 1707897Shestness@cs.utexas.edu .desc("Number of integer alu accesses") 1717897Shestness@cs.utexas.edu ; 1727897Shestness@cs.utexas.edu 1737897Shestness@cs.utexas.edu numFpAluAccesses 1747897Shestness@cs.utexas.edu .name(name() + ".num_fp_alu_accesses") 1757897Shestness@cs.utexas.edu .desc("Number of float alu accesses") 1767897Shestness@cs.utexas.edu ; 1777897Shestness@cs.utexas.edu 1787897Shestness@cs.utexas.edu numCallsReturns 1797897Shestness@cs.utexas.edu .name(name() + ".num_func_calls") 1807897Shestness@cs.utexas.edu .desc("number of times a function call or return occured") 1817897Shestness@cs.utexas.edu ; 1827897Shestness@cs.utexas.edu 1837897Shestness@cs.utexas.edu numCondCtrlInsts 1847897Shestness@cs.utexas.edu .name(name() + ".num_conditional_control_insts") 1857897Shestness@cs.utexas.edu .desc("number of instructions that are conditional controls") 1867897Shestness@cs.utexas.edu ; 1877897Shestness@cs.utexas.edu 1887897Shestness@cs.utexas.edu numIntInsts 1897897Shestness@cs.utexas.edu .name(name() + ".num_int_insts") 1907897Shestness@cs.utexas.edu .desc("number of integer instructions") 1917897Shestness@cs.utexas.edu ; 1927897Shestness@cs.utexas.edu 1937897Shestness@cs.utexas.edu numFpInsts 1947897Shestness@cs.utexas.edu .name(name() + ".num_fp_insts") 1957897Shestness@cs.utexas.edu .desc("number of float instructions") 1967897Shestness@cs.utexas.edu ; 1977897Shestness@cs.utexas.edu 1987897Shestness@cs.utexas.edu numIntRegReads 1997897Shestness@cs.utexas.edu .name(name() + ".num_int_register_reads") 2007897Shestness@cs.utexas.edu .desc("number of times the integer registers were read") 2017897Shestness@cs.utexas.edu ; 2027897Shestness@cs.utexas.edu 2037897Shestness@cs.utexas.edu numIntRegWrites 2047897Shestness@cs.utexas.edu .name(name() + ".num_int_register_writes") 2057897Shestness@cs.utexas.edu .desc("number of times the integer registers were written") 2067897Shestness@cs.utexas.edu ; 2077897Shestness@cs.utexas.edu 2087897Shestness@cs.utexas.edu numFpRegReads 2097897Shestness@cs.utexas.edu .name(name() + ".num_fp_register_reads") 2107897Shestness@cs.utexas.edu .desc("number of times the floating registers were read") 2117897Shestness@cs.utexas.edu ; 2127897Shestness@cs.utexas.edu 2137897Shestness@cs.utexas.edu numFpRegWrites 2147897Shestness@cs.utexas.edu .name(name() + ".num_fp_register_writes") 2157897Shestness@cs.utexas.edu .desc("number of times the floating registers were written") 2167897Shestness@cs.utexas.edu ; 2177897Shestness@cs.utexas.edu 2189920Syasuko.eckert@amd.com numCCRegReads 2199920Syasuko.eckert@amd.com .name(name() + ".num_cc_register_reads") 2209920Syasuko.eckert@amd.com .desc("number of times the CC registers were read") 2219920Syasuko.eckert@amd.com .flags(nozero) 2229920Syasuko.eckert@amd.com ; 2239920Syasuko.eckert@amd.com 2249920Syasuko.eckert@amd.com numCCRegWrites 2259920Syasuko.eckert@amd.com .name(name() + ".num_cc_register_writes") 2269920Syasuko.eckert@amd.com .desc("number of times the CC registers were written") 2279920Syasuko.eckert@amd.com .flags(nozero) 2289920Syasuko.eckert@amd.com ; 2299920Syasuko.eckert@amd.com 2302SN/A numMemRefs 2317897Shestness@cs.utexas.edu .name(name()+".num_mem_refs") 2327897Shestness@cs.utexas.edu .desc("number of memory refs") 2337897Shestness@cs.utexas.edu ; 2347897Shestness@cs.utexas.edu 2357897Shestness@cs.utexas.edu numStoreInsts 2367897Shestness@cs.utexas.edu .name(name() + ".num_store_insts") 2377897Shestness@cs.utexas.edu .desc("Number of store instructions") 2387897Shestness@cs.utexas.edu ; 2397897Shestness@cs.utexas.edu 2407897Shestness@cs.utexas.edu numLoadInsts 2417897Shestness@cs.utexas.edu .name(name() + ".num_load_insts") 2427897Shestness@cs.utexas.edu .desc("Number of load instructions") 2432SN/A ; 2442SN/A 2451001SN/A notIdleFraction 2461001SN/A .name(name() + ".not_idle_fraction") 2471001SN/A .desc("Percentage of non-idle cycles") 2481001SN/A ; 2491001SN/A 2502SN/A idleFraction 2512SN/A .name(name() + ".idle_fraction") 2522SN/A .desc("Percentage of idle cycles") 2532SN/A ; 2542SN/A 2557897Shestness@cs.utexas.edu numBusyCycles 2567897Shestness@cs.utexas.edu .name(name() + ".num_busy_cycles") 2577897Shestness@cs.utexas.edu .desc("Number of busy cycles") 2587897Shestness@cs.utexas.edu ; 2597897Shestness@cs.utexas.edu 2607897Shestness@cs.utexas.edu numIdleCycles 2617897Shestness@cs.utexas.edu .name(name()+".num_idle_cycles") 2627897Shestness@cs.utexas.edu .desc("Number of idle cycles") 2637897Shestness@cs.utexas.edu ; 2647897Shestness@cs.utexas.edu 2652SN/A icacheStallCycles 2662SN/A .name(name() + ".icache_stall_cycles") 2672SN/A .desc("ICache total stall cycles") 2682SN/A .prereq(icacheStallCycles) 2692SN/A ; 2702SN/A 2712SN/A dcacheStallCycles 2722SN/A .name(name() + ".dcache_stall_cycles") 2732SN/A .desc("DCache total stall cycles") 2742SN/A .prereq(dcacheStallCycles) 2752SN/A ; 2762SN/A 2772390SN/A icacheRetryCycles 2782390SN/A .name(name() + ".icache_retry_cycles") 2792390SN/A .desc("ICache total retry cycles") 2802390SN/A .prereq(icacheRetryCycles) 2812390SN/A ; 2822390SN/A 2832390SN/A dcacheRetryCycles 2842390SN/A .name(name() + ".dcache_retry_cycles") 2852390SN/A .desc("DCache total retry cycles") 2862390SN/A .prereq(dcacheRetryCycles) 2872390SN/A ; 2882390SN/A 28910193SCurtis.Dunham@arm.com statExecutedInstType 29010193SCurtis.Dunham@arm.com .init(Enums::Num_OpClass) 29110193SCurtis.Dunham@arm.com .name(name() + ".op_class") 29210193SCurtis.Dunham@arm.com .desc("Class of executed instruction") 29310193SCurtis.Dunham@arm.com .flags(total | pdf | dist) 29410193SCurtis.Dunham@arm.com ; 29510193SCurtis.Dunham@arm.com for (unsigned i = 0; i < Num_OpClasses; ++i) { 29610193SCurtis.Dunham@arm.com statExecutedInstType.subname(i, Enums::OpClassStrings[i]); 29710193SCurtis.Dunham@arm.com } 29810193SCurtis.Dunham@arm.com 299385SN/A idleFraction = constant(1.0) - notIdleFraction; 3007897Shestness@cs.utexas.edu numIdleCycles = idleFraction * numCycles; 3017897Shestness@cs.utexas.edu numBusyCycles = (notIdleFraction)*numCycles; 30210061Sandreas@sandberg.pp.se 30310061Sandreas@sandberg.pp.se numBranches 30410061Sandreas@sandberg.pp.se .name(name() + ".Branches") 30510061Sandreas@sandberg.pp.se .desc("Number of branches fetched") 30610061Sandreas@sandberg.pp.se .prereq(numBranches); 30710061Sandreas@sandberg.pp.se 30810061Sandreas@sandberg.pp.se numPredictedBranches 30910061Sandreas@sandberg.pp.se .name(name() + ".predictedBranches") 31010061Sandreas@sandberg.pp.se .desc("Number of branches predicted as taken") 31110061Sandreas@sandberg.pp.se .prereq(numPredictedBranches); 31210061Sandreas@sandberg.pp.se 31310061Sandreas@sandberg.pp.se numBranchMispred 31410061Sandreas@sandberg.pp.se .name(name() + ".BranchMispred") 31510061Sandreas@sandberg.pp.se .desc("Number of branch mispredictions") 31610061Sandreas@sandberg.pp.se .prereq(numBranchMispred); 3172SN/A} 3182SN/A 3192SN/Avoid 3202623SN/ABaseSimpleCPU::resetStats() 321334SN/A{ 3222361SN/A// startNumInst = numInst; 3235496Ssaidi@eecs.umich.edu notIdleFraction = (_status != Idle); 324334SN/A} 325334SN/A 326334SN/Avoid 3279448SAndreas.Sandberg@ARM.comBaseSimpleCPU::serializeThread(ostream &os, ThreadID tid) 3282SN/A{ 3299448SAndreas.Sandberg@ARM.com assert(_status == Idle || _status == Running); 3309448SAndreas.Sandberg@ARM.com assert(tid == 0); 3319448SAndreas.Sandberg@ARM.com 3322683Sktlim@umich.edu thread->serialize(os); 3332SN/A} 3342SN/A 3352SN/Avoid 3369448SAndreas.Sandberg@ARM.comBaseSimpleCPU::unserializeThread(Checkpoint *cp, const string §ion, 3379448SAndreas.Sandberg@ARM.com ThreadID tid) 3382SN/A{ 3399448SAndreas.Sandberg@ARM.com if (tid != 0) 3409448SAndreas.Sandberg@ARM.com fatal("Trying to load more than one thread into a SimpleCPU\n"); 3419448SAndreas.Sandberg@ARM.com thread->unserialize(cp, section); 3422SN/A} 3432SN/A 3442SN/Avoid 3456221Snate@binkert.orgchange_thread_state(ThreadID tid, int activate, int priority) 3462SN/A{ 3472SN/A} 3482SN/A 3492SN/AAddr 3502623SN/ABaseSimpleCPU::dbg_vtophys(Addr addr) 3512SN/A{ 3522680Sktlim@umich.edu return vtophys(tc, addr); 3532SN/A} 3542SN/A 3552SN/Avoid 3565807Snate@binkert.orgBaseSimpleCPU::wakeup() 3572SN/A{ 3585807Snate@binkert.org if (thread->status() != ThreadContext::Suspended) 3595807Snate@binkert.org return; 3602SN/A 3615807Snate@binkert.org DPRINTF(Quiesce,"Suspended Processor awoke\n"); 3625807Snate@binkert.org thread->activate(); 3632SN/A} 3642SN/A 3652SN/Avoid 3662623SN/ABaseSimpleCPU::checkForInterrupts() 3672SN/A{ 3685704Snate@binkert.org if (checkInterrupts(tc)) { 3695647Sgblack@eecs.umich.edu Fault interrupt = interrupts->getInterrupt(tc); 3702SN/A 3713520Sgblack@eecs.umich.edu if (interrupt != NoFault) { 3727338SAli.Saidi@ARM.com fetchOffset = 0; 3735647Sgblack@eecs.umich.edu interrupts->updateIntrInfo(tc); 3743520Sgblack@eecs.umich.edu interrupt->invoke(tc); 3759023Sgblack@eecs.umich.edu thread->decoder.reset(); 3762SN/A } 3772SN/A } 3782623SN/A} 3792SN/A 3802623SN/A 3815894Sgblack@eecs.umich.eduvoid 3822662Sstever@eecs.umich.eduBaseSimpleCPU::setupFetchRequest(Request *req) 3832623SN/A{ 3847720Sgblack@eecs.umich.edu Addr instAddr = thread->instAddr(); 3854495Sacolyte@umich.edu 3862623SN/A // set up memory request for instruction fetch 3877720Sgblack@eecs.umich.edu DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr); 3882623SN/A 3897720Sgblack@eecs.umich.edu Addr fetchPC = (instAddr & PCMask) + fetchOffset; 3908832SAli.Saidi@ARM.com req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instMasterId(), 3918832SAli.Saidi@ARM.com instAddr); 3922623SN/A} 3932623SN/A 3942623SN/A 3952623SN/Avoid 3962623SN/ABaseSimpleCPU::preExecute() 3972623SN/A{ 3982SN/A // maintain $r0 semantics 3992683Sktlim@umich.edu thread->setIntReg(ZeroReg, 0); 4002427SN/A#if THE_ISA == ALPHA_ISA 4012683Sktlim@umich.edu thread->setFloatReg(ZeroReg, 0.0); 4022427SN/A#endif // ALPHA_ISA 4032SN/A 4042623SN/A // check for instruction-count-based events 4052623SN/A comInstEventQueue[0]->serviceEvents(numInst); 4067897Shestness@cs.utexas.edu system->instEventQueue.serviceEvents(system->totalNumInsts); 4072SN/A 4082623SN/A // decode the instruction 4092623SN/A inst = gtoh(inst); 4104377Sgblack@eecs.umich.edu 4117720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 4124377Sgblack@eecs.umich.edu 4137720Sgblack@eecs.umich.edu if (isRomMicroPC(pcState.microPC())) { 4145665Sgblack@eecs.umich.edu stayAtPC = false; 4157720Sgblack@eecs.umich.edu curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(), 4167720Sgblack@eecs.umich.edu curMacroStaticInst); 4175665Sgblack@eecs.umich.edu } else if (!curMacroStaticInst) { 4185665Sgblack@eecs.umich.edu //We're not in the middle of a macro instruction 4194181Sgblack@eecs.umich.edu StaticInstPtr instPtr = NULL; 4204181Sgblack@eecs.umich.edu 4219023Sgblack@eecs.umich.edu TheISA::Decoder *decoder = &(thread->decoder); 4229023Sgblack@eecs.umich.edu 4234181Sgblack@eecs.umich.edu //Predecode, ie bundle up an ExtMachInst 4244182Sgblack@eecs.umich.edu //If more fetch data is needed, pass it in. 4257720Sgblack@eecs.umich.edu Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset; 4269023Sgblack@eecs.umich.edu //if(decoder->needMoreBytes()) 4279023Sgblack@eecs.umich.edu decoder->moreBytes(pcState, fetchPC, inst); 4284593Sgblack@eecs.umich.edu //else 4299023Sgblack@eecs.umich.edu // decoder->process(); 4304377Sgblack@eecs.umich.edu 4319023Sgblack@eecs.umich.edu //Decode an instruction if one is ready. Otherwise, we'll have to 4324377Sgblack@eecs.umich.edu //fetch beyond the MachInst at the current pc. 4339023Sgblack@eecs.umich.edu instPtr = decoder->decode(pcState); 4349023Sgblack@eecs.umich.edu if (instPtr) { 4354377Sgblack@eecs.umich.edu stayAtPC = false; 4367720Sgblack@eecs.umich.edu thread->pcState(pcState); 4374377Sgblack@eecs.umich.edu } else { 4384377Sgblack@eecs.umich.edu stayAtPC = true; 4394377Sgblack@eecs.umich.edu fetchOffset += sizeof(MachInst); 4404377Sgblack@eecs.umich.edu } 4414181Sgblack@eecs.umich.edu 4424181Sgblack@eecs.umich.edu //If we decoded an instruction and it's microcoded, start pulling 4434181Sgblack@eecs.umich.edu //out micro ops 4444539Sgblack@eecs.umich.edu if (instPtr && instPtr->isMacroop()) { 4453276Sgblack@eecs.umich.edu curMacroStaticInst = instPtr; 4467720Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 4473280Sgblack@eecs.umich.edu } else { 4483280Sgblack@eecs.umich.edu curStaticInst = instPtr; 4493276Sgblack@eecs.umich.edu } 4503276Sgblack@eecs.umich.edu } else { 4513276Sgblack@eecs.umich.edu //Read the next micro op from the macro op 4527720Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 4533276Sgblack@eecs.umich.edu } 4543276Sgblack@eecs.umich.edu 4554181Sgblack@eecs.umich.edu //If we decoded an instruction this "tick", record information about it. 4568955Sgblack@eecs.umich.edu if (curStaticInst) { 4574522Ssaidi@eecs.umich.edu#if TRACING_ON 4587823Ssteve.reinhardt@amd.com traceData = tracer->getInstRecord(curTick(), tc, 4597720Sgblack@eecs.umich.edu curStaticInst, thread->pcState(), curMacroStaticInst); 4602470SN/A 4618955Sgblack@eecs.umich.edu DPRINTF(Decode,"Decode: Decoded %s instruction: %#x\n", 4624181Sgblack@eecs.umich.edu curStaticInst->getName(), curStaticInst->machInst); 4634522Ssaidi@eecs.umich.edu#endif // TRACING_ON 4644181Sgblack@eecs.umich.edu } 46510061Sandreas@sandberg.pp.se 46610061Sandreas@sandberg.pp.se if (branchPred && curStaticInst && curStaticInst->isControl()) { 46710061Sandreas@sandberg.pp.se // Use a fake sequence number since we only have one 46810061Sandreas@sandberg.pp.se // instruction in flight at the same time. 46910061Sandreas@sandberg.pp.se const InstSeqNum cur_sn(0); 47010061Sandreas@sandberg.pp.se const ThreadID tid(0); 47110061Sandreas@sandberg.pp.se pred_pc = thread->pcState(); 47210061Sandreas@sandberg.pp.se const bool predict_taken( 47310061Sandreas@sandberg.pp.se branchPred->predict(curStaticInst, cur_sn, pred_pc, tid)); 47410061Sandreas@sandberg.pp.se 47510061Sandreas@sandberg.pp.se if (predict_taken) 47610061Sandreas@sandberg.pp.se ++numPredictedBranches; 47710061Sandreas@sandberg.pp.se } 4782623SN/A} 4792623SN/A 4802623SN/Avoid 4812623SN/ABaseSimpleCPU::postExecute() 4822623SN/A{ 4837720Sgblack@eecs.umich.edu assert(curStaticInst); 4847720Sgblack@eecs.umich.edu 4857720Sgblack@eecs.umich.edu TheISA::PCState pc = tc->pcState(); 4867720Sgblack@eecs.umich.edu Addr instAddr = pc.instAddr(); 4878780Sgblack@eecs.umich.edu if (FullSystem && thread->profile) { 4883577Sgblack@eecs.umich.edu bool usermode = TheISA::inUserMode(tc); 4897720Sgblack@eecs.umich.edu thread->profilePC = usermode ? 1 : instAddr; 4905086Sgblack@eecs.umich.edu ProfileNode *node = thread->profile->consume(tc, curStaticInst); 4912623SN/A if (node) 4922683Sktlim@umich.edu thread->profileNode = node; 4932623SN/A } 4942SN/A 4952623SN/A if (curStaticInst->isMemRef()) { 4962623SN/A numMemRefs++; 4972SN/A } 4982SN/A 4992623SN/A if (curStaticInst->isLoad()) { 5002623SN/A ++numLoad; 5012623SN/A comLoadEventQueue[0]->serviceEvents(numLoad); 5022623SN/A } 5032SN/A 5045953Ssaidi@eecs.umich.edu if (CPA::available()) { 5057720Sgblack@eecs.umich.edu CPA::cpa()->swAutoBegin(tc, pc.nextInstAddr()); 5065953Ssaidi@eecs.umich.edu } 5075953Ssaidi@eecs.umich.edu 50810061Sandreas@sandberg.pp.se if (curStaticInst->isControl()) { 50910061Sandreas@sandberg.pp.se ++numBranches; 51010061Sandreas@sandberg.pp.se } 51110061Sandreas@sandberg.pp.se 5127897Shestness@cs.utexas.edu /* Power model statistics */ 5137897Shestness@cs.utexas.edu //integer alu accesses 5147897Shestness@cs.utexas.edu if (curStaticInst->isInteger()){ 5157897Shestness@cs.utexas.edu numIntAluAccesses++; 5167897Shestness@cs.utexas.edu numIntInsts++; 5177897Shestness@cs.utexas.edu } 5187897Shestness@cs.utexas.edu 5197897Shestness@cs.utexas.edu //float alu accesses 5207897Shestness@cs.utexas.edu if (curStaticInst->isFloating()){ 5217897Shestness@cs.utexas.edu numFpAluAccesses++; 5227897Shestness@cs.utexas.edu numFpInsts++; 5237897Shestness@cs.utexas.edu } 5247897Shestness@cs.utexas.edu 5257897Shestness@cs.utexas.edu //number of function calls/returns to get window accesses 5267897Shestness@cs.utexas.edu if (curStaticInst->isCall() || curStaticInst->isReturn()){ 5277897Shestness@cs.utexas.edu numCallsReturns++; 5287897Shestness@cs.utexas.edu } 5297897Shestness@cs.utexas.edu 5307897Shestness@cs.utexas.edu //the number of branch predictions that will be made 5317897Shestness@cs.utexas.edu if (curStaticInst->isCondCtrl()){ 5327897Shestness@cs.utexas.edu numCondCtrlInsts++; 5337897Shestness@cs.utexas.edu } 5347897Shestness@cs.utexas.edu 5357897Shestness@cs.utexas.edu //result bus acceses 5367897Shestness@cs.utexas.edu if (curStaticInst->isLoad()){ 5377897Shestness@cs.utexas.edu numLoadInsts++; 5387897Shestness@cs.utexas.edu } 5397897Shestness@cs.utexas.edu 5407897Shestness@cs.utexas.edu if (curStaticInst->isStore()){ 5417897Shestness@cs.utexas.edu numStoreInsts++; 5427897Shestness@cs.utexas.edu } 5437897Shestness@cs.utexas.edu /* End power model statistics */ 5447897Shestness@cs.utexas.edu 54510193SCurtis.Dunham@arm.com statExecutedInstType[curStaticInst->opClass()]++; 54610193SCurtis.Dunham@arm.com 5478780Sgblack@eecs.umich.edu if (FullSystem) 5488780Sgblack@eecs.umich.edu traceFunctions(instAddr); 5492644Sstever@eecs.umich.edu 5502644Sstever@eecs.umich.edu if (traceData) { 5514046Sbinkertn@umich.edu traceData->dump(); 5524046Sbinkertn@umich.edu delete traceData; 5534046Sbinkertn@umich.edu traceData = NULL; 5542644Sstever@eecs.umich.edu } 5552623SN/A} 5562SN/A 5572623SN/Avoid 5582623SN/ABaseSimpleCPU::advancePC(Fault fault) 5592623SN/A{ 56010061Sandreas@sandberg.pp.se const bool branching(thread->pcState().branching()); 56110061Sandreas@sandberg.pp.se 5624377Sgblack@eecs.umich.edu //Since we're moving to a new pc, zero out the offset 5634377Sgblack@eecs.umich.edu fetchOffset = 0; 5642090SN/A if (fault != NoFault) { 5653905Ssaidi@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 5667678Sgblack@eecs.umich.edu fault->invoke(tc, curStaticInst); 5679023Sgblack@eecs.umich.edu thread->decoder.reset(); 5684377Sgblack@eecs.umich.edu } else { 5697720Sgblack@eecs.umich.edu if (curStaticInst) { 5707720Sgblack@eecs.umich.edu if (curStaticInst->isLastMicroop()) 5717720Sgblack@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 5727720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5737720Sgblack@eecs.umich.edu TheISA::advancePC(pcState, curStaticInst); 5747720Sgblack@eecs.umich.edu thread->pcState(pcState); 5753276Sgblack@eecs.umich.edu } 5762SN/A } 57710061Sandreas@sandberg.pp.se 57810061Sandreas@sandberg.pp.se if (branchPred && curStaticInst && curStaticInst->isControl()) { 57910061Sandreas@sandberg.pp.se // Use a fake sequence number since we only have one 58010061Sandreas@sandberg.pp.se // instruction in flight at the same time. 58110061Sandreas@sandberg.pp.se const InstSeqNum cur_sn(0); 58210061Sandreas@sandberg.pp.se const ThreadID tid(0); 58310061Sandreas@sandberg.pp.se 58410061Sandreas@sandberg.pp.se if (pred_pc == thread->pcState()) { 58510061Sandreas@sandberg.pp.se // Correctly predicted branch 58610061Sandreas@sandberg.pp.se branchPred->update(cur_sn, tid); 58710061Sandreas@sandberg.pp.se } else { 58810061Sandreas@sandberg.pp.se // Mis-predicted branch 58910061Sandreas@sandberg.pp.se branchPred->squash(cur_sn, pcState(), 59010061Sandreas@sandberg.pp.se branching, tid); 59110061Sandreas@sandberg.pp.se ++numBranchMispred; 59210061Sandreas@sandberg.pp.se } 59310061Sandreas@sandberg.pp.se } 5942SN/A} 5952SN/A 5969461Snilay@cs.wisc.eduvoid 5979461Snilay@cs.wisc.eduBaseSimpleCPU::startup() 5989461Snilay@cs.wisc.edu{ 5999461Snilay@cs.wisc.edu BaseCPU::startup(); 6009461Snilay@cs.wisc.edu thread->startup(); 6019461Snilay@cs.wisc.edu} 602