atomic.hh revision 9443:0cb3209bc5c7
1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Steve Reinhardt 41 */ 42 43#ifndef __CPU_SIMPLE_ATOMIC_HH__ 44#define __CPU_SIMPLE_ATOMIC_HH__ 45 46#include "cpu/simple/base.hh" 47#include "params/AtomicSimpleCPU.hh" 48 49class AtomicSimpleCPU : public BaseSimpleCPU 50{ 51 public: 52 53 AtomicSimpleCPU(AtomicSimpleCPUParams *params); 54 virtual ~AtomicSimpleCPU(); 55 56 virtual void init(); 57 58 private: 59 60 struct TickEvent : public Event 61 { 62 AtomicSimpleCPU *cpu; 63 64 TickEvent(AtomicSimpleCPU *c); 65 void process(); 66 const char *description() const; 67 }; 68 69 TickEvent tickEvent; 70 71 const int width; 72 bool locked; 73 const bool simulate_data_stalls; 74 const bool simulate_inst_stalls; 75 76 /** 77 * Drain manager to use when signaling drain completion 78 * 79 * This pointer is non-NULL when draining and NULL otherwise. 80 */ 81 DrainManager *drain_manager; 82 83 // main simulation loop (one cycle) 84 void tick(); 85 86 /** 87 * Check if a system is in a drained state. 88 * 89 * We need to drain if: 90 * <ul> 91 * <li>We are in the middle of a microcode sequence as some CPUs 92 * (e.g., HW accelerated CPUs) can't be started in the middle 93 * of a gem5 microcode sequence. 94 * 95 * <li>The CPU is in a LLSC region. This shouldn't normally happen 96 * as these are executed atomically within a single tick() 97 * call. The only way this can happen at the moment is if 98 * there is an event in the PC event queue that affects the 99 * CPU state while it is in an LLSC region. 100 * 101 * <li>Stay at PC is true. 102 * </ul> 103 */ 104 bool isDrained() { 105 return microPC() == 0 && 106 !locked && 107 !stayAtPC; 108 } 109 110 /** 111 * Try to complete a drain request. 112 * 113 * @returns true if the CPU is drained, false otherwise. 114 */ 115 bool tryCompleteDrain(); 116 117 /** 118 * An AtomicCPUPort overrides the default behaviour of the 119 * recvAtomic and ignores the packet instead of panicking. 120 */ 121 class AtomicCPUPort : public CpuPort 122 { 123 124 public: 125 126 AtomicCPUPort(const std::string &_name, BaseCPU* _cpu) 127 : CpuPort(_name, _cpu) 128 { } 129 130 protected: 131 132 virtual Tick recvAtomicSnoop(PacketPtr pkt) 133 { 134 // Snooping a coherence request, just return 135 return 0; 136 } 137 138 }; 139 140 AtomicCPUPort icachePort; 141 AtomicCPUPort dcachePort; 142 143 bool fastmem; 144 Request ifetch_req; 145 Request data_read_req; 146 Request data_write_req; 147 148 bool dcache_access; 149 Tick dcache_latency; 150 151 protected: 152 153 /** Return a reference to the data port. */ 154 virtual CpuPort &getDataPort() { return dcachePort; } 155 156 /** Return a reference to the instruction port. */ 157 virtual CpuPort &getInstPort() { return icachePort; } 158 159 public: 160 161 unsigned int drain(DrainManager *drain_manager); 162 void drainResume(); 163 164 void switchOut(); 165 void takeOverFrom(BaseCPU *oldCPU); 166 167 virtual void activateContext(ThreadID thread_num, Cycles delay); 168 virtual void suspendContext(ThreadID thread_num); 169 170 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 171 172 Fault writeMem(uint8_t *data, unsigned size, 173 Addr addr, unsigned flags, uint64_t *res); 174 175 /** 176 * Print state of address in memory system via PrintReq (for 177 * debugging). 178 */ 179 void printAddr(Addr a); 180}; 181 182#endif // __CPU_SIMPLE_ATOMIC_HH__ 183