atomic.hh revision 8922:17f037ad8918 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_SIMPLE_ATOMIC_HH__
32#define __CPU_SIMPLE_ATOMIC_HH__
33
34#include "cpu/simple/base.hh"
35#include "params/AtomicSimpleCPU.hh"
36
37class AtomicSimpleCPU : public BaseSimpleCPU
38{
39  public:
40
41    AtomicSimpleCPU(AtomicSimpleCPUParams *params);
42    virtual ~AtomicSimpleCPU();
43
44    virtual void init();
45
46  private:
47
48    struct TickEvent : public Event
49    {
50        AtomicSimpleCPU *cpu;
51
52        TickEvent(AtomicSimpleCPU *c);
53        void process();
54        const char *description() const;
55    };
56
57    TickEvent tickEvent;
58
59    const int width;
60    bool locked;
61    const bool simulate_data_stalls;
62    const bool simulate_inst_stalls;
63
64    // main simulation loop (one cycle)
65    void tick();
66
67    /**
68     * An AtomicCPUPort overrides the default behaviour of the
69     * recvAtomic and ignores the packet instead of panicking.
70     */
71    class AtomicCPUPort : public CpuPort
72    {
73
74      public:
75
76        AtomicCPUPort(const std::string &_name, BaseCPU* _cpu)
77            : CpuPort(_name, _cpu)
78        { }
79
80      protected:
81
82        virtual Tick recvAtomic(PacketPtr pkt)
83        {
84            // Snooping a coherence request, just return
85            return 0;
86        }
87
88    };
89
90    AtomicCPUPort icachePort;
91    AtomicCPUPort dcachePort;
92
93    CpuPort physmemPort;
94    bool hasPhysMemPort;
95    Request ifetch_req;
96    Request data_read_req;
97    Request data_write_req;
98
99    bool dcache_access;
100    Tick dcache_latency;
101
102    Range<Addr> physMemAddr;
103
104  protected:
105
106    /** Return a reference to the data port. */
107    virtual CpuPort &getDataPort() { return dcachePort; }
108
109    /** Return a reference to the instruction port. */
110    virtual CpuPort &getInstPort() { return icachePort; }
111
112  public:
113
114    /**
115     * Override the getMasterPort of the BaseCPU so that we can
116     * provide the physmemPort, unique to the Atomic CPU.
117     */
118    virtual MasterPort &getMasterPort(const std::string &if_name,
119                                      int idx = -1);
120
121    virtual void serialize(std::ostream &os);
122    virtual void unserialize(Checkpoint *cp, const std::string &section);
123    virtual void resume();
124
125    void switchOut();
126    void takeOverFrom(BaseCPU *oldCPU);
127
128    virtual void activateContext(ThreadID thread_num, int delay);
129    virtual void suspendContext(ThreadID thread_num);
130
131    Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
132
133    Fault writeMem(uint8_t *data, unsigned size,
134                   Addr addr, unsigned flags, uint64_t *res);
135
136    /**
137     * Print state of address in memory system via PrintReq (for
138     * debugging).
139     */
140    void printAddr(Addr a);
141};
142
143#endif // __CPU_SIMPLE_ATOMIC_HH__
144