atomic.hh revision 5487:f0ac4112e128 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_SIMPLE_ATOMIC_HH__
32#define __CPU_SIMPLE_ATOMIC_HH__
33
34#include "cpu/simple/base.hh"
35
36class AtomicSimpleCPU : public BaseSimpleCPU
37{
38  public:
39
40    struct Params : public BaseSimpleCPU::Params {
41        int width;
42        bool simulate_data_stalls;
43        bool simulate_inst_stalls;
44    };
45
46    AtomicSimpleCPU(Params *params);
47    virtual ~AtomicSimpleCPU();
48
49    virtual void init();
50
51  public:
52    //
53    enum Status {
54        Running,
55        Idle,
56        SwitchedOut
57    };
58
59  protected:
60    Status _status;
61
62    Status status() const { return _status; }
63
64  private:
65
66    struct TickEvent : public Event
67    {
68        AtomicSimpleCPU *cpu;
69
70        TickEvent(AtomicSimpleCPU *c);
71        void process();
72        const char *description() const;
73    };
74
75    TickEvent tickEvent;
76
77    const int width;
78    const bool simulate_data_stalls;
79    const bool simulate_inst_stalls;
80
81    // main simulation loop (one cycle)
82    void tick();
83
84    class CpuPort : public Port
85    {
86      public:
87
88        CpuPort(const std::string &_name, AtomicSimpleCPU *_cpu)
89            : Port(_name, _cpu), cpu(_cpu)
90        { }
91
92        bool snoopRangeSent;
93
94      protected:
95
96        AtomicSimpleCPU *cpu;
97
98        virtual bool recvTiming(PacketPtr pkt);
99
100        virtual Tick recvAtomic(PacketPtr pkt);
101
102        virtual void recvFunctional(PacketPtr pkt);
103
104        virtual void recvStatusChange(Status status);
105
106        virtual void recvRetry();
107
108        virtual void getDeviceAddressRanges(AddrRangeList &resp,
109            bool &snoop)
110        { resp.clear(); snoop = true; }
111
112    };
113    CpuPort icachePort;
114
115    class DcachePort : public CpuPort
116    {
117      public:
118        DcachePort(const std::string &_name, AtomicSimpleCPU *_cpu)
119            : CpuPort(_name, _cpu)
120        { }
121
122        virtual void setPeer(Port *port);
123    };
124    DcachePort dcachePort;
125
126    CpuPort physmemPort;
127    bool hasPhysMemPort;
128    Request ifetch_req;
129    Request data_read_req;
130    Request data_write_req;
131
132    bool dcache_access;
133    Tick dcache_latency;
134
135    Range<Addr> physMemAddr;
136
137  public:
138
139    virtual Port *getPort(const std::string &if_name, int idx = -1);
140
141    virtual void serialize(std::ostream &os);
142    virtual void unserialize(Checkpoint *cp, const std::string &section);
143    virtual void resume();
144
145    void switchOut();
146    void takeOverFrom(BaseCPU *oldCPU);
147
148    virtual void activateContext(int thread_num, int delay);
149    virtual void suspendContext(int thread_num);
150
151    template <class T>
152    Fault read(Addr addr, T &data, unsigned flags);
153
154    template <class T>
155    Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
156
157    Fault translateDataReadAddr(Addr vaddr, Addr &paddr,
158            int size, unsigned flags);
159    Fault translateDataWriteAddr(Addr vaddr, Addr &paddr,
160            int size, unsigned flags);
161
162    /**
163     * Print state of address in memory system via PrintReq (for
164     * debugging).
165     */
166    void printAddr(Addr a);
167};
168
169#endif // __CPU_SIMPLE_ATOMIC_HH__
170