atomic.hh revision 10913:38dbdeea7f1f 
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 */
42
43#ifndef __CPU_SIMPLE_ATOMIC_HH__
44#define __CPU_SIMPLE_ATOMIC_HH__
45
46#include "cpu/simple/base.hh"
47#include "params/AtomicSimpleCPU.hh"
48#include "sim/probe/probe.hh"
49
50class AtomicSimpleCPU : public BaseSimpleCPU
51{
52  public:
53
54    AtomicSimpleCPU(AtomicSimpleCPUParams *params);
55    virtual ~AtomicSimpleCPU();
56
57    virtual void init();
58
59  private:
60
61    struct TickEvent : public Event
62    {
63        AtomicSimpleCPU *cpu;
64
65        TickEvent(AtomicSimpleCPU *c);
66        void process();
67        const char *description() const;
68    };
69
70    TickEvent tickEvent;
71
72    const int width;
73    bool locked;
74    const bool simulate_data_stalls;
75    const bool simulate_inst_stalls;
76
77    // main simulation loop (one cycle)
78    void tick();
79
80    /**
81     * Check if a system is in a drained state.
82     *
83     * We need to drain if:
84     * <ul>
85     * <li>We are in the middle of a microcode sequence as some CPUs
86     *     (e.g., HW accelerated CPUs) can't be started in the middle
87     *     of a gem5 microcode sequence.
88     *
89     * <li>The CPU is in a LLSC region. This shouldn't normally happen
90     *     as these are executed atomically within a single tick()
91     *     call. The only way this can happen at the moment is if
92     *     there is an event in the PC event queue that affects the
93     *     CPU state while it is in an LLSC region.
94     *
95     * <li>Stay at PC is true.
96     * </ul>
97     */
98    bool isDrained() {
99        return microPC() == 0 &&
100            !locked &&
101            !stayAtPC;
102    }
103
104    /**
105     * Try to complete a drain request.
106     *
107     * @returns true if the CPU is drained, false otherwise.
108     */
109    bool tryCompleteDrain();
110
111    /**
112     * An AtomicCPUPort overrides the default behaviour of the
113     * recvAtomicSnoop and ignores the packet instead of panicking. It
114     * also provides an implementation for the purely virtual timing
115     * functions and panics on either of these.
116     */
117    class AtomicCPUPort : public MasterPort
118    {
119
120      public:
121
122        AtomicCPUPort(const std::string &_name, BaseSimpleCPU* _cpu)
123            : MasterPort(_name, _cpu)
124        { }
125
126      protected:
127        virtual Tick recvAtomicSnoop(PacketPtr pkt) { return 0; }
128
129        bool recvTimingResp(PacketPtr pkt)
130        {
131            panic("Atomic CPU doesn't expect recvTimingResp!\n");
132            return true;
133        }
134
135        void recvReqRetry()
136        {
137            panic("Atomic CPU doesn't expect recvRetry!\n");
138        }
139
140    };
141
142    class AtomicCPUDPort : public AtomicCPUPort
143    {
144
145      public:
146
147        AtomicCPUDPort(const std::string &_name, BaseSimpleCPU* _cpu)
148            : AtomicCPUPort(_name, _cpu), cpu(_cpu)
149        {
150            cacheBlockMask = ~(cpu->cacheLineSize() - 1);
151        }
152
153        bool isSnooping() const { return true; }
154
155        Addr cacheBlockMask;
156      protected:
157        BaseSimpleCPU *cpu;
158
159        virtual Tick recvAtomicSnoop(PacketPtr pkt);
160        virtual void recvFunctionalSnoop(PacketPtr pkt);
161    };
162
163
164    AtomicCPUPort icachePort;
165    AtomicCPUDPort dcachePort;
166
167    bool fastmem;
168    Request ifetch_req;
169    Request data_read_req;
170    Request data_write_req;
171
172    bool dcache_access;
173    Tick dcache_latency;
174
175    /** Probe Points. */
176    ProbePointArg<std::pair<SimpleThread*, const StaticInstPtr>> *ppCommit;
177
178  protected:
179
180    /** Return a reference to the data port. */
181    virtual MasterPort &getDataPort() { return dcachePort; }
182
183    /** Return a reference to the instruction port. */
184    virtual MasterPort &getInstPort() { return icachePort; }
185
186  public:
187
188    DrainState drain() M5_ATTR_OVERRIDE;
189    void drainResume() M5_ATTR_OVERRIDE;
190
191    void switchOut();
192    void takeOverFrom(BaseCPU *oldCPU);
193
194    void verifyMemoryMode() const;
195
196    virtual void activateContext(ThreadID thread_num);
197    virtual void suspendContext(ThreadID thread_num);
198
199    Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
200
201    Fault writeMem(uint8_t *data, unsigned size,
202                   Addr addr, unsigned flags, uint64_t *res);
203
204    virtual void regProbePoints();
205
206    /**
207     * Print state of address in memory system via PrintReq (for
208     * debugging).
209     */
210    void printAddr(Addr a);
211};
212
213#endif // __CPU_SIMPLE_ATOMIC_HH__
214