atomic.cc revision 6043:19852407f5c9
11736SN/A/* 27778Sgblack@eecs.umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 31736SN/A * All rights reserved. 41736SN/A * 51736SN/A * Redistribution and use in source and binary forms, with or without 61736SN/A * modification, are permitted provided that the following conditions are 71736SN/A * met: redistributions of source code must retain the above copyright 81736SN/A * notice, this list of conditions and the following disclaimer; 91736SN/A * redistributions in binary form must reproduce the above copyright 101736SN/A * notice, this list of conditions and the following disclaimer in the 111736SN/A * documentation and/or other materials provided with the distribution; 121736SN/A * neither the name of the copyright holders nor the names of its 131736SN/A * contributors may be used to endorse or promote products derived from 141736SN/A * this software without specific prior written permission. 151736SN/A * 161736SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171736SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181736SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191736SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201736SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211736SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221736SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231736SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241736SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251736SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261736SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Steve Reinhardt 297778Sgblack@eecs.umich.edu */ 301736SN/A 311519SN/A#include "arch/locked_mem.hh" 3212247Sgabeblack@google.com#include "arch/mmaped_ipr.hh" 3312247Sgabeblack@google.com#include "arch/utility.hh" 3412247Sgabeblack@google.com#include "base/bigint.hh" 3512247Sgabeblack@google.com#include "cpu/exetrace.hh" 3612247Sgabeblack@google.com#include "cpu/simple/atomic.hh" 3712247Sgabeblack@google.com#include "mem/packet.hh" 3812247Sgabeblack@google.com#include "mem/packet_access.hh" 3912247Sgabeblack@google.com#include "params/AtomicSimpleCPU.hh" 4012247Sgabeblack@google.com#include "sim/system.hh" 4112247Sgabeblack@google.com 4212247Sgabeblack@google.comusing namespace std; 4312247Sgabeblack@google.comusing namespace TheISA; 441519SN/A 451519SN/AAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 461519SN/A : Event(CPU_Tick_Pri), cpu(c) 471519SN/A{ 481519SN/A} 491519SN/A 501519SN/A 511519SN/Avoid 521519SN/AAtomicSimpleCPU::TickEvent::process() 531519SN/A{ 5412247Sgabeblack@google.com cpu->tick(); 5512247Sgabeblack@google.com} 5612247Sgabeblack@google.com 5712247Sgabeblack@google.comconst char * 5812247Sgabeblack@google.comAtomicSimpleCPU::TickEvent::description() const 5912247Sgabeblack@google.com{ 6012247Sgabeblack@google.com return "AtomicSimpleCPU tick"; 6112247Sgabeblack@google.com} 6212247Sgabeblack@google.com 6312247Sgabeblack@google.comPort * 6412247Sgabeblack@google.comAtomicSimpleCPU::getPort(const std::string &if_name, int idx) 6512247Sgabeblack@google.com{ 6612247Sgabeblack@google.com if (if_name == "dcache_port") 6712247Sgabeblack@google.com return &dcachePort; 6812247Sgabeblack@google.com else if (if_name == "icache_port") 6912247Sgabeblack@google.com return &icachePort; 7012247Sgabeblack@google.com else if (if_name == "physmem_port") { 7112247Sgabeblack@google.com hasPhysMemPort = true; 7212247Sgabeblack@google.com return &physmemPort; 7312247Sgabeblack@google.com } 7412247Sgabeblack@google.com else 7512247Sgabeblack@google.com panic("No Such Port\n"); 7612247Sgabeblack@google.com} 7712247Sgabeblack@google.com 7812247Sgabeblack@google.comvoid 7912247Sgabeblack@google.comAtomicSimpleCPU::init() 8012247Sgabeblack@google.com{ 8112247Sgabeblack@google.com BaseCPU::init(); 8212247Sgabeblack@google.com#if FULL_SYSTEM 8312247Sgabeblack@google.com for (int i = 0; i < threadContexts.size(); ++i) { 8412247Sgabeblack@google.com ThreadContext *tc = threadContexts[i]; 8512247Sgabeblack@google.com 8612247Sgabeblack@google.com // initialize CPU, including PC 8712247Sgabeblack@google.com TheISA::initCPU(tc, tc->contextId()); 8812247Sgabeblack@google.com } 8912247Sgabeblack@google.com#endif 9012247Sgabeblack@google.com if (hasPhysMemPort) { 911519SN/A bool snoop = false; 921606SN/A AddrRangeList pmAddrList; 931606SN/A physmemPort.getPeerAddressRanges(pmAddrList, snoop); 9412247Sgabeblack@google.com physMemAddr = *pmAddrList.begin(); 9512247Sgabeblack@google.com } 9612247Sgabeblack@google.com // Atomic doesn't do MT right now, so contextId == threadId 9712247Sgabeblack@google.com ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT 9812247Sgabeblack@google.com data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too 9912247Sgabeblack@google.com data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too 10012247Sgabeblack@google.com} 10112247Sgabeblack@google.com 10212247Sgabeblack@google.combool 10312247Sgabeblack@google.comAtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt) 10412247Sgabeblack@google.com{ 10512247Sgabeblack@google.com panic("AtomicSimpleCPU doesn't expect recvTiming callback!"); 10612247Sgabeblack@google.com return true; 10712247Sgabeblack@google.com} 10812247Sgabeblack@google.com 10912247Sgabeblack@google.comTick 11012247Sgabeblack@google.comAtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 11112247Sgabeblack@google.com{ 1121606SN/A //Snooping a coherence request, just return 11312247Sgabeblack@google.com return 0; 1141606SN/A} 11512247Sgabeblack@google.com 11612247Sgabeblack@google.comvoid 11712247Sgabeblack@google.comAtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 11812247Sgabeblack@google.com{ 11912247Sgabeblack@google.com //No internal storage to update, just return 12012247Sgabeblack@google.com return; 12112247Sgabeblack@google.com} 12212247Sgabeblack@google.com 12312247Sgabeblack@google.comvoid 12412247Sgabeblack@google.comAtomicSimpleCPU::CpuPort::recvStatusChange(Status status) 1251944SN/A{ 1261606SN/A if (status == RangeChange) { 12712247Sgabeblack@google.com if (!snoopRangeSent) { 12812247Sgabeblack@google.com snoopRangeSent = true; 1291519SN/A sendStatusChange(Port::RangeChange); 1301606SN/A } 1311606SN/A return; 13212247Sgabeblack@google.com } 13312247Sgabeblack@google.com 13412247Sgabeblack@google.com panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!"); 13512247Sgabeblack@google.com} 13612247Sgabeblack@google.com 1371858SN/Avoid 1381606SN/AAtomicSimpleCPU::CpuPort::recvRetry() 13912247Sgabeblack@google.com{ 1401606SN/A panic("AtomicSimpleCPU doesn't expect recvRetry callback!"); 1411606SN/A} 14212247Sgabeblack@google.com 14312247Sgabeblack@google.comvoid 14412247Sgabeblack@google.comAtomicSimpleCPU::DcachePort::setPeer(Port *port) 14512247Sgabeblack@google.com{ 1461858SN/A Port::setPeer(port); 1471519SN/A 1481589SN/A#if FULL_SYSTEM 14912247Sgabeblack@google.com // Update the ThreadContext's memory ports (Functional/Virtual 1501519SN/A // Ports) 1511589SN/A cpu->tcBase()->connectMemPorts(cpu->tcBase()); 15212247Sgabeblack@google.com#endif 1531606SN/A} 1544167SN/A 1551606SN/AAtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) 1561606SN/A : BaseSimpleCPU(p), tickEvent(this), width(p->width), 15712247Sgabeblack@google.com simulate_data_stalls(p->simulate_data_stalls), 15812247Sgabeblack@google.com simulate_inst_stalls(p->simulate_inst_stalls), 1591606SN/A icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this), 1601606SN/A physmemPort(name() + "-iport", this), hasPhysMemPort(false) 1611606SN/A{ 16212247Sgabeblack@google.com _status = Idle; 1631606SN/A 1641606SN/A icachePort.snoopRangeSent = false; 1651606SN/A dcachePort.snoopRangeSent = false; 1661606SN/A 1671606SN/A} 1684167SN/A 1694167SN/A 1704167SN/AAtomicSimpleCPU::~AtomicSimpleCPU() 17112247Sgabeblack@google.com{ 1724167SN/A} 1734167SN/A 1744167SN/Avoid 1754167SN/AAtomicSimpleCPU::serialize(ostream &os) 17612247Sgabeblack@google.com{ 17712247Sgabeblack@google.com SimObject::State so_state = SimObject::getState(); 1784167SN/A SERIALIZE_ENUM(so_state); 1794167SN/A BaseSimpleCPU::serialize(os); 1804167SN/A nameOut(os, csprintf("%s.tickEvent", name())); 1811519SN/A tickEvent.serialize(os); 1821589SN/A} 18312247Sgabeblack@google.com 1841519SN/Avoid 1851589SN/AAtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 18612247Sgabeblack@google.com{ 1871519SN/A SimObject::State so_state; 1881589SN/A UNSERIALIZE_ENUM(so_state); 18912247Sgabeblack@google.com BaseSimpleCPU::unserialize(cp, section); 1907777Sgblack@eecs.umich.edu tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 1917777Sgblack@eecs.umich.edu} 1927777Sgblack@eecs.umich.edu 1937777Sgblack@eecs.umich.eduvoid 1947777Sgblack@eecs.umich.eduAtomicSimpleCPU::resume() 1957777Sgblack@eecs.umich.edu{ 1967777Sgblack@eecs.umich.edu if (_status == Idle || _status == SwitchedOut) 1977777Sgblack@eecs.umich.edu return; 1987777Sgblack@eecs.umich.edu 1997777Sgblack@eecs.umich.edu DPRINTF(SimpleCPU, "Resume\n"); 2007777Sgblack@eecs.umich.edu assert(system->getMemoryMode() == Enums::atomic); 2017777Sgblack@eecs.umich.edu 2027777Sgblack@eecs.umich.edu changeState(SimObject::Running); 2037777Sgblack@eecs.umich.edu if (thread->status() == ThreadContext::Active) { 2047777Sgblack@eecs.umich.edu if (!tickEvent.scheduled()) 2057777Sgblack@eecs.umich.edu schedule(tickEvent, nextCycle()); 2067777Sgblack@eecs.umich.edu } 2077777Sgblack@eecs.umich.edu} 2087777Sgblack@eecs.umich.edu 2097777Sgblack@eecs.umich.eduvoid 2107777Sgblack@eecs.umich.eduAtomicSimpleCPU::switchOut() 2117777Sgblack@eecs.umich.edu{ 2127777Sgblack@eecs.umich.edu assert(_status == Running || _status == Idle); 2137777Sgblack@eecs.umich.edu _status = SwitchedOut; 2147777Sgblack@eecs.umich.edu 2157777Sgblack@eecs.umich.edu tickEvent.squash(); 2167777Sgblack@eecs.umich.edu} 2177777Sgblack@eecs.umich.edu 2187777Sgblack@eecs.umich.edu 2197777Sgblack@eecs.umich.eduvoid 2207777Sgblack@eecs.umich.eduAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 2217777Sgblack@eecs.umich.edu{ 2227777Sgblack@eecs.umich.edu BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 2237777Sgblack@eecs.umich.edu 2247777Sgblack@eecs.umich.edu assert(!tickEvent.scheduled()); 2257777Sgblack@eecs.umich.edu 2267777Sgblack@eecs.umich.edu // if any of this CPU's ThreadContexts are active, mark the CPU as 2277777Sgblack@eecs.umich.edu // running and schedule its tick event. 2287777Sgblack@eecs.umich.edu for (int i = 0; i < threadContexts.size(); ++i) { 2297777Sgblack@eecs.umich.edu ThreadContext *tc = threadContexts[i]; 2307777Sgblack@eecs.umich.edu if (tc->status() == ThreadContext::Active && _status != Running) { 2317777Sgblack@eecs.umich.edu _status = Running; 2327777Sgblack@eecs.umich.edu schedule(tickEvent, nextCycle()); 2337777Sgblack@eecs.umich.edu break; 2347777Sgblack@eecs.umich.edu } 2357777Sgblack@eecs.umich.edu } 2367777Sgblack@eecs.umich.edu if (_status != Running) { 2377777Sgblack@eecs.umich.edu _status = Idle; 2387777Sgblack@eecs.umich.edu } 2399827Sakash.bagdia@arm.com assert(threadContexts.size() == 1); 2409827Sakash.bagdia@arm.com ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT 24112247Sgabeblack@google.com data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too 2429827Sakash.bagdia@arm.com data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too 24310427Sandreas.hansson@arm.com} 24412247Sgabeblack@google.com 24512251Sgabeblack@google.com 24612251Sgabeblack@google.comvoid 24712251Sgabeblack@google.comAtomicSimpleCPU::activateContext(int thread_num, int delay) 248{ 249 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 250 251 assert(thread_num == 0); 252 assert(thread); 253 254 assert(_status == Idle); 255 assert(!tickEvent.scheduled()); 256 257 notIdleFraction++; 258 numCycles += tickToCycles(thread->lastActivate - thread->lastSuspend); 259 260 //Make sure ticks are still on multiples of cycles 261 schedule(tickEvent, nextCycle(curTick + ticks(delay))); 262 _status = Running; 263} 264 265 266void 267AtomicSimpleCPU::suspendContext(int thread_num) 268{ 269 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 270 271 assert(thread_num == 0); 272 assert(thread); 273 274 if (_status == Idle) 275 return; 276 277 assert(_status == Running); 278 279 // tick event may not be scheduled if this gets called from inside 280 // an instruction's execution, e.g. "quiesce" 281 if (tickEvent.scheduled()) 282 deschedule(tickEvent); 283 284 notIdleFraction--; 285 _status = Idle; 286} 287 288 289template <class T> 290Fault 291AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) 292{ 293 // use the CPU's statically allocated read request and packet objects 294 Request *req = &data_read_req; 295 296 if (traceData) { 297 traceData->setAddr(addr); 298 } 299 300 //The block size of our peer. 301 int blockSize = dcachePort.peerBlockSize(); 302 //The size of the data we're trying to read. 303 int dataSize = sizeof(T); 304 305 uint8_t * dataPtr = (uint8_t *)&data; 306 307 //The address of the second part of this access if it needs to be split 308 //across a cache line boundary. 309 Addr secondAddr = roundDown(addr + dataSize - 1, blockSize); 310 311 if(secondAddr > addr) 312 dataSize = secondAddr - addr; 313 314 dcache_latency = 0; 315 316 while(1) { 317 req->setVirt(0, addr, dataSize, flags, thread->readPC()); 318 319 // translate to physical address 320 Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read); 321 322 // Now do the access. 323 if (fault == NoFault) { 324 Packet pkt = Packet(req, 325 req->isLocked() ? MemCmd::LoadLockedReq : MemCmd::ReadReq, 326 Packet::Broadcast); 327 pkt.dataStatic(dataPtr); 328 329 if (req->isMmapedIpr()) 330 dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt); 331 else { 332 if (hasPhysMemPort && pkt.getAddr() == physMemAddr) 333 dcache_latency += physmemPort.sendAtomic(&pkt); 334 else 335 dcache_latency += dcachePort.sendAtomic(&pkt); 336 } 337 dcache_access = true; 338 339 assert(!pkt.isError()); 340 341 if (req->isLocked()) { 342 TheISA::handleLockedRead(thread, req); 343 } 344 } 345 346 // This will need a new way to tell if it has a dcache attached. 347 if (req->isUncacheable()) 348 recordEvent("Uncached Read"); 349 350 //If there's a fault, return it 351 if (fault != NoFault) 352 return fault; 353 //If we don't need to access a second cache line, stop now. 354 if (secondAddr <= addr) 355 { 356 data = gtoh(data); 357 if (traceData) { 358 traceData->setData(data); 359 } 360 return fault; 361 } 362 363 /* 364 * Set up for accessing the second cache line. 365 */ 366 367 //Move the pointer we're reading into to the correct location. 368 dataPtr += dataSize; 369 //Adjust the size to get the remaining bytes. 370 dataSize = addr + sizeof(T) - secondAddr; 371 //And access the right address. 372 addr = secondAddr; 373 } 374} 375 376#ifndef DOXYGEN_SHOULD_SKIP_THIS 377 378template 379Fault 380AtomicSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags); 381 382template 383Fault 384AtomicSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); 385 386template 387Fault 388AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 389 390template 391Fault 392AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 393 394template 395Fault 396AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 397 398template 399Fault 400AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 401 402#endif //DOXYGEN_SHOULD_SKIP_THIS 403 404template<> 405Fault 406AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags) 407{ 408 return read(addr, *(uint64_t*)&data, flags); 409} 410 411template<> 412Fault 413AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags) 414{ 415 return read(addr, *(uint32_t*)&data, flags); 416} 417 418 419template<> 420Fault 421AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 422{ 423 return read(addr, (uint32_t&)data, flags); 424} 425 426 427template <class T> 428Fault 429AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 430{ 431 // use the CPU's statically allocated write request and packet objects 432 Request *req = &data_write_req; 433 434 if (traceData) { 435 traceData->setAddr(addr); 436 } 437 438 //The block size of our peer. 439 int blockSize = dcachePort.peerBlockSize(); 440 //The size of the data we're trying to read. 441 int dataSize = sizeof(T); 442 443 uint8_t * dataPtr = (uint8_t *)&data; 444 445 //The address of the second part of this access if it needs to be split 446 //across a cache line boundary. 447 Addr secondAddr = roundDown(addr + dataSize - 1, blockSize); 448 449 if(secondAddr > addr) 450 dataSize = secondAddr - addr; 451 452 dcache_latency = 0; 453 454 while(1) { 455 req->setVirt(0, addr, dataSize, flags, thread->readPC()); 456 457 // translate to physical address 458 Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write); 459 460 // Now do the access. 461 if (fault == NoFault) { 462 MemCmd cmd = MemCmd::WriteReq; // default 463 bool do_access = true; // flag to suppress cache access 464 465 if (req->isLocked()) { 466 cmd = MemCmd::StoreCondReq; 467 do_access = TheISA::handleLockedWrite(thread, req); 468 } else if (req->isSwap()) { 469 cmd = MemCmd::SwapReq; 470 if (req->isCondSwap()) { 471 assert(res); 472 req->setExtraData(*res); 473 } 474 } 475 476 if (do_access) { 477 Packet pkt = Packet(req, cmd, Packet::Broadcast); 478 pkt.dataStatic(dataPtr); 479 480 if (req->isMmapedIpr()) { 481 dcache_latency += 482 TheISA::handleIprWrite(thread->getTC(), &pkt); 483 } else { 484 //XXX This needs to be outside of the loop in order to 485 //work properly for cache line boundary crossing 486 //accesses in transendian simulations. 487 data = htog(data); 488 if (hasPhysMemPort && pkt.getAddr() == physMemAddr) 489 dcache_latency += physmemPort.sendAtomic(&pkt); 490 else 491 dcache_latency += dcachePort.sendAtomic(&pkt); 492 } 493 dcache_access = true; 494 assert(!pkt.isError()); 495 496 if (req->isSwap()) { 497 assert(res); 498 *res = pkt.get<T>(); 499 } 500 } 501 502 if (res && !req->isSwap()) { 503 *res = req->getExtraData(); 504 } 505 } 506 507 // This will need a new way to tell if it's hooked up to a cache or not. 508 if (req->isUncacheable()) 509 recordEvent("Uncached Write"); 510 511 //If there's a fault or we don't need to access a second cache line, 512 //stop now. 513 if (fault != NoFault || secondAddr <= addr) 514 { 515 // If the write needs to have a fault on the access, consider 516 // calling changeStatus() and changing it to "bad addr write" 517 // or something. 518 if (traceData) { 519 traceData->setData(gtoh(data)); 520 } 521 return fault; 522 } 523 524 /* 525 * Set up for accessing the second cache line. 526 */ 527 528 //Move the pointer we're reading into to the correct location. 529 dataPtr += dataSize; 530 //Adjust the size to get the remaining bytes. 531 dataSize = addr + sizeof(T) - secondAddr; 532 //And access the right address. 533 addr = secondAddr; 534 } 535} 536 537 538#ifndef DOXYGEN_SHOULD_SKIP_THIS 539 540template 541Fault 542AtomicSimpleCPU::write(Twin32_t data, Addr addr, 543 unsigned flags, uint64_t *res); 544 545template 546Fault 547AtomicSimpleCPU::write(Twin64_t data, Addr addr, 548 unsigned flags, uint64_t *res); 549 550template 551Fault 552AtomicSimpleCPU::write(uint64_t data, Addr addr, 553 unsigned flags, uint64_t *res); 554 555template 556Fault 557AtomicSimpleCPU::write(uint32_t data, Addr addr, 558 unsigned flags, uint64_t *res); 559 560template 561Fault 562AtomicSimpleCPU::write(uint16_t data, Addr addr, 563 unsigned flags, uint64_t *res); 564 565template 566Fault 567AtomicSimpleCPU::write(uint8_t data, Addr addr, 568 unsigned flags, uint64_t *res); 569 570#endif //DOXYGEN_SHOULD_SKIP_THIS 571 572template<> 573Fault 574AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 575{ 576 return write(*(uint64_t*)&data, addr, flags, res); 577} 578 579template<> 580Fault 581AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 582{ 583 return write(*(uint32_t*)&data, addr, flags, res); 584} 585 586 587template<> 588Fault 589AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 590{ 591 return write((uint32_t)data, addr, flags, res); 592} 593 594 595void 596AtomicSimpleCPU::tick() 597{ 598 DPRINTF(SimpleCPU, "Tick\n"); 599 600 Tick latency = 0; 601 602 for (int i = 0; i < width; ++i) { 603 numCycles++; 604 605 if (!curStaticInst || !curStaticInst->isDelayedCommit()) 606 checkForInterrupts(); 607 608 checkPcEventQueue(); 609 610 Fault fault = NoFault; 611 612 bool fromRom = isRomMicroPC(thread->readMicroPC()); 613 if (!fromRom && !curMacroStaticInst) { 614 setupFetchRequest(&ifetch_req); 615 fault = thread->itb->translateAtomic(&ifetch_req, tc, 616 BaseTLB::Execute); 617 } 618 619 if (fault == NoFault) { 620 Tick icache_latency = 0; 621 bool icache_access = false; 622 dcache_access = false; // assume no dcache access 623 624 if (!fromRom && !curMacroStaticInst) { 625 // This is commented out because the predecoder would act like 626 // a tiny cache otherwise. It wouldn't be flushed when needed 627 // like the I cache. It should be flushed, and when that works 628 // this code should be uncommented. 629 //Fetch more instruction memory if necessary 630 //if(predecoder.needMoreBytes()) 631 //{ 632 icache_access = true; 633 Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq, 634 Packet::Broadcast); 635 ifetch_pkt.dataStatic(&inst); 636 637 if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr) 638 icache_latency = physmemPort.sendAtomic(&ifetch_pkt); 639 else 640 icache_latency = icachePort.sendAtomic(&ifetch_pkt); 641 642 assert(!ifetch_pkt.isError()); 643 644 // ifetch_req is initialized to read the instruction directly 645 // into the CPU object's inst field. 646 //} 647 } 648 649 preExecute(); 650 651 if (curStaticInst) { 652 fault = curStaticInst->execute(this, traceData); 653 654 // keep an instruction count 655 if (fault == NoFault) 656 countInst(); 657 else if (traceData) { 658 // If there was a fault, we should trace this instruction. 659 delete traceData; 660 traceData = NULL; 661 } 662 663 postExecute(); 664 } 665 666 // @todo remove me after debugging with legion done 667 if (curStaticInst && (!curStaticInst->isMicroop() || 668 curStaticInst->isFirstMicroop())) 669 instCnt++; 670 671 Tick stall_ticks = 0; 672 if (simulate_inst_stalls && icache_access) 673 stall_ticks += icache_latency; 674 675 if (simulate_data_stalls && dcache_access) 676 stall_ticks += dcache_latency; 677 678 if (stall_ticks) { 679 Tick stall_cycles = stall_ticks / ticks(1); 680 Tick aligned_stall_ticks = ticks(stall_cycles); 681 682 if (aligned_stall_ticks < stall_ticks) 683 aligned_stall_ticks += 1; 684 685 latency += aligned_stall_ticks; 686 } 687 688 } 689 if(fault != NoFault || !stayAtPC) 690 advancePC(fault); 691 } 692 693 // instruction takes at least one cycle 694 if (latency < ticks(1)) 695 latency = ticks(1); 696 697 if (_status != Idle) 698 schedule(tickEvent, curTick + latency); 699} 700 701 702void 703AtomicSimpleCPU::printAddr(Addr a) 704{ 705 dcachePort.printAddr(a); 706} 707 708 709//////////////////////////////////////////////////////////////////////// 710// 711// AtomicSimpleCPU Simulation Object 712// 713AtomicSimpleCPU * 714AtomicSimpleCPUParams::create() 715{ 716 numThreads = 1; 717#if !FULL_SYSTEM 718 if (workload.size() != 1) 719 panic("only one workload allowed"); 720#endif 721 return new AtomicSimpleCPU(this); 722} 723