atomic.cc revision 5177
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 */ 30 31#include "arch/locked_mem.hh" 32#include "arch/mmaped_ipr.hh" 33#include "arch/utility.hh" 34#include "base/bigint.hh" 35#include "cpu/exetrace.hh" 36#include "cpu/simple/atomic.hh" 37#include "mem/packet.hh" 38#include "mem/packet_access.hh" 39#include "params/AtomicSimpleCPU.hh" 40#include "sim/system.hh" 41 42using namespace std; 43using namespace TheISA; 44 45AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 46 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 47{ 48} 49 50 51void 52AtomicSimpleCPU::TickEvent::process() 53{ 54 cpu->tick(); 55} 56 57const char * 58AtomicSimpleCPU::TickEvent::description() 59{ 60 return "AtomicSimpleCPU tick"; 61} 62 63Port * 64AtomicSimpleCPU::getPort(const std::string &if_name, int idx) 65{ 66 if (if_name == "dcache_port") 67 return &dcachePort; 68 else if (if_name == "icache_port") 69 return &icachePort; 70 else if (if_name == "physmem_port") { 71 hasPhysMemPort = true; 72 return &physmemPort; 73 } 74 else 75 panic("No Such Port\n"); 76} 77 78void 79AtomicSimpleCPU::init() 80{ 81 BaseCPU::init(); 82#if FULL_SYSTEM 83 for (int i = 0; i < threadContexts.size(); ++i) { 84 ThreadContext *tc = threadContexts[i]; 85 86 // initialize CPU, including PC 87 TheISA::initCPU(tc, tc->readCpuId()); 88 } 89#endif 90 if (hasPhysMemPort) { 91 bool snoop = false; 92 AddrRangeList pmAddrList; 93 physmemPort.getPeerAddressRanges(pmAddrList, snoop); 94 physMemAddr = *pmAddrList.begin(); 95 } 96} 97 98bool 99AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt) 100{ 101 panic("AtomicSimpleCPU doesn't expect recvTiming callback!"); 102 return true; 103} 104 105Tick 106AtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 107{ 108 //Snooping a coherence request, just return 109 return 0; 110} 111 112void 113AtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 114{ 115 //No internal storage to update, just return 116 return; 117} 118 119void 120AtomicSimpleCPU::CpuPort::recvStatusChange(Status status) 121{ 122 if (status == RangeChange) { 123 if (!snoopRangeSent) { 124 snoopRangeSent = true; 125 sendStatusChange(Port::RangeChange); 126 } 127 return; 128 } 129 130 panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!"); 131} 132 133void 134AtomicSimpleCPU::CpuPort::recvRetry() 135{ 136 panic("AtomicSimpleCPU doesn't expect recvRetry callback!"); 137} 138 139void 140AtomicSimpleCPU::DcachePort::setPeer(Port *port) 141{ 142 Port::setPeer(port); 143 144#if FULL_SYSTEM 145 // Update the ThreadContext's memory ports (Functional/Virtual 146 // Ports) 147 cpu->tcBase()->connectMemPorts(); 148#endif 149} 150 151AtomicSimpleCPU::AtomicSimpleCPU(Params *p) 152 : BaseSimpleCPU(p), tickEvent(this), 153 width(p->width), simulate_stalls(p->simulate_stalls), 154 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this), 155 physmemPort(name() + "-iport", this), hasPhysMemPort(false) 156{ 157 _status = Idle; 158 159 icachePort.snoopRangeSent = false; 160 dcachePort.snoopRangeSent = false; 161 162 ifetch_req.setThreadContext(cpuId, 0); // Add thread ID if we add MT 163 data_read_req.setThreadContext(cpuId, 0); // Add thread ID here too 164 data_write_req.setThreadContext(cpuId, 0); // Add thread ID here too 165} 166 167 168AtomicSimpleCPU::~AtomicSimpleCPU() 169{ 170} 171 172void 173AtomicSimpleCPU::serialize(ostream &os) 174{ 175 SimObject::State so_state = SimObject::getState(); 176 SERIALIZE_ENUM(so_state); 177 Status _status = status(); 178 SERIALIZE_ENUM(_status); 179 BaseSimpleCPU::serialize(os); 180 nameOut(os, csprintf("%s.tickEvent", name())); 181 tickEvent.serialize(os); 182} 183 184void 185AtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 186{ 187 SimObject::State so_state; 188 UNSERIALIZE_ENUM(so_state); 189 UNSERIALIZE_ENUM(_status); 190 BaseSimpleCPU::unserialize(cp, section); 191 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 192} 193 194void 195AtomicSimpleCPU::resume() 196{ 197 DPRINTF(SimpleCPU, "Resume\n"); 198 if (_status != SwitchedOut && _status != Idle) { 199 assert(system->getMemoryMode() == Enums::atomic); 200 201 changeState(SimObject::Running); 202 if (thread->status() == ThreadContext::Active) { 203 if (!tickEvent.scheduled()) { 204 tickEvent.schedule(nextCycle()); 205 } 206 } 207 } 208} 209 210void 211AtomicSimpleCPU::switchOut() 212{ 213 assert(status() == Running || status() == Idle); 214 _status = SwitchedOut; 215 216 tickEvent.squash(); 217} 218 219 220void 221AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 222{ 223 BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort); 224 225 assert(!tickEvent.scheduled()); 226 227 // if any of this CPU's ThreadContexts are active, mark the CPU as 228 // running and schedule its tick event. 229 for (int i = 0; i < threadContexts.size(); ++i) { 230 ThreadContext *tc = threadContexts[i]; 231 if (tc->status() == ThreadContext::Active && _status != Running) { 232 _status = Running; 233 tickEvent.schedule(nextCycle()); 234 break; 235 } 236 } 237 if (_status != Running) { 238 _status = Idle; 239 } 240 assert(threadContexts.size() == 1); 241 cpuId = tc->readCpuId(); 242} 243 244 245void 246AtomicSimpleCPU::activateContext(int thread_num, int delay) 247{ 248 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 249 250 assert(thread_num == 0); 251 assert(thread); 252 253 assert(_status == Idle); 254 assert(!tickEvent.scheduled()); 255 256 notIdleFraction++; 257 numCycles += tickToCycles(thread->lastActivate - thread->lastSuspend); 258 259 //Make sure ticks are still on multiples of cycles 260 tickEvent.schedule(nextCycle(curTick + ticks(delay))); 261 _status = Running; 262} 263 264 265void 266AtomicSimpleCPU::suspendContext(int thread_num) 267{ 268 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 269 270 assert(thread_num == 0); 271 assert(thread); 272 273 assert(_status == Running); 274 275 // tick event may not be scheduled if this gets called from inside 276 // an instruction's execution, e.g. "quiesce" 277 if (tickEvent.scheduled()) 278 tickEvent.deschedule(); 279 280 notIdleFraction--; 281 _status = Idle; 282} 283 284 285template <class T> 286Fault 287AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) 288{ 289 // use the CPU's statically allocated read request and packet objects 290 Request *req = &data_read_req; 291 292 if (traceData) { 293 traceData->setAddr(addr); 294 } 295 296 //The block size of our peer. 297 int blockSize = dcachePort.peerBlockSize(); 298 //The size of the data we're trying to read. 299 int dataSize = sizeof(T); 300 301 uint8_t * dataPtr = (uint8_t *)&data; 302 303 //The address of the second part of this access if it needs to be split 304 //across a cache line boundary. 305 Addr secondAddr = roundDown(addr + dataSize - 1, blockSize); 306 307 if(secondAddr > addr) 308 dataSize = secondAddr - addr; 309 310 dcache_latency = 0; 311 312 while(1) { 313 req->setVirt(0, addr, dataSize, flags, thread->readPC()); 314 315 // translate to physical address 316 Fault fault = thread->translateDataReadReq(req); 317 318 // Now do the access. 319 if (fault == NoFault) { 320 Packet pkt = Packet(req, 321 req->isLocked() ? MemCmd::LoadLockedReq : MemCmd::ReadReq, 322 Packet::Broadcast); 323 pkt.dataStatic(dataPtr); 324 325 if (req->isMmapedIpr()) 326 dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt); 327 else { 328 if (hasPhysMemPort && pkt.getAddr() == physMemAddr) 329 dcache_latency += physmemPort.sendAtomic(&pkt); 330 else 331 dcache_latency += dcachePort.sendAtomic(&pkt); 332 } 333 dcache_access = true; 334 335 assert(!pkt.isError()); 336 337 if (req->isLocked()) { 338 TheISA::handleLockedRead(thread, req); 339 } 340 } 341 342 // This will need a new way to tell if it has a dcache attached. 343 if (req->isUncacheable()) 344 recordEvent("Uncached Read"); 345 346 //If there's a fault, return it 347 if (fault != NoFault) 348 return fault; 349 //If we don't need to access a second cache line, stop now. 350 if (secondAddr <= addr) 351 { 352 data = gtoh(data); 353 return fault; 354 } 355 356 /* 357 * Set up for accessing the second cache line. 358 */ 359 360 //Move the pointer we're reading into to the correct location. 361 dataPtr += dataSize; 362 //Adjust the size to get the remaining bytes. 363 dataSize = addr + sizeof(T) - secondAddr; 364 //And access the right address. 365 addr = secondAddr; 366 } 367} 368 369Fault 370AtomicSimpleCPU::translateDataReadAddr(Addr vaddr, Addr & paddr, 371 int size, unsigned flags) 372{ 373 // use the CPU's statically allocated read request and packet objects 374 Request *req = &data_read_req; 375 376 if (traceData) { 377 traceData->setAddr(vaddr); 378 } 379 380 //The block size of our peer. 381 int blockSize = dcachePort.peerBlockSize(); 382 //The size of the data we're trying to read. 383 int dataSize = size; 384 385 bool firstTimeThrough = true; 386 387 //The address of the second part of this access if it needs to be split 388 //across a cache line boundary. 389 Addr secondAddr = roundDown(vaddr + dataSize - 1, blockSize); 390 391 if(secondAddr > vaddr) 392 dataSize = secondAddr - vaddr; 393 394 while(1) { 395 req->setVirt(0, vaddr, dataSize, flags, thread->readPC()); 396 397 // translate to physical address 398 Fault fault = thread->translateDataReadReq(req); 399 400 //If there's a fault, return it 401 if (fault != NoFault) 402 return fault; 403 404 if (firstTimeThrough) { 405 paddr = req->getPaddr(); 406 firstTimeThrough = false; 407 } 408 409 //If we don't need to access a second cache line, stop now. 410 if (secondAddr <= vaddr) 411 return fault; 412 413 /* 414 * Set up for accessing the second cache line. 415 */ 416 417 //Adjust the size to get the remaining bytes. 418 dataSize = vaddr + size - secondAddr; 419 //And access the right address. 420 vaddr = secondAddr; 421 } 422} 423 424#ifndef DOXYGEN_SHOULD_SKIP_THIS 425 426template 427Fault 428AtomicSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags); 429 430template 431Fault 432AtomicSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); 433 434template 435Fault 436AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 437 438template 439Fault 440AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 441 442template 443Fault 444AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 445 446template 447Fault 448AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 449 450#endif //DOXYGEN_SHOULD_SKIP_THIS 451 452template<> 453Fault 454AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags) 455{ 456 return read(addr, *(uint64_t*)&data, flags); 457} 458 459template<> 460Fault 461AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags) 462{ 463 return read(addr, *(uint32_t*)&data, flags); 464} 465 466 467template<> 468Fault 469AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 470{ 471 return read(addr, (uint32_t&)data, flags); 472} 473 474 475template <class T> 476Fault 477AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 478{ 479 // use the CPU's statically allocated write request and packet objects 480 Request *req = &data_write_req; 481 482 if (traceData) { 483 traceData->setAddr(addr); 484 } 485 486 //The block size of our peer. 487 int blockSize = dcachePort.peerBlockSize(); 488 //The size of the data we're trying to read. 489 int dataSize = sizeof(T); 490 491 uint8_t * dataPtr = (uint8_t *)&data; 492 493 //The address of the second part of this access if it needs to be split 494 //across a cache line boundary. 495 Addr secondAddr = roundDown(addr + dataSize - 1, blockSize); 496 497 if(secondAddr > addr) 498 dataSize = secondAddr - addr; 499 500 dcache_latency = 0; 501 502 while(1) { 503 req->setVirt(0, addr, dataSize, flags, thread->readPC()); 504 505 // translate to physical address 506 Fault fault = thread->translateDataWriteReq(req); 507 508 // Now do the access. 509 if (fault == NoFault) { 510 MemCmd cmd = MemCmd::WriteReq; // default 511 bool do_access = true; // flag to suppress cache access 512 513 if (req->isLocked()) { 514 cmd = MemCmd::StoreCondReq; 515 do_access = TheISA::handleLockedWrite(thread, req); 516 } else if (req->isSwap()) { 517 cmd = MemCmd::SwapReq; 518 if (req->isCondSwap()) { 519 assert(res); 520 req->setExtraData(*res); 521 } 522 } 523 524 if (do_access) { 525 Packet pkt = Packet(req, cmd, Packet::Broadcast); 526 pkt.dataStatic(dataPtr); 527 528 if (req->isMmapedIpr()) { 529 dcache_latency += 530 TheISA::handleIprWrite(thread->getTC(), &pkt); 531 } else { 532 //XXX This needs to be outside of the loop in order to 533 //work properly for cache line boundary crossing 534 //accesses in transendian simulations. 535 data = htog(data); 536 if (hasPhysMemPort && pkt.getAddr() == physMemAddr) 537 dcache_latency += physmemPort.sendAtomic(&pkt); 538 else 539 dcache_latency += dcachePort.sendAtomic(&pkt); 540 } 541 dcache_access = true; 542 assert(!pkt.isError()); 543 544 if (req->isSwap()) { 545 assert(res); 546 *res = pkt.get<T>(); 547 } 548 } 549 550 if (res && !req->isSwap()) { 551 *res = req->getExtraData(); 552 } 553 } 554 555 // This will need a new way to tell if it's hooked up to a cache or not. 556 if (req->isUncacheable()) 557 recordEvent("Uncached Write"); 558 559 //If there's a fault or we don't need to access a second cache line, 560 //stop now. 561 if (fault != NoFault || secondAddr <= addr) 562 { 563 // If the write needs to have a fault on the access, consider 564 // calling changeStatus() and changing it to "bad addr write" 565 // or something. 566 return fault; 567 } 568 569 /* 570 * Set up for accessing the second cache line. 571 */ 572 573 //Move the pointer we're reading into to the correct location. 574 dataPtr += dataSize; 575 //Adjust the size to get the remaining bytes. 576 dataSize = addr + sizeof(T) - secondAddr; 577 //And access the right address. 578 addr = secondAddr; 579 } 580} 581 582Fault 583AtomicSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr, 584 int size, unsigned flags) 585{ 586 // use the CPU's statically allocated write request and packet objects 587 Request *req = &data_write_req; 588 589 if (traceData) { 590 traceData->setAddr(vaddr); 591 } 592 593 //The block size of our peer. 594 int blockSize = dcachePort.peerBlockSize(); 595 596 //The address of the second part of this access if it needs to be split 597 //across a cache line boundary. 598 Addr secondAddr = roundDown(vaddr + size - 1, blockSize); 599 600 //The size of the data we're trying to read. 601 int dataSize = size; 602 603 bool firstTimeThrough = true; 604 605 if(secondAddr > vaddr) 606 dataSize = secondAddr - vaddr; 607 608 dcache_latency = 0; 609 610 while(1) { 611 req->setVirt(0, vaddr, flags, flags, thread->readPC()); 612 613 // translate to physical address 614 Fault fault = thread->translateDataWriteReq(req); 615 616 //If there's a fault or we don't need to access a second cache line, 617 //stop now. 618 if (fault != NoFault) 619 return fault; 620 621 if (firstTimeThrough) { 622 paddr = req->getPaddr(); 623 firstTimeThrough = false; 624 } 625 626 if (secondAddr <= vaddr) 627 return fault; 628 629 /* 630 * Set up for accessing the second cache line. 631 */ 632 633 //Adjust the size to get the remaining bytes. 634 dataSize = vaddr + size - secondAddr; 635 //And access the right address. 636 vaddr = secondAddr; 637 } 638} 639 640 641#ifndef DOXYGEN_SHOULD_SKIP_THIS 642 643template 644Fault 645AtomicSimpleCPU::write(Twin32_t data, Addr addr, 646 unsigned flags, uint64_t *res); 647 648template 649Fault 650AtomicSimpleCPU::write(Twin64_t data, Addr addr, 651 unsigned flags, uint64_t *res); 652 653template 654Fault 655AtomicSimpleCPU::write(uint64_t data, Addr addr, 656 unsigned flags, uint64_t *res); 657 658template 659Fault 660AtomicSimpleCPU::write(uint32_t data, Addr addr, 661 unsigned flags, uint64_t *res); 662 663template 664Fault 665AtomicSimpleCPU::write(uint16_t data, Addr addr, 666 unsigned flags, uint64_t *res); 667 668template 669Fault 670AtomicSimpleCPU::write(uint8_t data, Addr addr, 671 unsigned flags, uint64_t *res); 672 673#endif //DOXYGEN_SHOULD_SKIP_THIS 674 675template<> 676Fault 677AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 678{ 679 return write(*(uint64_t*)&data, addr, flags, res); 680} 681 682template<> 683Fault 684AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 685{ 686 return write(*(uint32_t*)&data, addr, flags, res); 687} 688 689 690template<> 691Fault 692AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 693{ 694 return write((uint32_t)data, addr, flags, res); 695} 696 697 698void 699AtomicSimpleCPU::tick() 700{ 701 DPRINTF(SimpleCPU, "Tick\n"); 702 703 Tick latency = ticks(1); // instruction takes one cycle by default 704 705 for (int i = 0; i < width; ++i) { 706 numCycles++; 707 708 if (!curStaticInst || !curStaticInst->isDelayedCommit()) 709 checkForInterrupts(); 710 711 Fault fault = setupFetchRequest(&ifetch_req); 712 713 if (fault == NoFault) { 714 Tick icache_latency = 0; 715 bool icache_access = false; 716 dcache_access = false; // assume no dcache access 717 718 //Fetch more instruction memory if necessary 719 //if(predecoder.needMoreBytes()) 720 //{ 721 icache_access = true; 722 Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq, 723 Packet::Broadcast); 724 ifetch_pkt.dataStatic(&inst); 725 726 if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr) 727 icache_latency = physmemPort.sendAtomic(&ifetch_pkt); 728 else 729 icache_latency = icachePort.sendAtomic(&ifetch_pkt); 730 731 assert(!ifetch_pkt.isError()); 732 733 // ifetch_req is initialized to read the instruction directly 734 // into the CPU object's inst field. 735 //} 736 737 preExecute(); 738 739 if (curStaticInst) { 740 fault = curStaticInst->execute(this, traceData); 741 742 // keep an instruction count 743 if (fault == NoFault) 744 countInst(); 745 else if (traceData) { 746 // If there was a fault, we should trace this instruction. 747 delete traceData; 748 traceData = NULL; 749 } 750 751 postExecute(); 752 } 753 754 // @todo remove me after debugging with legion done 755 if (curStaticInst && (!curStaticInst->isMicroop() || 756 curStaticInst->isFirstMicroop())) 757 instCnt++; 758 759 if (simulate_stalls) { 760 Tick icache_stall = 761 icache_access ? icache_latency - ticks(1) : 0; 762 Tick dcache_stall = 763 dcache_access ? dcache_latency - ticks(1) : 0; 764 Tick stall_cycles = (icache_stall + dcache_stall) / ticks(1); 765 if (ticks(stall_cycles) < (icache_stall + dcache_stall)) 766 latency += ticks(stall_cycles+1); 767 else 768 latency += ticks(stall_cycles); 769 } 770 771 } 772 if(fault != NoFault || !stayAtPC) 773 advancePC(fault); 774 } 775 776 if (_status != Idle) 777 tickEvent.schedule(curTick + latency); 778} 779 780 781//////////////////////////////////////////////////////////////////////// 782// 783// AtomicSimpleCPU Simulation Object 784// 785AtomicSimpleCPU * 786AtomicSimpleCPUParams::create() 787{ 788 AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params(); 789 params->name = name; 790 params->numberOfThreads = 1; 791 params->max_insts_any_thread = max_insts_any_thread; 792 params->max_insts_all_threads = max_insts_all_threads; 793 params->max_loads_any_thread = max_loads_any_thread; 794 params->max_loads_all_threads = max_loads_all_threads; 795 params->progress_interval = progress_interval; 796 params->deferRegistration = defer_registration; 797 params->phase = phase; 798 params->clock = clock; 799 params->functionTrace = function_trace; 800 params->functionTraceStart = function_trace_start; 801 params->width = width; 802 params->simulate_stalls = simulate_stalls; 803 params->system = system; 804 params->cpu_id = cpu_id; 805 params->tracer = tracer; 806 807 params->itb = itb; 808 params->dtb = dtb; 809#if FULL_SYSTEM 810 params->profile = profile; 811 params->do_quiesce = do_quiesce; 812 params->do_checkpoint_insts = do_checkpoint_insts; 813 params->do_statistics_insts = do_statistics_insts; 814#else 815 if (workload.size() != 1) 816 panic("only one workload allowed"); 817 params->process = workload[0]; 818#endif 819 820 AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params); 821 return cpu; 822} 823