atomic.cc revision 3807:1455bc719432
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 */ 30 31#include "arch/locked_mem.hh" 32#include "arch/mmaped_ipr.hh" 33#include "arch/utility.hh" 34#include "cpu/exetrace.hh" 35#include "cpu/simple/atomic.hh" 36#include "mem/packet.hh" 37#include "mem/packet_access.hh" 38#include "sim/builder.hh" 39#include "sim/system.hh" 40 41using namespace std; 42using namespace TheISA; 43 44AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 45 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 46{ 47} 48 49 50void 51AtomicSimpleCPU::TickEvent::process() 52{ 53 cpu->tick(); 54} 55 56const char * 57AtomicSimpleCPU::TickEvent::description() 58{ 59 return "AtomicSimpleCPU tick event"; 60} 61 62Port * 63AtomicSimpleCPU::getPort(const std::string &if_name, int idx) 64{ 65 if (if_name == "dcache_port") 66 return &dcachePort; 67 else if (if_name == "icache_port") 68 return &icachePort; 69 else 70 panic("No Such Port\n"); 71} 72 73void 74AtomicSimpleCPU::init() 75{ 76 BaseCPU::init(); 77#if FULL_SYSTEM 78 for (int i = 0; i < threadContexts.size(); ++i) { 79 ThreadContext *tc = threadContexts[i]; 80 81 // initialize CPU, including PC 82 TheISA::initCPU(tc, tc->readCpuId()); 83 } 84#endif 85} 86 87bool 88AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt) 89{ 90 panic("AtomicSimpleCPU doesn't expect recvTiming callback!"); 91 return true; 92} 93 94Tick 95AtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 96{ 97 //Snooping a coherence request, just return 98 return 0; 99} 100 101void 102AtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt) 103{ 104 //No internal storage to update, just return 105 return; 106} 107 108void 109AtomicSimpleCPU::CpuPort::recvStatusChange(Status status) 110{ 111 if (status == RangeChange) { 112 if (!snoopRangeSent) { 113 snoopRangeSent = true; 114 sendStatusChange(Port::RangeChange); 115 } 116 return; 117 } 118 119 panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!"); 120} 121 122void 123AtomicSimpleCPU::CpuPort::recvRetry() 124{ 125 panic("AtomicSimpleCPU doesn't expect recvRetry callback!"); 126} 127 128 129AtomicSimpleCPU::AtomicSimpleCPU(Params *p) 130 : BaseSimpleCPU(p), tickEvent(this), 131 width(p->width), simulate_stalls(p->simulate_stalls), 132 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this) 133{ 134 _status = Idle; 135 136 icachePort.snoopRangeSent = false; 137 dcachePort.snoopRangeSent = false; 138 139 ifetch_req = new Request(); 140 ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT 141 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast); 142 ifetch_pkt->dataStatic(&inst); 143 144 data_read_req = new Request(); 145 data_read_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too 146 data_read_pkt = new Packet(data_read_req, Packet::ReadReq, 147 Packet::Broadcast); 148 data_read_pkt->dataStatic(&dataReg); 149 150 data_write_req = new Request(); 151 data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too 152 data_write_pkt = new Packet(data_write_req, Packet::WriteReq, 153 Packet::Broadcast); 154} 155 156 157AtomicSimpleCPU::~AtomicSimpleCPU() 158{ 159} 160 161void 162AtomicSimpleCPU::serialize(ostream &os) 163{ 164 SimObject::State so_state = SimObject::getState(); 165 SERIALIZE_ENUM(so_state); 166 Status _status = status(); 167 SERIALIZE_ENUM(_status); 168 BaseSimpleCPU::serialize(os); 169 nameOut(os, csprintf("%s.tickEvent", name())); 170 tickEvent.serialize(os); 171} 172 173void 174AtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 175{ 176 SimObject::State so_state; 177 UNSERIALIZE_ENUM(so_state); 178 UNSERIALIZE_ENUM(_status); 179 BaseSimpleCPU::unserialize(cp, section); 180 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 181} 182 183void 184AtomicSimpleCPU::resume() 185{ 186 if (_status != SwitchedOut && _status != Idle) { 187 assert(system->getMemoryMode() == System::Atomic); 188 189 changeState(SimObject::Running); 190 if (thread->status() == ThreadContext::Active) { 191 if (!tickEvent.scheduled()) { 192 tickEvent.schedule(nextCycle()); 193 } 194 } 195 } 196} 197 198void 199AtomicSimpleCPU::switchOut() 200{ 201 assert(status() == Running || status() == Idle); 202 _status = SwitchedOut; 203 204 tickEvent.squash(); 205} 206 207 208void 209AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 210{ 211 BaseCPU::takeOverFrom(oldCPU); 212 213 assert(!tickEvent.scheduled()); 214 215 // if any of this CPU's ThreadContexts are active, mark the CPU as 216 // running and schedule its tick event. 217 for (int i = 0; i < threadContexts.size(); ++i) { 218 ThreadContext *tc = threadContexts[i]; 219 if (tc->status() == ThreadContext::Active && _status != Running) { 220 _status = Running; 221 tickEvent.schedule(nextCycle()); 222 break; 223 } 224 } 225 if (_status != Running) { 226 _status = Idle; 227 } 228} 229 230 231void 232AtomicSimpleCPU::activateContext(int thread_num, int delay) 233{ 234 assert(thread_num == 0); 235 assert(thread); 236 237 assert(_status == Idle); 238 assert(!tickEvent.scheduled()); 239 240 notIdleFraction++; 241 242#if FULL_SYSTEM 243 // Connect the ThreadContext's memory ports (Functional/Virtual 244 // Ports) 245 tc->connectMemPorts(); 246#endif 247 248 //Make sure ticks are still on multiples of cycles 249 tickEvent.schedule(nextCycle(curTick + cycles(delay))); 250 _status = Running; 251} 252 253 254void 255AtomicSimpleCPU::suspendContext(int thread_num) 256{ 257 assert(thread_num == 0); 258 assert(thread); 259 260 assert(_status == Running); 261 262 // tick event may not be scheduled if this gets called from inside 263 // an instruction's execution, e.g. "quiesce" 264 if (tickEvent.scheduled()) 265 tickEvent.deschedule(); 266 267 notIdleFraction--; 268 _status = Idle; 269} 270 271 272template <class T> 273Fault 274AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) 275{ 276 // use the CPU's statically allocated read request and packet objects 277 Request *req = data_read_req; 278 PacketPtr pkt = data_read_pkt; 279 280 req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 281 282 if (traceData) { 283 traceData->setAddr(addr); 284 } 285 286 // translate to physical address 287 Fault fault = thread->translateDataReadReq(req); 288 289 // Now do the access. 290 if (fault == NoFault) { 291 pkt->reinitFromRequest(); 292 293 if (req->isMmapedIpr()) 294 dcache_latency = TheISA::handleIprRead(thread->getTC(),pkt); 295 else 296 dcache_latency = dcachePort.sendAtomic(pkt); 297 dcache_access = true; 298 299 assert(pkt->result == Packet::Success); 300 data = pkt->get<T>(); 301 302 if (req->isLocked()) { 303 TheISA::handleLockedRead(thread, req); 304 } 305 } 306 307 // This will need a new way to tell if it has a dcache attached. 308 if (req->isUncacheable()) 309 recordEvent("Uncached Read"); 310 311 return fault; 312} 313 314#ifndef DOXYGEN_SHOULD_SKIP_THIS 315 316template 317Fault 318AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 319 320template 321Fault 322AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 323 324template 325Fault 326AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 327 328template 329Fault 330AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 331 332#endif //DOXYGEN_SHOULD_SKIP_THIS 333 334template<> 335Fault 336AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags) 337{ 338 return read(addr, *(uint64_t*)&data, flags); 339} 340 341template<> 342Fault 343AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags) 344{ 345 return read(addr, *(uint32_t*)&data, flags); 346} 347 348 349template<> 350Fault 351AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 352{ 353 return read(addr, (uint32_t&)data, flags); 354} 355 356 357template <class T> 358Fault 359AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 360{ 361 // use the CPU's statically allocated write request and packet objects 362 Request *req = data_write_req; 363 PacketPtr pkt = data_write_pkt; 364 365 req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 366 367 if (traceData) { 368 traceData->setAddr(addr); 369 } 370 371 // translate to physical address 372 Fault fault = thread->translateDataWriteReq(req); 373 374 // Now do the access. 375 if (fault == NoFault) { 376 bool do_access = true; // flag to suppress cache access 377 378 if (req->isLocked()) { 379 do_access = TheISA::handleLockedWrite(thread, req); 380 } 381 382 if (do_access) { 383 pkt->reinitFromRequest(); 384 pkt->dataStatic(&data); 385 386 if (req->isMmapedIpr()) { 387 dcache_latency = TheISA::handleIprWrite(thread->getTC(), pkt); 388 } else { 389 data = htog(data); 390 dcache_latency = dcachePort.sendAtomic(pkt); 391 } 392 dcache_access = true; 393 394 assert(pkt->result == Packet::Success); 395 } 396 397 if (req->isLocked()) { 398 uint64_t scResult = req->getScResult(); 399 if (scResult != 0) { 400 // clear failure counter 401 thread->setStCondFailures(0); 402 } 403 if (res) { 404 *res = req->getScResult(); 405 } 406 } 407 } 408 409 // This will need a new way to tell if it's hooked up to a cache or not. 410 if (req->isUncacheable()) 411 recordEvent("Uncached Write"); 412 413 // If the write needs to have a fault on the access, consider calling 414 // changeStatus() and changing it to "bad addr write" or something. 415 return fault; 416} 417 418 419#ifndef DOXYGEN_SHOULD_SKIP_THIS 420template 421Fault 422AtomicSimpleCPU::write(uint64_t data, Addr addr, 423 unsigned flags, uint64_t *res); 424 425template 426Fault 427AtomicSimpleCPU::write(uint32_t data, Addr addr, 428 unsigned flags, uint64_t *res); 429 430template 431Fault 432AtomicSimpleCPU::write(uint16_t data, Addr addr, 433 unsigned flags, uint64_t *res); 434 435template 436Fault 437AtomicSimpleCPU::write(uint8_t data, Addr addr, 438 unsigned flags, uint64_t *res); 439 440#endif //DOXYGEN_SHOULD_SKIP_THIS 441 442template<> 443Fault 444AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 445{ 446 return write(*(uint64_t*)&data, addr, flags, res); 447} 448 449template<> 450Fault 451AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 452{ 453 return write(*(uint32_t*)&data, addr, flags, res); 454} 455 456 457template<> 458Fault 459AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 460{ 461 return write((uint32_t)data, addr, flags, res); 462} 463 464 465void 466AtomicSimpleCPU::tick() 467{ 468 Tick latency = cycles(1); // instruction takes one cycle by default 469 470 for (int i = 0; i < width; ++i) { 471 numCycles++; 472 473 if (!curStaticInst || !curStaticInst->isDelayedCommit()) 474 checkForInterrupts(); 475 476 Fault fault = setupFetchRequest(ifetch_req); 477 478 if (fault == NoFault) { 479 ifetch_pkt->reinitFromRequest(); 480 481 Tick icache_latency = icachePort.sendAtomic(ifetch_pkt); 482 // ifetch_req is initialized to read the instruction directly 483 // into the CPU object's inst field. 484 485 dcache_access = false; // assume no dcache access 486 preExecute(); 487 fault = curStaticInst->execute(this, traceData); 488 postExecute(); 489 490 if (simulate_stalls) { 491 Tick icache_stall = icache_latency - cycles(1); 492 Tick dcache_stall = 493 dcache_access ? dcache_latency - cycles(1) : 0; 494 Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1); 495 if (cycles(stall_cycles) < (icache_stall + dcache_stall)) 496 latency += cycles(stall_cycles+1); 497 else 498 latency += cycles(stall_cycles); 499 } 500 501 } 502 503 advancePC(fault); 504 } 505 506 if (_status != Idle) 507 tickEvent.schedule(curTick + latency); 508} 509 510 511//////////////////////////////////////////////////////////////////////// 512// 513// AtomicSimpleCPU Simulation Object 514// 515BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 516 517 Param<Counter> max_insts_any_thread; 518 Param<Counter> max_insts_all_threads; 519 Param<Counter> max_loads_any_thread; 520 Param<Counter> max_loads_all_threads; 521 Param<Tick> progress_interval; 522 SimObjectParam<System *> system; 523 Param<int> cpu_id; 524 525#if FULL_SYSTEM 526 SimObjectParam<TheISA::ITB *> itb; 527 SimObjectParam<TheISA::DTB *> dtb; 528 Param<Tick> profile; 529 530 Param<bool> do_quiesce; 531 Param<bool> do_checkpoint_insts; 532 Param<bool> do_statistics_insts; 533#else 534 SimObjectParam<Process *> workload; 535#endif // FULL_SYSTEM 536 537 Param<int> clock; 538 Param<int> phase; 539 540 Param<bool> defer_registration; 541 Param<int> width; 542 Param<bool> function_trace; 543 Param<Tick> function_trace_start; 544 Param<bool> simulate_stalls; 545 546END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 547 548BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 549 550 INIT_PARAM(max_insts_any_thread, 551 "terminate when any thread reaches this inst count"), 552 INIT_PARAM(max_insts_all_threads, 553 "terminate when all threads have reached this inst count"), 554 INIT_PARAM(max_loads_any_thread, 555 "terminate when any thread reaches this load count"), 556 INIT_PARAM(max_loads_all_threads, 557 "terminate when all threads have reached this load count"), 558 INIT_PARAM(progress_interval, "Progress interval"), 559 INIT_PARAM(system, "system object"), 560 INIT_PARAM(cpu_id, "processor ID"), 561 562#if FULL_SYSTEM 563 INIT_PARAM(itb, "Instruction TLB"), 564 INIT_PARAM(dtb, "Data TLB"), 565 INIT_PARAM(profile, ""), 566 INIT_PARAM(do_quiesce, ""), 567 INIT_PARAM(do_checkpoint_insts, ""), 568 INIT_PARAM(do_statistics_insts, ""), 569#else 570 INIT_PARAM(workload, "processes to run"), 571#endif // FULL_SYSTEM 572 573 INIT_PARAM(clock, "clock speed"), 574 INIT_PARAM_DFLT(phase, "clock phase", 0), 575 INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 576 INIT_PARAM(width, "cpu width"), 577 INIT_PARAM(function_trace, "Enable function trace"), 578 INIT_PARAM(function_trace_start, "Cycle to start function trace"), 579 INIT_PARAM(simulate_stalls, "Simulate cache stall cycles") 580 581END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 582 583 584CREATE_SIM_OBJECT(AtomicSimpleCPU) 585{ 586 AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params(); 587 params->name = getInstanceName(); 588 params->numberOfThreads = 1; 589 params->max_insts_any_thread = max_insts_any_thread; 590 params->max_insts_all_threads = max_insts_all_threads; 591 params->max_loads_any_thread = max_loads_any_thread; 592 params->max_loads_all_threads = max_loads_all_threads; 593 params->progress_interval = progress_interval; 594 params->deferRegistration = defer_registration; 595 params->phase = phase; 596 params->clock = clock; 597 params->functionTrace = function_trace; 598 params->functionTraceStart = function_trace_start; 599 params->width = width; 600 params->simulate_stalls = simulate_stalls; 601 params->system = system; 602 params->cpu_id = cpu_id; 603 604#if FULL_SYSTEM 605 params->itb = itb; 606 params->dtb = dtb; 607 params->profile = profile; 608 params->do_quiesce = do_quiesce; 609 params->do_checkpoint_insts = do_checkpoint_insts; 610 params->do_statistics_insts = do_statistics_insts; 611#else 612 params->process = workload; 613#endif 614 615 AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params); 616 return cpu; 617} 618 619REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU) 620 621