atomic.cc revision 3686:fa8d8b90cd8a 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/locked_mem.hh"
32#include "arch/utility.hh"
33#include "cpu/exetrace.hh"
34#include "cpu/simple/atomic.hh"
35#include "mem/packet.hh"
36#include "mem/packet_access.hh"
37#include "sim/builder.hh"
38#include "sim/system.hh"
39
40using namespace std;
41using namespace TheISA;
42
43AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
44    : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
45{
46}
47
48
49void
50AtomicSimpleCPU::TickEvent::process()
51{
52    cpu->tick();
53}
54
55const char *
56AtomicSimpleCPU::TickEvent::description()
57{
58    return "AtomicSimpleCPU tick event";
59}
60
61Port *
62AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
63{
64    if (if_name == "dcache_port")
65        return &dcachePort;
66    else if (if_name == "icache_port")
67        return &icachePort;
68    else
69        panic("No Such Port\n");
70}
71
72void
73AtomicSimpleCPU::init()
74{
75    BaseCPU::init();
76#if FULL_SYSTEM
77    for (int i = 0; i < threadContexts.size(); ++i) {
78        ThreadContext *tc = threadContexts[i];
79
80        // initialize CPU, including PC
81        TheISA::initCPU(tc, tc->readCpuId());
82    }
83#endif
84}
85
86bool
87AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
88{
89    panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
90    return true;
91}
92
93Tick
94AtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
95{
96    //Snooping a coherence request, just return
97    return 0;
98}
99
100void
101AtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
102{
103    //No internal storage to update, just return
104    return;
105}
106
107void
108AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
109{
110    if (status == RangeChange) {
111        if (!snoopRangeSent) {
112            snoopRangeSent = true;
113            sendStatusChange(Port::RangeChange);
114        }
115        return;
116    }
117
118    panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
119}
120
121void
122AtomicSimpleCPU::CpuPort::recvRetry()
123{
124    panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
125}
126
127
128AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
129    : BaseSimpleCPU(p), tickEvent(this),
130      width(p->width), simulate_stalls(p->simulate_stalls),
131      icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
132{
133    _status = Idle;
134
135    icachePort.snoopRangeSent = false;
136    dcachePort.snoopRangeSent = false;
137
138    ifetch_req = new Request();
139    ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
140    ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
141    ifetch_pkt->dataStatic(&inst);
142
143    data_read_req = new Request();
144    data_read_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
145    data_read_pkt = new Packet(data_read_req, Packet::ReadReq,
146                               Packet::Broadcast);
147    data_read_pkt->dataStatic(&dataReg);
148
149    data_write_req = new Request();
150    data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
151    data_write_pkt = new Packet(data_write_req, Packet::WriteReq,
152                                Packet::Broadcast);
153}
154
155
156AtomicSimpleCPU::~AtomicSimpleCPU()
157{
158}
159
160void
161AtomicSimpleCPU::serialize(ostream &os)
162{
163    SimObject::State so_state = SimObject::getState();
164    SERIALIZE_ENUM(so_state);
165    Status _status = status();
166    SERIALIZE_ENUM(_status);
167    BaseSimpleCPU::serialize(os);
168    nameOut(os, csprintf("%s.tickEvent", name()));
169    tickEvent.serialize(os);
170}
171
172void
173AtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
174{
175    SimObject::State so_state;
176    UNSERIALIZE_ENUM(so_state);
177    UNSERIALIZE_ENUM(_status);
178    BaseSimpleCPU::unserialize(cp, section);
179    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
180}
181
182void
183AtomicSimpleCPU::resume()
184{
185    if (_status != SwitchedOut && _status != Idle) {
186        assert(system->getMemoryMode() == System::Atomic);
187
188        changeState(SimObject::Running);
189        if (thread->status() == ThreadContext::Active) {
190            if (!tickEvent.scheduled()) {
191                tickEvent.schedule(nextCycle());
192            }
193        }
194    }
195}
196
197void
198AtomicSimpleCPU::switchOut()
199{
200    assert(status() == Running || status() == Idle);
201    _status = SwitchedOut;
202
203    tickEvent.squash();
204}
205
206
207void
208AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
209{
210    BaseCPU::takeOverFrom(oldCPU);
211
212    assert(!tickEvent.scheduled());
213
214    // if any of this CPU's ThreadContexts are active, mark the CPU as
215    // running and schedule its tick event.
216    for (int i = 0; i < threadContexts.size(); ++i) {
217        ThreadContext *tc = threadContexts[i];
218        if (tc->status() == ThreadContext::Active && _status != Running) {
219            _status = Running;
220            tickEvent.schedule(nextCycle());
221            break;
222        }
223    }
224    if (_status != Running) {
225        _status = Idle;
226    }
227}
228
229
230void
231AtomicSimpleCPU::activateContext(int thread_num, int delay)
232{
233    assert(thread_num == 0);
234    assert(thread);
235
236    assert(_status == Idle);
237    assert(!tickEvent.scheduled());
238
239    notIdleFraction++;
240
241#if FULL_SYSTEM
242    // Connect the ThreadContext's memory ports (Functional/Virtual
243    // Ports)
244    tc->connectMemPorts();
245#endif
246
247    //Make sure ticks are still on multiples of cycles
248    tickEvent.schedule(nextCycle(curTick + cycles(delay)));
249    _status = Running;
250}
251
252
253void
254AtomicSimpleCPU::suspendContext(int thread_num)
255{
256    assert(thread_num == 0);
257    assert(thread);
258
259    assert(_status == Running);
260
261    // tick event may not be scheduled if this gets called from inside
262    // an instruction's execution, e.g. "quiesce"
263    if (tickEvent.scheduled())
264        tickEvent.deschedule();
265
266    notIdleFraction--;
267    _status = Idle;
268}
269
270
271template <class T>
272Fault
273AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
274{
275    // use the CPU's statically allocated read request and packet objects
276    Request *req = data_read_req;
277    PacketPtr pkt = data_read_pkt;
278
279    req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
280
281    if (traceData) {
282        traceData->setAddr(addr);
283    }
284
285    // translate to physical address
286    Fault fault = thread->translateDataReadReq(req);
287
288    // Now do the access.
289    if (fault == NoFault) {
290        pkt->reinitFromRequest();
291
292        dcache_latency = dcachePort.sendAtomic(pkt);
293        dcache_access = true;
294
295        assert(pkt->result == Packet::Success);
296        data = pkt->get<T>();
297
298        if (req->isLocked()) {
299            TheISA::handleLockedRead(thread, req);
300        }
301    }
302
303    // This will need a new way to tell if it has a dcache attached.
304    if (req->isUncacheable())
305        recordEvent("Uncached Read");
306
307    return fault;
308}
309
310#ifndef DOXYGEN_SHOULD_SKIP_THIS
311
312template
313Fault
314AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
315
316template
317Fault
318AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
319
320template
321Fault
322AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
323
324template
325Fault
326AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
327
328#endif //DOXYGEN_SHOULD_SKIP_THIS
329
330template<>
331Fault
332AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
333{
334    return read(addr, *(uint64_t*)&data, flags);
335}
336
337template<>
338Fault
339AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
340{
341    return read(addr, *(uint32_t*)&data, flags);
342}
343
344
345template<>
346Fault
347AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
348{
349    return read(addr, (uint32_t&)data, flags);
350}
351
352
353template <class T>
354Fault
355AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
356{
357    // use the CPU's statically allocated write request and packet objects
358    Request *req = data_write_req;
359    PacketPtr pkt = data_write_pkt;
360
361    req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
362
363    if (traceData) {
364        traceData->setAddr(addr);
365    }
366
367    // translate to physical address
368    Fault fault = thread->translateDataWriteReq(req);
369
370    // Now do the access.
371    if (fault == NoFault) {
372        bool do_access = true;  // flag to suppress cache access
373
374        if (req->isLocked()) {
375            do_access = TheISA::handleLockedWrite(thread, req);
376        }
377
378        if (do_access) {
379            data = htog(data);
380            pkt->reinitFromRequest();
381            pkt->dataStatic(&data);
382
383            dcache_latency = dcachePort.sendAtomic(pkt);
384            dcache_access = true;
385
386            assert(pkt->result == Packet::Success);
387        }
388
389        if (req->isLocked()) {
390            uint64_t scResult = req->getScResult();
391            if (scResult != 0) {
392                // clear failure counter
393                thread->setStCondFailures(0);
394            }
395            if (res) {
396                *res = req->getScResult();
397            }
398        }
399    }
400
401    // This will need a new way to tell if it's hooked up to a cache or not.
402    if (req->isUncacheable())
403        recordEvent("Uncached Write");
404
405    // If the write needs to have a fault on the access, consider calling
406    // changeStatus() and changing it to "bad addr write" or something.
407    return fault;
408}
409
410
411#ifndef DOXYGEN_SHOULD_SKIP_THIS
412template
413Fault
414AtomicSimpleCPU::write(uint64_t data, Addr addr,
415                       unsigned flags, uint64_t *res);
416
417template
418Fault
419AtomicSimpleCPU::write(uint32_t data, Addr addr,
420                       unsigned flags, uint64_t *res);
421
422template
423Fault
424AtomicSimpleCPU::write(uint16_t data, Addr addr,
425                       unsigned flags, uint64_t *res);
426
427template
428Fault
429AtomicSimpleCPU::write(uint8_t data, Addr addr,
430                       unsigned flags, uint64_t *res);
431
432#endif //DOXYGEN_SHOULD_SKIP_THIS
433
434template<>
435Fault
436AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
437{
438    return write(*(uint64_t*)&data, addr, flags, res);
439}
440
441template<>
442Fault
443AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
444{
445    return write(*(uint32_t*)&data, addr, flags, res);
446}
447
448
449template<>
450Fault
451AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
452{
453    return write((uint32_t)data, addr, flags, res);
454}
455
456
457void
458AtomicSimpleCPU::tick()
459{
460    Tick latency = cycles(1); // instruction takes one cycle by default
461
462    for (int i = 0; i < width; ++i) {
463        numCycles++;
464
465        if (!curStaticInst || !curStaticInst->isDelayedCommit())
466            checkForInterrupts();
467
468        Fault fault = setupFetchRequest(ifetch_req);
469
470        if (fault == NoFault) {
471            ifetch_pkt->reinitFromRequest();
472
473            Tick icache_latency = icachePort.sendAtomic(ifetch_pkt);
474            // ifetch_req is initialized to read the instruction directly
475            // into the CPU object's inst field.
476
477            dcache_access = false; // assume no dcache access
478            preExecute();
479            fault = curStaticInst->execute(this, traceData);
480            postExecute();
481
482            if (simulate_stalls) {
483                Tick icache_stall = icache_latency - cycles(1);
484                Tick dcache_stall =
485                    dcache_access ? dcache_latency - cycles(1) : 0;
486                Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
487                if (cycles(stall_cycles) < (icache_stall + dcache_stall))
488                    latency += cycles(stall_cycles+1);
489                else
490                    latency += cycles(stall_cycles);
491            }
492
493        }
494
495        advancePC(fault);
496    }
497
498    if (_status != Idle)
499        tickEvent.schedule(curTick + latency);
500}
501
502
503////////////////////////////////////////////////////////////////////////
504//
505//  AtomicSimpleCPU Simulation Object
506//
507BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
508
509    Param<Counter> max_insts_any_thread;
510    Param<Counter> max_insts_all_threads;
511    Param<Counter> max_loads_any_thread;
512    Param<Counter> max_loads_all_threads;
513    Param<Tick> progress_interval;
514    SimObjectParam<System *> system;
515    Param<int> cpu_id;
516
517#if FULL_SYSTEM
518    SimObjectParam<TheISA::ITB *> itb;
519    SimObjectParam<TheISA::DTB *> dtb;
520    Param<Tick> profile;
521
522    Param<bool> do_quiesce;
523    Param<bool> do_checkpoint_insts;
524    Param<bool> do_statistics_insts;
525#else
526    SimObjectParam<Process *> workload;
527#endif // FULL_SYSTEM
528
529    Param<int> clock;
530    Param<int> phase;
531
532    Param<bool> defer_registration;
533    Param<int> width;
534    Param<bool> function_trace;
535    Param<Tick> function_trace_start;
536    Param<bool> simulate_stalls;
537
538END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
539
540BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
541
542    INIT_PARAM(max_insts_any_thread,
543               "terminate when any thread reaches this inst count"),
544    INIT_PARAM(max_insts_all_threads,
545               "terminate when all threads have reached this inst count"),
546    INIT_PARAM(max_loads_any_thread,
547               "terminate when any thread reaches this load count"),
548    INIT_PARAM(max_loads_all_threads,
549               "terminate when all threads have reached this load count"),
550    INIT_PARAM(progress_interval, "Progress interval"),
551    INIT_PARAM(system, "system object"),
552    INIT_PARAM(cpu_id, "processor ID"),
553
554#if FULL_SYSTEM
555    INIT_PARAM(itb, "Instruction TLB"),
556    INIT_PARAM(dtb, "Data TLB"),
557    INIT_PARAM(profile, ""),
558    INIT_PARAM(do_quiesce, ""),
559    INIT_PARAM(do_checkpoint_insts, ""),
560    INIT_PARAM(do_statistics_insts, ""),
561#else
562    INIT_PARAM(workload, "processes to run"),
563#endif // FULL_SYSTEM
564
565    INIT_PARAM(clock, "clock speed"),
566    INIT_PARAM_DFLT(phase, "clock phase", 0),
567    INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
568    INIT_PARAM(width, "cpu width"),
569    INIT_PARAM(function_trace, "Enable function trace"),
570    INIT_PARAM(function_trace_start, "Cycle to start function trace"),
571    INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
572
573END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
574
575
576CREATE_SIM_OBJECT(AtomicSimpleCPU)
577{
578    AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
579    params->name = getInstanceName();
580    params->numberOfThreads = 1;
581    params->max_insts_any_thread = max_insts_any_thread;
582    params->max_insts_all_threads = max_insts_all_threads;
583    params->max_loads_any_thread = max_loads_any_thread;
584    params->max_loads_all_threads = max_loads_all_threads;
585    params->progress_interval = progress_interval;
586    params->deferRegistration = defer_registration;
587    params->phase = phase;
588    params->clock = clock;
589    params->functionTrace = function_trace;
590    params->functionTraceStart = function_trace_start;
591    params->width = width;
592    params->simulate_stalls = simulate_stalls;
593    params->system = system;
594    params->cpu_id = cpu_id;
595
596#if FULL_SYSTEM
597    params->itb = itb;
598    params->dtb = dtb;
599    params->profile = profile;
600    params->do_quiesce = do_quiesce;
601    params->do_checkpoint_insts = do_checkpoint_insts;
602    params->do_statistics_insts = do_statistics_insts;
603#else
604    params->process = workload;
605#endif
606
607    AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
608    return cpu;
609}
610
611REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU)
612
613