atomic.cc revision 3479:4fbcaa81d105 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/locked_mem.hh"
32#include "arch/utility.hh"
33#include "cpu/exetrace.hh"
34#include "cpu/simple/atomic.hh"
35#include "mem/packet.hh"
36#include "mem/packet_access.hh"
37#include "sim/builder.hh"
38#include "sim/system.hh"
39
40using namespace std;
41using namespace TheISA;
42
43AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
44    : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
45{
46}
47
48
49void
50AtomicSimpleCPU::TickEvent::process()
51{
52    cpu->tick();
53}
54
55const char *
56AtomicSimpleCPU::TickEvent::description()
57{
58    return "AtomicSimpleCPU tick event";
59}
60
61Port *
62AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
63{
64    if (if_name == "dcache_port")
65        return &dcachePort;
66    else if (if_name == "icache_port")
67        return &icachePort;
68    else
69        panic("No Such Port\n");
70}
71
72void
73AtomicSimpleCPU::init()
74{
75    BaseCPU::init();
76#if FULL_SYSTEM
77    for (int i = 0; i < threadContexts.size(); ++i) {
78        ThreadContext *tc = threadContexts[i];
79
80        // initialize CPU, including PC
81        TheISA::initCPU(tc, tc->readCpuId());
82    }
83#endif
84}
85
86bool
87AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
88{
89    panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
90    return true;
91}
92
93Tick
94AtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
95{
96    //Snooping a coherence request, just return
97    return curTick;
98}
99
100void
101AtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
102{
103    //No internal storage to update, just return
104    return;
105}
106
107void
108AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
109{
110    if (status == RangeChange)
111        return;
112
113    panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
114}
115
116void
117AtomicSimpleCPU::CpuPort::recvRetry()
118{
119    panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
120}
121
122
123AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
124    : BaseSimpleCPU(p), tickEvent(this),
125      width(p->width), simulate_stalls(p->simulate_stalls),
126      icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
127{
128    _status = Idle;
129
130    ifetch_req = new Request();
131    ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
132    ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
133    ifetch_pkt->dataStatic(&inst);
134
135    data_read_req = new Request();
136    data_read_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
137    data_read_pkt = new Packet(data_read_req, Packet::ReadReq,
138                               Packet::Broadcast);
139    data_read_pkt->dataStatic(&dataReg);
140
141    data_write_req = new Request();
142    data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
143    data_write_pkt = new Packet(data_write_req, Packet::WriteReq,
144                                Packet::Broadcast);
145}
146
147
148AtomicSimpleCPU::~AtomicSimpleCPU()
149{
150}
151
152void
153AtomicSimpleCPU::serialize(ostream &os)
154{
155    SimObject::State so_state = SimObject::getState();
156    SERIALIZE_ENUM(so_state);
157    Status _status = status();
158    SERIALIZE_ENUM(_status);
159    BaseSimpleCPU::serialize(os);
160    nameOut(os, csprintf("%s.tickEvent", name()));
161    tickEvent.serialize(os);
162}
163
164void
165AtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
166{
167    SimObject::State so_state;
168    UNSERIALIZE_ENUM(so_state);
169    UNSERIALIZE_ENUM(_status);
170    BaseSimpleCPU::unserialize(cp, section);
171    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
172}
173
174void
175AtomicSimpleCPU::resume()
176{
177    if (_status != SwitchedOut && _status != Idle) {
178        assert(system->getMemoryMode() == System::Atomic);
179
180        changeState(SimObject::Running);
181        if (thread->status() == ThreadContext::Active) {
182            if (!tickEvent.scheduled()) {
183                Tick nextTick = curTick + cycles(1) - 1;
184                nextTick -= (nextTick % (cycles(1)));
185                tickEvent.schedule(nextTick);
186            }
187        }
188    }
189}
190
191void
192AtomicSimpleCPU::switchOut()
193{
194    assert(status() == Running || status() == Idle);
195    _status = SwitchedOut;
196
197    tickEvent.squash();
198}
199
200
201void
202AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
203{
204    BaseCPU::takeOverFrom(oldCPU);
205
206    assert(!tickEvent.scheduled());
207
208    // if any of this CPU's ThreadContexts are active, mark the CPU as
209    // running and schedule its tick event.
210    for (int i = 0; i < threadContexts.size(); ++i) {
211        ThreadContext *tc = threadContexts[i];
212        if (tc->status() == ThreadContext::Active && _status != Running) {
213            _status = Running;
214            Tick nextTick = curTick + cycles(1) - 1;
215            nextTick -= (nextTick % (cycles(1)));
216            tickEvent.schedule(nextTick);
217            break;
218        }
219    }
220}
221
222
223void
224AtomicSimpleCPU::activateContext(int thread_num, int delay)
225{
226    assert(thread_num == 0);
227    assert(thread);
228
229    assert(_status == Idle);
230    assert(!tickEvent.scheduled());
231
232    notIdleFraction++;
233    //Make sure ticks are still on multiples of cycles
234    Tick nextTick = curTick + cycles(delay + 1) - 1;
235    nextTick -= (nextTick % (cycles(1)));
236    tickEvent.schedule(nextTick);
237    _status = Running;
238}
239
240
241void
242AtomicSimpleCPU::suspendContext(int thread_num)
243{
244    assert(thread_num == 0);
245    assert(thread);
246
247    assert(_status == Running);
248
249    // tick event may not be scheduled if this gets called from inside
250    // an instruction's execution, e.g. "quiesce"
251    if (tickEvent.scheduled())
252        tickEvent.deschedule();
253
254    notIdleFraction--;
255    _status = Idle;
256}
257
258
259template <class T>
260Fault
261AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
262{
263    // use the CPU's statically allocated read request and packet objects
264    Request *req = data_read_req;
265    PacketPtr pkt = data_read_pkt;
266
267    req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
268
269    if (traceData) {
270        traceData->setAddr(addr);
271    }
272
273    // translate to physical address
274    Fault fault = thread->translateDataReadReq(req);
275
276    // Now do the access.
277    if (fault == NoFault) {
278        pkt->reinitFromRequest();
279
280        dcache_latency = dcachePort.sendAtomic(pkt);
281        dcache_access = true;
282
283        assert(pkt->result == Packet::Success);
284        data = pkt->get<T>();
285
286        if (req->isLocked()) {
287            TheISA::handleLockedRead(thread, req);
288        }
289    }
290
291    // This will need a new way to tell if it has a dcache attached.
292    if (req->isUncacheable())
293        recordEvent("Uncached Read");
294
295    return fault;
296}
297
298#ifndef DOXYGEN_SHOULD_SKIP_THIS
299
300template
301Fault
302AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
303
304template
305Fault
306AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
307
308template
309Fault
310AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
311
312template
313Fault
314AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
315
316#endif //DOXYGEN_SHOULD_SKIP_THIS
317
318template<>
319Fault
320AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
321{
322    return read(addr, *(uint64_t*)&data, flags);
323}
324
325template<>
326Fault
327AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
328{
329    return read(addr, *(uint32_t*)&data, flags);
330}
331
332
333template<>
334Fault
335AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
336{
337    return read(addr, (uint32_t&)data, flags);
338}
339
340
341template <class T>
342Fault
343AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
344{
345    // use the CPU's statically allocated write request and packet objects
346    Request *req = data_write_req;
347    PacketPtr pkt = data_write_pkt;
348
349    req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
350
351    if (traceData) {
352        traceData->setAddr(addr);
353    }
354
355    // translate to physical address
356    Fault fault = thread->translateDataWriteReq(req);
357
358    // Now do the access.
359    if (fault == NoFault) {
360        bool do_access = true;  // flag to suppress cache access
361
362        if (req->isLocked()) {
363            do_access = TheISA::handleLockedWrite(thread, req);
364        }
365
366        if (do_access) {
367            data = htog(data);
368            pkt->reinitFromRequest();
369            pkt->dataStatic(&data);
370
371            dcache_latency = dcachePort.sendAtomic(pkt);
372            dcache_access = true;
373
374            assert(pkt->result == Packet::Success);
375        }
376
377        if (req->isLocked()) {
378            uint64_t scResult = req->getScResult();
379            if (scResult != 0) {
380                // clear failure counter
381                thread->setStCondFailures(0);
382            }
383            if (res) {
384                *res = req->getScResult();
385            }
386        }
387    }
388
389    // This will need a new way to tell if it's hooked up to a cache or not.
390    if (req->isUncacheable())
391        recordEvent("Uncached Write");
392
393    // If the write needs to have a fault on the access, consider calling
394    // changeStatus() and changing it to "bad addr write" or something.
395    return fault;
396}
397
398
399#ifndef DOXYGEN_SHOULD_SKIP_THIS
400template
401Fault
402AtomicSimpleCPU::write(uint64_t data, Addr addr,
403                       unsigned flags, uint64_t *res);
404
405template
406Fault
407AtomicSimpleCPU::write(uint32_t data, Addr addr,
408                       unsigned flags, uint64_t *res);
409
410template
411Fault
412AtomicSimpleCPU::write(uint16_t data, Addr addr,
413                       unsigned flags, uint64_t *res);
414
415template
416Fault
417AtomicSimpleCPU::write(uint8_t data, Addr addr,
418                       unsigned flags, uint64_t *res);
419
420#endif //DOXYGEN_SHOULD_SKIP_THIS
421
422template<>
423Fault
424AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
425{
426    return write(*(uint64_t*)&data, addr, flags, res);
427}
428
429template<>
430Fault
431AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
432{
433    return write(*(uint32_t*)&data, addr, flags, res);
434}
435
436
437template<>
438Fault
439AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
440{
441    return write((uint32_t)data, addr, flags, res);
442}
443
444
445void
446AtomicSimpleCPU::tick()
447{
448    Tick latency = cycles(1); // instruction takes one cycle by default
449
450    for (int i = 0; i < width; ++i) {
451        numCycles++;
452
453        if (!curStaticInst || !curStaticInst->isDelayedCommit())
454            checkForInterrupts();
455
456        Fault fault = setupFetchRequest(ifetch_req);
457
458        if (fault == NoFault) {
459            ifetch_pkt->reinitFromRequest();
460
461            Tick icache_latency = icachePort.sendAtomic(ifetch_pkt);
462            // ifetch_req is initialized to read the instruction directly
463            // into the CPU object's inst field.
464
465            dcache_access = false; // assume no dcache access
466            preExecute();
467            fault = curStaticInst->execute(this, traceData);
468            postExecute();
469
470            if (simulate_stalls) {
471                Tick icache_stall = icache_latency - cycles(1);
472                Tick dcache_stall =
473                    dcache_access ? dcache_latency - cycles(1) : 0;
474                Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
475                if (cycles(stall_cycles) < (icache_stall + dcache_stall))
476                    latency += cycles(stall_cycles+1);
477                else
478                    latency += cycles(stall_cycles);
479            }
480
481        }
482
483        advancePC(fault);
484    }
485
486    if (_status != Idle)
487        tickEvent.schedule(curTick + latency);
488}
489
490
491////////////////////////////////////////////////////////////////////////
492//
493//  AtomicSimpleCPU Simulation Object
494//
495BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
496
497    Param<Counter> max_insts_any_thread;
498    Param<Counter> max_insts_all_threads;
499    Param<Counter> max_loads_any_thread;
500    Param<Counter> max_loads_all_threads;
501    Param<Tick> progress_interval;
502    SimObjectParam<System *> system;
503    Param<int> cpu_id;
504
505#if FULL_SYSTEM
506    SimObjectParam<TheISA::ITB *> itb;
507    SimObjectParam<TheISA::DTB *> dtb;
508    Param<Tick> profile;
509#else
510    SimObjectParam<Process *> workload;
511#endif // FULL_SYSTEM
512
513    Param<int> clock;
514
515    Param<bool> defer_registration;
516    Param<int> width;
517    Param<bool> function_trace;
518    Param<Tick> function_trace_start;
519    Param<bool> simulate_stalls;
520
521END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
522
523BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
524
525    INIT_PARAM(max_insts_any_thread,
526               "terminate when any thread reaches this inst count"),
527    INIT_PARAM(max_insts_all_threads,
528               "terminate when all threads have reached this inst count"),
529    INIT_PARAM(max_loads_any_thread,
530               "terminate when any thread reaches this load count"),
531    INIT_PARAM(max_loads_all_threads,
532               "terminate when all threads have reached this load count"),
533    INIT_PARAM(progress_interval, "Progress interval"),
534    INIT_PARAM(system, "system object"),
535    INIT_PARAM(cpu_id, "processor ID"),
536
537#if FULL_SYSTEM
538    INIT_PARAM(itb, "Instruction TLB"),
539    INIT_PARAM(dtb, "Data TLB"),
540    INIT_PARAM(profile, ""),
541#else
542    INIT_PARAM(workload, "processes to run"),
543#endif // FULL_SYSTEM
544
545    INIT_PARAM(clock, "clock speed"),
546    INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
547    INIT_PARAM(width, "cpu width"),
548    INIT_PARAM(function_trace, "Enable function trace"),
549    INIT_PARAM(function_trace_start, "Cycle to start function trace"),
550    INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
551
552END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
553
554
555CREATE_SIM_OBJECT(AtomicSimpleCPU)
556{
557    AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
558    params->name = getInstanceName();
559    params->numberOfThreads = 1;
560    params->max_insts_any_thread = max_insts_any_thread;
561    params->max_insts_all_threads = max_insts_all_threads;
562    params->max_loads_any_thread = max_loads_any_thread;
563    params->max_loads_all_threads = max_loads_all_threads;
564    params->progress_interval = progress_interval;
565    params->deferRegistration = defer_registration;
566    params->clock = clock;
567    params->functionTrace = function_trace;
568    params->functionTraceStart = function_trace_start;
569    params->width = width;
570    params->simulate_stalls = simulate_stalls;
571    params->system = system;
572    params->cpu_id = cpu_id;
573
574#if FULL_SYSTEM
575    params->itb = itb;
576    params->dtb = dtb;
577    params->profile = profile;
578#else
579    params->process = workload;
580#endif
581
582    AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
583    return cpu;
584}
585
586REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU)
587
588