atomic.cc revision 3324:c75da9e726ff
110399Sstephan.diestelhorst@arm.com/* 211128Sali.jafri@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 310399Sstephan.diestelhorst@arm.com * All rights reserved. 410399Sstephan.diestelhorst@arm.com * 510399Sstephan.diestelhorst@arm.com * Redistribution and use in source and binary forms, with or without 610399Sstephan.diestelhorst@arm.com * modification, are permitted provided that the following conditions are 710399Sstephan.diestelhorst@arm.com * met: redistributions of source code must retain the above copyright 810399Sstephan.diestelhorst@arm.com * notice, this list of conditions and the following disclaimer; 910399Sstephan.diestelhorst@arm.com * redistributions in binary form must reproduce the above copyright 1010399Sstephan.diestelhorst@arm.com * notice, this list of conditions and the following disclaimer in the 1110399Sstephan.diestelhorst@arm.com * documentation and/or other materials provided with the distribution; 1210399Sstephan.diestelhorst@arm.com * neither the name of the copyright holders nor the names of its 1310399Sstephan.diestelhorst@arm.com * contributors may be used to endorse or promote products derived from 1410399Sstephan.diestelhorst@arm.com * this software without specific prior written permission. 1510399Sstephan.diestelhorst@arm.com * 1610399Sstephan.diestelhorst@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710399Sstephan.diestelhorst@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810399Sstephan.diestelhorst@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910399Sstephan.diestelhorst@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010399Sstephan.diestelhorst@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110399Sstephan.diestelhorst@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210399Sstephan.diestelhorst@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310399Sstephan.diestelhorst@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410399Sstephan.diestelhorst@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510399Sstephan.diestelhorst@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610399Sstephan.diestelhorst@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710399Sstephan.diestelhorst@arm.com * 2810399Sstephan.diestelhorst@arm.com * Authors: Steve Reinhardt 2910399Sstephan.diestelhorst@arm.com */ 3010399Sstephan.diestelhorst@arm.com 3110399Sstephan.diestelhorst@arm.com#include "arch/locked_mem.hh" 3210399Sstephan.diestelhorst@arm.com#include "arch/utility.hh" 3310399Sstephan.diestelhorst@arm.com#include "cpu/exetrace.hh" 3410399Sstephan.diestelhorst@arm.com#include "cpu/simple/atomic.hh" 3510399Sstephan.diestelhorst@arm.com#include "mem/packet_impl.hh" 3610399Sstephan.diestelhorst@arm.com#include "sim/builder.hh" 3710399Sstephan.diestelhorst@arm.com#include "sim/system.hh" 3810399Sstephan.diestelhorst@arm.com 3910399Sstephan.diestelhorst@arm.comusing namespace std; 4010399Sstephan.diestelhorst@arm.comusing namespace TheISA; 4110399Sstephan.diestelhorst@arm.com 4210399Sstephan.diestelhorst@arm.comAtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 4310399Sstephan.diestelhorst@arm.com : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 4410399Sstephan.diestelhorst@arm.com{ 4510399Sstephan.diestelhorst@arm.com} 4610399Sstephan.diestelhorst@arm.com 4710399Sstephan.diestelhorst@arm.com 4810399Sstephan.diestelhorst@arm.comvoid 4910399Sstephan.diestelhorst@arm.comAtomicSimpleCPU::TickEvent::process() 5010399Sstephan.diestelhorst@arm.com{ 5111129Sali.jafri@arm.com cpu->tick(); 5211129Sali.jafri@arm.com} 5311129Sali.jafri@arm.com 5411129Sali.jafri@arm.comconst char * 5511129Sali.jafri@arm.comAtomicSimpleCPU::TickEvent::description() 5611129Sali.jafri@arm.com{ 5711129Sali.jafri@arm.com return "AtomicSimpleCPU tick event"; 5811129Sali.jafri@arm.com} 5911129Sali.jafri@arm.com 6011129Sali.jafri@arm.comPort * 6111129Sali.jafri@arm.comAtomicSimpleCPU::getPort(const std::string &if_name, int idx) 6210399Sstephan.diestelhorst@arm.com{ 6310399Sstephan.diestelhorst@arm.com if (if_name == "dcache_port") 6410399Sstephan.diestelhorst@arm.com return &dcachePort; 6510399Sstephan.diestelhorst@arm.com else if (if_name == "icache_port") 6610399Sstephan.diestelhorst@arm.com return &icachePort; 6710399Sstephan.diestelhorst@arm.com else 6811128Sali.jafri@arm.com panic("No Such Port\n"); 6911128Sali.jafri@arm.com} 7011128Sali.jafri@arm.com 7111128Sali.jafri@arm.comvoid 7210399Sstephan.diestelhorst@arm.comAtomicSimpleCPU::init() 7311131Sandreas.hansson@arm.com{ 7411131Sandreas.hansson@arm.com //Create Memory Ports (conect them up) 7511128Sali.jafri@arm.com// Port *mem_dport = mem->getPort(""); 7611128Sali.jafri@arm.com// dcachePort.setPeer(mem_dport); 7711128Sali.jafri@arm.com// mem_dport->setPeer(&dcachePort); 7811128Sali.jafri@arm.com 7911128Sali.jafri@arm.com// Port *mem_iport = mem->getPort(""); 8011128Sali.jafri@arm.com// icachePort.setPeer(mem_iport); 8111128Sali.jafri@arm.com// mem_iport->setPeer(&icachePort); 8211131Sandreas.hansson@arm.com 8311131Sandreas.hansson@arm.com BaseCPU::init(); 8411131Sandreas.hansson@arm.com#if FULL_SYSTEM 8511131Sandreas.hansson@arm.com for (int i = 0; i < threadContexts.size(); ++i) { 8610403Sstephan.diestelhorst@arm.com ThreadContext *tc = threadContexts[i]; 8710403Sstephan.diestelhorst@arm.com 8811129Sali.jafri@arm.com // initialize CPU, including PC 8911129Sali.jafri@arm.com TheISA::initCPU(tc, tc->readCpuId()); 9011129Sali.jafri@arm.com } 9111129Sali.jafri@arm.com#endif 9211129Sali.jafri@arm.com} 9310403Sstephan.diestelhorst@arm.com 9410403Sstephan.diestelhorst@arm.combool 9510403Sstephan.diestelhorst@arm.comAtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt) 9610403Sstephan.diestelhorst@arm.com{ 9710403Sstephan.diestelhorst@arm.com panic("AtomicSimpleCPU doesn't expect recvTiming callback!"); 9810403Sstephan.diestelhorst@arm.com return true; 9910403Sstephan.diestelhorst@arm.com} 10010403Sstephan.diestelhorst@arm.com 10110399Sstephan.diestelhorst@arm.comTick 10210399Sstephan.diestelhorst@arm.comAtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt) 10310399Sstephan.diestelhorst@arm.com{ 10410399Sstephan.diestelhorst@arm.com panic("AtomicSimpleCPU doesn't expect recvAtomic callback!"); 10511129Sali.jafri@arm.com return curTick; 10611129Sali.jafri@arm.com} 10711129Sali.jafri@arm.com 10811129Sali.jafri@arm.comvoid 10911129Sali.jafri@arm.comAtomicSimpleCPU::CpuPort::recvFunctional(Packet *pkt) 11011129Sali.jafri@arm.com{ 11110399Sstephan.diestelhorst@arm.com //No internal storage to update, just return 11210399Sstephan.diestelhorst@arm.com return; 11311129Sali.jafri@arm.com} 11410399Sstephan.diestelhorst@arm.com 11510399Sstephan.diestelhorst@arm.comvoid 11610399Sstephan.diestelhorst@arm.comAtomicSimpleCPU::CpuPort::recvStatusChange(Status status) 11710399Sstephan.diestelhorst@arm.com{ 11811129Sali.jafri@arm.com if (status == RangeChange) 11911129Sali.jafri@arm.com return; 12010399Sstephan.diestelhorst@arm.com 12110399Sstephan.diestelhorst@arm.com panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!"); 12210399Sstephan.diestelhorst@arm.com} 12310399Sstephan.diestelhorst@arm.com 12410399Sstephan.diestelhorst@arm.comvoid 12510399Sstephan.diestelhorst@arm.comAtomicSimpleCPU::CpuPort::recvRetry() 12611129Sali.jafri@arm.com{ 12711129Sali.jafri@arm.com panic("AtomicSimpleCPU doesn't expect recvRetry callback!"); 12810399Sstephan.diestelhorst@arm.com} 12910399Sstephan.diestelhorst@arm.com 13011129Sali.jafri@arm.com 13111129Sali.jafri@arm.comAtomicSimpleCPU::AtomicSimpleCPU(Params *p) 13211129Sali.jafri@arm.com : BaseSimpleCPU(p), tickEvent(this), 13311129Sali.jafri@arm.com width(p->width), simulate_stalls(p->simulate_stalls), 13411129Sali.jafri@arm.com icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this) 13511129Sali.jafri@arm.com{ 13611129Sali.jafri@arm.com _status = Idle; 13711129Sali.jafri@arm.com 13811129Sali.jafri@arm.com ifetch_req = new Request(); 13911129Sali.jafri@arm.com ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT 14011129Sali.jafri@arm.com ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast); 14111129Sali.jafri@arm.com ifetch_pkt->dataStatic(&inst); 14211129Sali.jafri@arm.com 14310399Sstephan.diestelhorst@arm.com data_read_req = new Request(); 14411129Sali.jafri@arm.com data_read_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too 14510403Sstephan.diestelhorst@arm.com data_read_pkt = new Packet(data_read_req, Packet::ReadReq, 14610399Sstephan.diestelhorst@arm.com Packet::Broadcast); 14710399Sstephan.diestelhorst@arm.com data_read_pkt->dataStatic(&dataReg); 14810399Sstephan.diestelhorst@arm.com 14911131Sandreas.hansson@arm.com data_write_req = new Request(); 15010399Sstephan.diestelhorst@arm.com data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too 15111131Sandreas.hansson@arm.com data_write_pkt = new Packet(data_write_req, Packet::WriteReq, 15211131Sandreas.hansson@arm.com Packet::Broadcast); 15311131Sandreas.hansson@arm.com} 15411131Sandreas.hansson@arm.com 15511131Sandreas.hansson@arm.com 15611131Sandreas.hansson@arm.comAtomicSimpleCPU::~AtomicSimpleCPU() 15711131Sandreas.hansson@arm.com{ 15811131Sandreas.hansson@arm.com} 15911131Sandreas.hansson@arm.com 16010399Sstephan.diestelhorst@arm.comvoid 16111131Sandreas.hansson@arm.comAtomicSimpleCPU::serialize(ostream &os) 16211131Sandreas.hansson@arm.com{ 16311131Sandreas.hansson@arm.com SimObject::State so_state = SimObject::getState(); 16410821Sandreas.hansson@arm.com SERIALIZE_ENUM(so_state); 16511131Sandreas.hansson@arm.com Status _status = status(); 16610399Sstephan.diestelhorst@arm.com SERIALIZE_ENUM(_status); 16710399Sstephan.diestelhorst@arm.com BaseSimpleCPU::serialize(os); 16810399Sstephan.diestelhorst@arm.com nameOut(os, csprintf("%s.tickEvent", name())); 16910399Sstephan.diestelhorst@arm.com tickEvent.serialize(os); 17010399Sstephan.diestelhorst@arm.com} 17110399Sstephan.diestelhorst@arm.com 17210399Sstephan.diestelhorst@arm.comvoid 17310399Sstephan.diestelhorst@arm.comAtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 17410399Sstephan.diestelhorst@arm.com{ 17510399Sstephan.diestelhorst@arm.com SimObject::State so_state; 17610399Sstephan.diestelhorst@arm.com UNSERIALIZE_ENUM(so_state); 17710399Sstephan.diestelhorst@arm.com UNSERIALIZE_ENUM(_status); 17810399Sstephan.diestelhorst@arm.com BaseSimpleCPU::unserialize(cp, section); 17910399Sstephan.diestelhorst@arm.com tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 18010399Sstephan.diestelhorst@arm.com} 18110399Sstephan.diestelhorst@arm.com 18210399Sstephan.diestelhorst@arm.comvoid 18311128Sali.jafri@arm.comAtomicSimpleCPU::resume() 18410403Sstephan.diestelhorst@arm.com{ 18510403Sstephan.diestelhorst@arm.com if (_status != SwitchedOut && _status != Idle) { 18611129Sali.jafri@arm.com assert(system->getMemoryMode() == System::Atomic); 18711129Sali.jafri@arm.com 18811129Sali.jafri@arm.com changeState(SimObject::Running); 18911129Sali.jafri@arm.com if (thread->status() == ThreadContext::Active) { 19011129Sali.jafri@arm.com if (!tickEvent.scheduled()) 19111129Sali.jafri@arm.com tickEvent.schedule(curTick); 19211129Sali.jafri@arm.com } 19311129Sali.jafri@arm.com } 19411129Sali.jafri@arm.com} 19511129Sali.jafri@arm.com 19611129Sali.jafri@arm.comvoid 19710399Sstephan.diestelhorst@arm.comAtomicSimpleCPU::switchOut() 19810399Sstephan.diestelhorst@arm.com{ 19910399Sstephan.diestelhorst@arm.com assert(status() == Running || status() == Idle); 20010399Sstephan.diestelhorst@arm.com _status = SwitchedOut; 20110399Sstephan.diestelhorst@arm.com 20210403Sstephan.diestelhorst@arm.com tickEvent.squash(); 20310403Sstephan.diestelhorst@arm.com} 20410403Sstephan.diestelhorst@arm.com 20510403Sstephan.diestelhorst@arm.com 20610403Sstephan.diestelhorst@arm.comvoid 20710403Sstephan.diestelhorst@arm.comAtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 20810403Sstephan.diestelhorst@arm.com{ 20910403Sstephan.diestelhorst@arm.com BaseCPU::takeOverFrom(oldCPU); 21010403Sstephan.diestelhorst@arm.com 21110883Sali.jafri@arm.com assert(!tickEvent.scheduled()); 21210883Sali.jafri@arm.com 21310883Sali.jafri@arm.com // if any of this CPU's ThreadContexts are active, mark the CPU as 21410883Sali.jafri@arm.com // running and schedule its tick event. 21510883Sali.jafri@arm.com for (int i = 0; i < threadContexts.size(); ++i) { 21611129Sali.jafri@arm.com ThreadContext *tc = threadContexts[i]; 21710883Sali.jafri@arm.com if (tc->status() == ThreadContext::Active && _status != Running) { 21810399Sstephan.diestelhorst@arm.com _status = Running; 21910399Sstephan.diestelhorst@arm.com tickEvent.schedule(curTick); 22010399Sstephan.diestelhorst@arm.com break; 22110399Sstephan.diestelhorst@arm.com } 22210399Sstephan.diestelhorst@arm.com } 22310399Sstephan.diestelhorst@arm.com} 22410399Sstephan.diestelhorst@arm.com 22511129Sali.jafri@arm.com 22610399Sstephan.diestelhorst@arm.comvoid 22710399Sstephan.diestelhorst@arm.comAtomicSimpleCPU::activateContext(int thread_num, int delay) 22810399Sstephan.diestelhorst@arm.com{ 22910399Sstephan.diestelhorst@arm.com assert(thread_num == 0); 23010399Sstephan.diestelhorst@arm.com assert(thread); 23110399Sstephan.diestelhorst@arm.com 23210399Sstephan.diestelhorst@arm.com assert(_status == Idle); 23310399Sstephan.diestelhorst@arm.com assert(!tickEvent.scheduled()); 23410399Sstephan.diestelhorst@arm.com 23510399Sstephan.diestelhorst@arm.com notIdleFraction++; 23610399Sstephan.diestelhorst@arm.com tickEvent.schedule(curTick + cycles(delay)); 23710399Sstephan.diestelhorst@arm.com _status = Running; 23810399Sstephan.diestelhorst@arm.com} 23910399Sstephan.diestelhorst@arm.com 24010399Sstephan.diestelhorst@arm.com 24110821Sandreas.hansson@arm.comvoid 24210821Sandreas.hansson@arm.comAtomicSimpleCPU::suspendContext(int thread_num) 24310821Sandreas.hansson@arm.com{ 24411128Sali.jafri@arm.com assert(thread_num == 0); 24511128Sali.jafri@arm.com assert(thread); 24611128Sali.jafri@arm.com 24711128Sali.jafri@arm.com assert(_status == Running); 24810821Sandreas.hansson@arm.com 24910821Sandreas.hansson@arm.com // tick event may not be scheduled if this gets called from inside 25011128Sali.jafri@arm.com // an instruction's execution, e.g. "quiesce" 25110399Sstephan.diestelhorst@arm.com if (tickEvent.scheduled()) 25210399Sstephan.diestelhorst@arm.com tickEvent.deschedule(); 25310399Sstephan.diestelhorst@arm.com 25410399Sstephan.diestelhorst@arm.com notIdleFraction--; 25510399Sstephan.diestelhorst@arm.com _status = Idle; 25610399Sstephan.diestelhorst@arm.com} 25710399Sstephan.diestelhorst@arm.com 25810399Sstephan.diestelhorst@arm.com 25910399Sstephan.diestelhorst@arm.comtemplate <class T> 26010399Sstephan.diestelhorst@arm.comFault 26110399Sstephan.diestelhorst@arm.comAtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) 26210399Sstephan.diestelhorst@arm.com{ 26310399Sstephan.diestelhorst@arm.com // use the CPU's statically allocated read request and packet objects 26410399Sstephan.diestelhorst@arm.com Request *req = data_read_req; 26510399Sstephan.diestelhorst@arm.com Packet *pkt = data_read_pkt; 26610399Sstephan.diestelhorst@arm.com 26710399Sstephan.diestelhorst@arm.com req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 26810399Sstephan.diestelhorst@arm.com 26910399Sstephan.diestelhorst@arm.com if (traceData) { 27010399Sstephan.diestelhorst@arm.com traceData->setAddr(addr); 27110399Sstephan.diestelhorst@arm.com } 27210399Sstephan.diestelhorst@arm.com 27310399Sstephan.diestelhorst@arm.com // translate to physical address 27410399Sstephan.diestelhorst@arm.com Fault fault = thread->translateDataReadReq(req); 27510399Sstephan.diestelhorst@arm.com 27610399Sstephan.diestelhorst@arm.com // Now do the access. 27710399Sstephan.diestelhorst@arm.com if (fault == NoFault) { 27810399Sstephan.diestelhorst@arm.com pkt->reinitFromRequest(); 27910399Sstephan.diestelhorst@arm.com 28010399Sstephan.diestelhorst@arm.com dcache_latency = dcachePort.sendAtomic(pkt); 28110399Sstephan.diestelhorst@arm.com dcache_access = true; 28211129Sali.jafri@arm.com 28310399Sstephan.diestelhorst@arm.com assert(pkt->result == Packet::Success); 28410399Sstephan.diestelhorst@arm.com data = pkt->get<T>(); 28510399Sstephan.diestelhorst@arm.com 28610399Sstephan.diestelhorst@arm.com if (req->isLocked()) { 28710399Sstephan.diestelhorst@arm.com TheISA::handleLockedRead(thread, req); 28810399Sstephan.diestelhorst@arm.com } 28910399Sstephan.diestelhorst@arm.com } 29010399Sstephan.diestelhorst@arm.com 29110399Sstephan.diestelhorst@arm.com // This will need a new way to tell if it has a dcache attached. 29210399Sstephan.diestelhorst@arm.com if (req->isUncacheable()) 29310399Sstephan.diestelhorst@arm.com recordEvent("Uncached Read"); 29410399Sstephan.diestelhorst@arm.com 29511128Sali.jafri@arm.com return fault; 29611129Sali.jafri@arm.com} 29711129Sali.jafri@arm.com 29811129Sali.jafri@arm.com#ifndef DOXYGEN_SHOULD_SKIP_THIS 29911129Sali.jafri@arm.com 30010399Sstephan.diestelhorst@arm.comtemplate 30110399Sstephan.diestelhorst@arm.comFault 30210399Sstephan.diestelhorst@arm.comAtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 30310399Sstephan.diestelhorst@arm.com 30410399Sstephan.diestelhorst@arm.comtemplate 30510399Sstephan.diestelhorst@arm.comFault 30610399Sstephan.diestelhorst@arm.comAtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 30710399Sstephan.diestelhorst@arm.com 30810399Sstephan.diestelhorst@arm.comtemplate 30910399Sstephan.diestelhorst@arm.comFault 31010399Sstephan.diestelhorst@arm.comAtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 31110399Sstephan.diestelhorst@arm.com 31210399Sstephan.diestelhorst@arm.comtemplate 31310399Sstephan.diestelhorst@arm.comFault 31410399Sstephan.diestelhorst@arm.comAtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 31510399Sstephan.diestelhorst@arm.com 31610399Sstephan.diestelhorst@arm.com#endif //DOXYGEN_SHOULD_SKIP_THIS 31710399Sstephan.diestelhorst@arm.com 31811129Sali.jafri@arm.comtemplate<> 31910399Sstephan.diestelhorst@arm.comFault 32010399Sstephan.diestelhorst@arm.comAtomicSimpleCPU::read(Addr addr, double &data, unsigned flags) 32110399Sstephan.diestelhorst@arm.com{ 32210399Sstephan.diestelhorst@arm.com return read(addr, *(uint64_t*)&data, flags); 32310399Sstephan.diestelhorst@arm.com} 32410399Sstephan.diestelhorst@arm.com 32510399Sstephan.diestelhorst@arm.comtemplate<> 32610399Sstephan.diestelhorst@arm.comFault 32710821Sandreas.hansson@arm.comAtomicSimpleCPU::read(Addr addr, float &data, unsigned flags) 32810821Sandreas.hansson@arm.com{ 32911128Sali.jafri@arm.com return read(addr, *(uint32_t*)&data, flags); 33011128Sali.jafri@arm.com} 33111128Sali.jafri@arm.com 33211128Sali.jafri@arm.com 33310821Sandreas.hansson@arm.comtemplate<> 33410821Sandreas.hansson@arm.comFault 33511128Sali.jafri@arm.comAtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 33610399Sstephan.diestelhorst@arm.com{ 33710399Sstephan.diestelhorst@arm.com return read(addr, (uint32_t&)data, flags); 33810399Sstephan.diestelhorst@arm.com} 33910399Sstephan.diestelhorst@arm.com 34010399Sstephan.diestelhorst@arm.com 34110399Sstephan.diestelhorst@arm.comtemplate <class T> 34210399Sstephan.diestelhorst@arm.comFault 34310399Sstephan.diestelhorst@arm.comAtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 34410399Sstephan.diestelhorst@arm.com{ 34510399Sstephan.diestelhorst@arm.com // use the CPU's statically allocated write request and packet objects 34611129Sali.jafri@arm.com Request *req = data_write_req; 34711129Sali.jafri@arm.com Packet *pkt = data_write_pkt; 34811129Sali.jafri@arm.com 34910399Sstephan.diestelhorst@arm.com req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 35010399Sstephan.diestelhorst@arm.com 35110399Sstephan.diestelhorst@arm.com if (traceData) { 35211129Sali.jafri@arm.com traceData->setAddr(addr); 35310399Sstephan.diestelhorst@arm.com } 35410399Sstephan.diestelhorst@arm.com 35510399Sstephan.diestelhorst@arm.com // translate to physical address 35610399Sstephan.diestelhorst@arm.com Fault fault = thread->translateDataWriteReq(req); 35710403Sstephan.diestelhorst@arm.com 35810403Sstephan.diestelhorst@arm.com // Now do the access. 35910403Sstephan.diestelhorst@arm.com if (fault == NoFault) { 36010403Sstephan.diestelhorst@arm.com bool do_access = true; // flag to suppress cache access 36110403Sstephan.diestelhorst@arm.com 36210403Sstephan.diestelhorst@arm.com if (req->isLocked()) { 36310403Sstephan.diestelhorst@arm.com do_access = TheISA::handleLockedWrite(thread, req); 36410403Sstephan.diestelhorst@arm.com } 36510403Sstephan.diestelhorst@arm.com 36610403Sstephan.diestelhorst@arm.com if (do_access) { 36710403Sstephan.diestelhorst@arm.com data = htog(data); 36810403Sstephan.diestelhorst@arm.com pkt->reinitFromRequest(); 36910403Sstephan.diestelhorst@arm.com pkt->dataStatic(&data); 37010403Sstephan.diestelhorst@arm.com 37110403Sstephan.diestelhorst@arm.com dcache_latency = dcachePort.sendAtomic(pkt); 37210403Sstephan.diestelhorst@arm.com dcache_access = true; 37310403Sstephan.diestelhorst@arm.com 37410403Sstephan.diestelhorst@arm.com assert(pkt->result == Packet::Success); 37510403Sstephan.diestelhorst@arm.com } 37610403Sstephan.diestelhorst@arm.com 37710403Sstephan.diestelhorst@arm.com if (req->isLocked()) { 37810403Sstephan.diestelhorst@arm.com uint64_t scResult = req->getScResult(); 37910403Sstephan.diestelhorst@arm.com if (scResult != 0) { 38010403Sstephan.diestelhorst@arm.com // clear failure counter 38110403Sstephan.diestelhorst@arm.com thread->setStCondFailures(0); 38210403Sstephan.diestelhorst@arm.com } 38310403Sstephan.diestelhorst@arm.com if (res) { 38410403Sstephan.diestelhorst@arm.com *res = req->getScResult(); 38510403Sstephan.diestelhorst@arm.com } 38610403Sstephan.diestelhorst@arm.com } 38710403Sstephan.diestelhorst@arm.com } 38810403Sstephan.diestelhorst@arm.com 38910399Sstephan.diestelhorst@arm.com // This will need a new way to tell if it's hooked up to a cache or not. 39010399Sstephan.diestelhorst@arm.com if (req->isUncacheable()) 39110399Sstephan.diestelhorst@arm.com recordEvent("Uncached Write"); 39210399Sstephan.diestelhorst@arm.com 39310399Sstephan.diestelhorst@arm.com // If the write needs to have a fault on the access, consider calling 394 // changeStatus() and changing it to "bad addr write" or something. 395 return fault; 396} 397 398 399#ifndef DOXYGEN_SHOULD_SKIP_THIS 400template 401Fault 402AtomicSimpleCPU::write(uint64_t data, Addr addr, 403 unsigned flags, uint64_t *res); 404 405template 406Fault 407AtomicSimpleCPU::write(uint32_t data, Addr addr, 408 unsigned flags, uint64_t *res); 409 410template 411Fault 412AtomicSimpleCPU::write(uint16_t data, Addr addr, 413 unsigned flags, uint64_t *res); 414 415template 416Fault 417AtomicSimpleCPU::write(uint8_t data, Addr addr, 418 unsigned flags, uint64_t *res); 419 420#endif //DOXYGEN_SHOULD_SKIP_THIS 421 422template<> 423Fault 424AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 425{ 426 return write(*(uint64_t*)&data, addr, flags, res); 427} 428 429template<> 430Fault 431AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 432{ 433 return write(*(uint32_t*)&data, addr, flags, res); 434} 435 436 437template<> 438Fault 439AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 440{ 441 return write((uint32_t)data, addr, flags, res); 442} 443 444 445void 446AtomicSimpleCPU::tick() 447{ 448 Tick latency = cycles(1); // instruction takes one cycle by default 449 450 for (int i = 0; i < width; ++i) { 451 numCycles++; 452 453 checkForInterrupts(); 454 455 Fault fault = setupFetchRequest(ifetch_req); 456 457 if (fault == NoFault) { 458 ifetch_pkt->reinitFromRequest(); 459 460 Tick icache_latency = icachePort.sendAtomic(ifetch_pkt); 461 // ifetch_req is initialized to read the instruction directly 462 // into the CPU object's inst field. 463 464 dcache_access = false; // assume no dcache access 465 preExecute(); 466 fault = curStaticInst->execute(this, traceData); 467 postExecute(); 468 469 if (simulate_stalls) { 470 Tick icache_stall = icache_latency - cycles(1); 471 Tick dcache_stall = 472 dcache_access ? dcache_latency - cycles(1) : 0; 473 Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1); 474 if (cycles(stall_cycles) < (icache_stall + dcache_stall)) 475 latency += cycles(stall_cycles+1); 476 else 477 latency += cycles(stall_cycles); 478 } 479 480 } 481 482 advancePC(fault); 483 } 484 485 if (_status != Idle) 486 tickEvent.schedule(curTick + latency); 487} 488 489 490//////////////////////////////////////////////////////////////////////// 491// 492// AtomicSimpleCPU Simulation Object 493// 494BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 495 496 Param<Counter> max_insts_any_thread; 497 Param<Counter> max_insts_all_threads; 498 Param<Counter> max_loads_any_thread; 499 Param<Counter> max_loads_all_threads; 500 Param<Tick> progress_interval; 501 SimObjectParam<MemObject *> mem; 502 SimObjectParam<System *> system; 503 Param<int> cpu_id; 504 505#if FULL_SYSTEM 506 SimObjectParam<AlphaITB *> itb; 507 SimObjectParam<AlphaDTB *> dtb; 508 Param<Tick> profile; 509#else 510 SimObjectParam<Process *> workload; 511#endif // FULL_SYSTEM 512 513 Param<int> clock; 514 515 Param<bool> defer_registration; 516 Param<int> width; 517 Param<bool> function_trace; 518 Param<Tick> function_trace_start; 519 Param<bool> simulate_stalls; 520 521END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 522 523BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 524 525 INIT_PARAM(max_insts_any_thread, 526 "terminate when any thread reaches this inst count"), 527 INIT_PARAM(max_insts_all_threads, 528 "terminate when all threads have reached this inst count"), 529 INIT_PARAM(max_loads_any_thread, 530 "terminate when any thread reaches this load count"), 531 INIT_PARAM(max_loads_all_threads, 532 "terminate when all threads have reached this load count"), 533 INIT_PARAM(progress_interval, "Progress interval"), 534 INIT_PARAM(mem, "memory"), 535 INIT_PARAM(system, "system object"), 536 INIT_PARAM(cpu_id, "processor ID"), 537 538#if FULL_SYSTEM 539 INIT_PARAM(itb, "Instruction TLB"), 540 INIT_PARAM(dtb, "Data TLB"), 541 INIT_PARAM(profile, ""), 542#else 543 INIT_PARAM(workload, "processes to run"), 544#endif // FULL_SYSTEM 545 546 INIT_PARAM(clock, "clock speed"), 547 INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 548 INIT_PARAM(width, "cpu width"), 549 INIT_PARAM(function_trace, "Enable function trace"), 550 INIT_PARAM(function_trace_start, "Cycle to start function trace"), 551 INIT_PARAM(simulate_stalls, "Simulate cache stall cycles") 552 553END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 554 555 556CREATE_SIM_OBJECT(AtomicSimpleCPU) 557{ 558 AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params(); 559 params->name = getInstanceName(); 560 params->numberOfThreads = 1; 561 params->max_insts_any_thread = max_insts_any_thread; 562 params->max_insts_all_threads = max_insts_all_threads; 563 params->max_loads_any_thread = max_loads_any_thread; 564 params->max_loads_all_threads = max_loads_all_threads; 565 params->progress_interval = progress_interval; 566 params->deferRegistration = defer_registration; 567 params->clock = clock; 568 params->functionTrace = function_trace; 569 params->functionTraceStart = function_trace_start; 570 params->width = width; 571 params->simulate_stalls = simulate_stalls; 572 params->mem = mem; 573 params->system = system; 574 params->cpu_id = cpu_id; 575 576#if FULL_SYSTEM 577 params->itb = itb; 578 params->dtb = dtb; 579 params->profile = profile; 580#else 581 params->process = workload; 582#endif 583 584 AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params); 585 return cpu; 586} 587 588REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU) 589 590