atomic.cc revision 3184
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 */ 30 31#include "arch/locked_mem.hh" 32#include "arch/utility.hh" 33#include "cpu/exetrace.hh" 34#include "cpu/simple/atomic.hh" 35#include "mem/packet_impl.hh" 36#include "sim/builder.hh" 37#include "sim/system.hh" 38 39using namespace std; 40using namespace TheISA; 41 42AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 43 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 44{ 45} 46 47 48void 49AtomicSimpleCPU::TickEvent::process() 50{ 51 cpu->tick(); 52} 53 54const char * 55AtomicSimpleCPU::TickEvent::description() 56{ 57 return "AtomicSimpleCPU tick event"; 58} 59 60Port * 61AtomicSimpleCPU::getPort(const std::string &if_name, int idx) 62{ 63 if (if_name == "dcache_port") 64 return &dcachePort; 65 else if (if_name == "icache_port") 66 return &icachePort; 67 else 68 panic("No Such Port\n"); 69} 70 71void 72AtomicSimpleCPU::init() 73{ 74 //Create Memory Ports (conect them up) 75// Port *mem_dport = mem->getPort(""); 76// dcachePort.setPeer(mem_dport); 77// mem_dport->setPeer(&dcachePort); 78 79// Port *mem_iport = mem->getPort(""); 80// icachePort.setPeer(mem_iport); 81// mem_iport->setPeer(&icachePort); 82 83 BaseCPU::init(); 84#if FULL_SYSTEM 85 for (int i = 0; i < threadContexts.size(); ++i) { 86 ThreadContext *tc = threadContexts[i]; 87 88 // initialize CPU, including PC 89 TheISA::initCPU(tc, tc->readCpuId()); 90 } 91#endif 92} 93 94bool 95AtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt) 96{ 97 panic("AtomicSimpleCPU doesn't expect recvTiming callback!"); 98 return true; 99} 100 101Tick 102AtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt) 103{ 104 panic("AtomicSimpleCPU doesn't expect recvAtomic callback!"); 105 return curTick; 106} 107 108void 109AtomicSimpleCPU::CpuPort::recvFunctional(Packet *pkt) 110{ 111 //No internal storage to update, just return 112 return; 113} 114 115void 116AtomicSimpleCPU::CpuPort::recvStatusChange(Status status) 117{ 118 if (status == RangeChange) 119 return; 120 121 panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!"); 122} 123 124void 125AtomicSimpleCPU::CpuPort::recvRetry() 126{ 127 panic("AtomicSimpleCPU doesn't expect recvRetry callback!"); 128} 129 130 131AtomicSimpleCPU::AtomicSimpleCPU(Params *p) 132 : BaseSimpleCPU(p), tickEvent(this), 133 width(p->width), simulate_stalls(p->simulate_stalls), 134 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this) 135{ 136 _status = Idle; 137 138 ifetch_req = new Request(); 139 ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT 140 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast); 141 ifetch_pkt->dataStatic(&inst); 142 143 data_read_req = new Request(); 144 data_read_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too 145 data_read_pkt = new Packet(data_read_req, Packet::ReadReq, 146 Packet::Broadcast); 147 data_read_pkt->dataStatic(&dataReg); 148 149 data_write_req = new Request(); 150 data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too 151 data_write_pkt = new Packet(data_write_req, Packet::WriteReq, 152 Packet::Broadcast); 153} 154 155 156AtomicSimpleCPU::~AtomicSimpleCPU() 157{ 158} 159 160void 161AtomicSimpleCPU::serialize(ostream &os) 162{ 163 SimObject::State so_state = SimObject::getState(); 164 SERIALIZE_ENUM(so_state); 165 BaseSimpleCPU::serialize(os); 166 nameOut(os, csprintf("%s.tickEvent", name())); 167 tickEvent.serialize(os); 168} 169 170void 171AtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 172{ 173 SimObject::State so_state; 174 UNSERIALIZE_ENUM(so_state); 175 BaseSimpleCPU::unserialize(cp, section); 176 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 177} 178 179void 180AtomicSimpleCPU::resume() 181{ 182 assert(system->getMemoryMode() == System::Atomic); 183 changeState(SimObject::Running); 184 if (thread->status() == ThreadContext::Active) { 185 if (!tickEvent.scheduled()) 186 tickEvent.schedule(curTick); 187 } 188} 189 190void 191AtomicSimpleCPU::switchOut() 192{ 193 assert(status() == Running || status() == Idle); 194 _status = SwitchedOut; 195 196 tickEvent.squash(); 197} 198 199 200void 201AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 202{ 203 BaseCPU::takeOverFrom(oldCPU); 204 205 assert(!tickEvent.scheduled()); 206 207 // if any of this CPU's ThreadContexts are active, mark the CPU as 208 // running and schedule its tick event. 209 for (int i = 0; i < threadContexts.size(); ++i) { 210 ThreadContext *tc = threadContexts[i]; 211 if (tc->status() == ThreadContext::Active && _status != Running) { 212 _status = Running; 213 tickEvent.schedule(curTick); 214 break; 215 } 216 } 217} 218 219 220void 221AtomicSimpleCPU::activateContext(int thread_num, int delay) 222{ 223 assert(thread_num == 0); 224 assert(thread); 225 226 assert(_status == Idle); 227 assert(!tickEvent.scheduled()); 228 229 notIdleFraction++; 230 tickEvent.schedule(curTick + cycles(delay)); 231 _status = Running; 232} 233 234 235void 236AtomicSimpleCPU::suspendContext(int thread_num) 237{ 238 assert(thread_num == 0); 239 assert(thread); 240 241 assert(_status == Running); 242 243 // tick event may not be scheduled if this gets called from inside 244 // an instruction's execution, e.g. "quiesce" 245 if (tickEvent.scheduled()) 246 tickEvent.deschedule(); 247 248 notIdleFraction--; 249 _status = Idle; 250} 251 252 253template <class T> 254Fault 255AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) 256{ 257 // use the CPU's statically allocated read request and packet objects 258 Request *req = data_read_req; 259 Packet *pkt = data_read_pkt; 260 261 req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 262 263 if (traceData) { 264 traceData->setAddr(addr); 265 } 266 267 // translate to physical address 268 Fault fault = thread->translateDataReadReq(req); 269 270 // Now do the access. 271 if (fault == NoFault) { 272 pkt->reinitFromRequest(); 273 274 dcache_latency = dcachePort.sendAtomic(pkt); 275 dcache_access = true; 276 277 assert(pkt->result == Packet::Success); 278 data = pkt->get<T>(); 279 280 if (req->isLocked()) { 281 TheISA::handleLockedRead(thread, req); 282 } 283 } 284 285 // This will need a new way to tell if it has a dcache attached. 286 if (req->isUncacheable()) 287 recordEvent("Uncached Read"); 288 289 return fault; 290} 291 292#ifndef DOXYGEN_SHOULD_SKIP_THIS 293 294template 295Fault 296AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 297 298template 299Fault 300AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 301 302template 303Fault 304AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 305 306template 307Fault 308AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 309 310#endif //DOXYGEN_SHOULD_SKIP_THIS 311 312template<> 313Fault 314AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags) 315{ 316 return read(addr, *(uint64_t*)&data, flags); 317} 318 319template<> 320Fault 321AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags) 322{ 323 return read(addr, *(uint32_t*)&data, flags); 324} 325 326 327template<> 328Fault 329AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 330{ 331 return read(addr, (uint32_t&)data, flags); 332} 333 334 335template <class T> 336Fault 337AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 338{ 339 // use the CPU's statically allocated write request and packet objects 340 Request *req = data_write_req; 341 Packet *pkt = data_write_pkt; 342 343 req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 344 345 if (traceData) { 346 traceData->setAddr(addr); 347 } 348 349 // translate to physical address 350 Fault fault = thread->translateDataWriteReq(req); 351 352 // Now do the access. 353 if (fault == NoFault) { 354 bool do_access = true; // flag to suppress cache access 355 356 if (req->isLocked()) { 357 do_access = TheISA::handleLockedWrite(thread, req); 358 } 359 360 if (do_access) { 361 data = htog(data); 362 pkt->reinitFromRequest(); 363 pkt->dataStatic(&data); 364 365 dcache_latency = dcachePort.sendAtomic(pkt); 366 dcache_access = true; 367 368 assert(pkt->result == Packet::Success); 369 } 370 371 if (req->isLocked()) { 372 uint64_t scResult = req->getScResult(); 373 if (scResult != 0) { 374 // clear failure counter 375 thread->setStCondFailures(0); 376 } 377 if (res) { 378 *res = req->getScResult(); 379 } 380 } 381 } 382 383 // This will need a new way to tell if it's hooked up to a cache or not. 384 if (req->isUncacheable()) 385 recordEvent("Uncached Write"); 386 387 // If the write needs to have a fault on the access, consider calling 388 // changeStatus() and changing it to "bad addr write" or something. 389 return fault; 390} 391 392 393#ifndef DOXYGEN_SHOULD_SKIP_THIS 394template 395Fault 396AtomicSimpleCPU::write(uint64_t data, Addr addr, 397 unsigned flags, uint64_t *res); 398 399template 400Fault 401AtomicSimpleCPU::write(uint32_t data, Addr addr, 402 unsigned flags, uint64_t *res); 403 404template 405Fault 406AtomicSimpleCPU::write(uint16_t data, Addr addr, 407 unsigned flags, uint64_t *res); 408 409template 410Fault 411AtomicSimpleCPU::write(uint8_t data, Addr addr, 412 unsigned flags, uint64_t *res); 413 414#endif //DOXYGEN_SHOULD_SKIP_THIS 415 416template<> 417Fault 418AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 419{ 420 return write(*(uint64_t*)&data, addr, flags, res); 421} 422 423template<> 424Fault 425AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 426{ 427 return write(*(uint32_t*)&data, addr, flags, res); 428} 429 430 431template<> 432Fault 433AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 434{ 435 return write((uint32_t)data, addr, flags, res); 436} 437 438 439void 440AtomicSimpleCPU::tick() 441{ 442 Tick latency = cycles(1); // instruction takes one cycle by default 443 444 for (int i = 0; i < width; ++i) { 445 numCycles++; 446 447 checkForInterrupts(); 448 449 Fault fault = setupFetchRequest(ifetch_req); 450 451 if (fault == NoFault) { 452 ifetch_pkt->reinitFromRequest(); 453 454 Tick icache_latency = icachePort.sendAtomic(ifetch_pkt); 455 // ifetch_req is initialized to read the instruction directly 456 // into the CPU object's inst field. 457 458 dcache_access = false; // assume no dcache access 459 preExecute(); 460 fault = curStaticInst->execute(this, traceData); 461 postExecute(); 462 463 if (simulate_stalls) { 464 Tick icache_stall = icache_latency - cycles(1); 465 Tick dcache_stall = 466 dcache_access ? dcache_latency - cycles(1) : 0; 467 Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1); 468 if (cycles(stall_cycles) < (icache_stall + dcache_stall)) 469 latency += cycles(stall_cycles+1); 470 else 471 latency += cycles(stall_cycles); 472 } 473 474 } 475 476 advancePC(fault); 477 } 478 479 if (_status != Idle) 480 tickEvent.schedule(curTick + latency); 481} 482 483 484//////////////////////////////////////////////////////////////////////// 485// 486// AtomicSimpleCPU Simulation Object 487// 488BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 489 490 Param<Counter> max_insts_any_thread; 491 Param<Counter> max_insts_all_threads; 492 Param<Counter> max_loads_any_thread; 493 Param<Counter> max_loads_all_threads; 494 Param<Tick> progress_interval; 495 SimObjectParam<MemObject *> mem; 496 SimObjectParam<System *> system; 497 Param<int> cpu_id; 498 499#if FULL_SYSTEM 500 SimObjectParam<AlphaITB *> itb; 501 SimObjectParam<AlphaDTB *> dtb; 502 Param<Tick> profile; 503#else 504 SimObjectParam<Process *> workload; 505#endif // FULL_SYSTEM 506 507 Param<int> clock; 508 509 Param<bool> defer_registration; 510 Param<int> width; 511 Param<bool> function_trace; 512 Param<Tick> function_trace_start; 513 Param<bool> simulate_stalls; 514 515END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 516 517BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 518 519 INIT_PARAM(max_insts_any_thread, 520 "terminate when any thread reaches this inst count"), 521 INIT_PARAM(max_insts_all_threads, 522 "terminate when all threads have reached this inst count"), 523 INIT_PARAM(max_loads_any_thread, 524 "terminate when any thread reaches this load count"), 525 INIT_PARAM(max_loads_all_threads, 526 "terminate when all threads have reached this load count"), 527 INIT_PARAM(progress_interval, "Progress interval"), 528 INIT_PARAM(mem, "memory"), 529 INIT_PARAM(system, "system object"), 530 INIT_PARAM(cpu_id, "processor ID"), 531 532#if FULL_SYSTEM 533 INIT_PARAM(itb, "Instruction TLB"), 534 INIT_PARAM(dtb, "Data TLB"), 535 INIT_PARAM(profile, ""), 536#else 537 INIT_PARAM(workload, "processes to run"), 538#endif // FULL_SYSTEM 539 540 INIT_PARAM(clock, "clock speed"), 541 INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 542 INIT_PARAM(width, "cpu width"), 543 INIT_PARAM(function_trace, "Enable function trace"), 544 INIT_PARAM(function_trace_start, "Cycle to start function trace"), 545 INIT_PARAM(simulate_stalls, "Simulate cache stall cycles") 546 547END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 548 549 550CREATE_SIM_OBJECT(AtomicSimpleCPU) 551{ 552 AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params(); 553 params->name = getInstanceName(); 554 params->numberOfThreads = 1; 555 params->max_insts_any_thread = max_insts_any_thread; 556 params->max_insts_all_threads = max_insts_all_threads; 557 params->max_loads_any_thread = max_loads_any_thread; 558 params->max_loads_all_threads = max_loads_all_threads; 559 params->progress_interval = progress_interval; 560 params->deferRegistration = defer_registration; 561 params->clock = clock; 562 params->functionTrace = function_trace; 563 params->functionTraceStart = function_trace_start; 564 params->width = width; 565 params->simulate_stalls = simulate_stalls; 566 params->mem = mem; 567 params->system = system; 568 params->cpu_id = cpu_id; 569 570#if FULL_SYSTEM 571 params->itb = itb; 572 params->dtb = dtb; 573 params->profile = profile; 574#else 575 params->process = workload; 576#endif 577 578 AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params); 579 return cpu; 580} 581 582REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU) 583 584