atomic.cc revision 2923:db8a876258df 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/utility.hh"
32#include "cpu/exetrace.hh"
33#include "cpu/simple/atomic.hh"
34#include "mem/packet_impl.hh"
35#include "sim/builder.hh"
36#include "sim/system.hh"
37
38using namespace std;
39using namespace TheISA;
40
41AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
42    : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
43{
44}
45
46
47void
48AtomicSimpleCPU::TickEvent::process()
49{
50    cpu->tick();
51}
52
53const char *
54AtomicSimpleCPU::TickEvent::description()
55{
56    return "AtomicSimpleCPU tick event";
57}
58
59Port *
60AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
61{
62    if (if_name == "dcache_port")
63        return &dcachePort;
64    else if (if_name == "icache_port")
65        return &icachePort;
66    else
67        panic("No Such Port\n");
68}
69
70void
71AtomicSimpleCPU::init()
72{
73    //Create Memory Ports (conect them up)
74//    Port *mem_dport = mem->getPort("");
75//    dcachePort.setPeer(mem_dport);
76//    mem_dport->setPeer(&dcachePort);
77
78//    Port *mem_iport = mem->getPort("");
79//    icachePort.setPeer(mem_iport);
80//    mem_iport->setPeer(&icachePort);
81
82    BaseCPU::init();
83#if FULL_SYSTEM
84    for (int i = 0; i < threadContexts.size(); ++i) {
85        ThreadContext *tc = threadContexts[i];
86
87        // initialize CPU, including PC
88        TheISA::initCPU(tc, tc->readCpuId());
89    }
90#endif
91}
92
93bool
94AtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt)
95{
96    panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
97    return true;
98}
99
100Tick
101AtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
102{
103    panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
104    return curTick;
105}
106
107void
108AtomicSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
109{
110    panic("AtomicSimpleCPU doesn't expect recvFunctional callback!");
111}
112
113void
114AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
115{
116    if (status == RangeChange)
117        return;
118
119    panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
120}
121
122void
123AtomicSimpleCPU::CpuPort::recvRetry()
124{
125    panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
126}
127
128
129AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
130    : BaseSimpleCPU(p), tickEvent(this),
131      width(p->width), simulate_stalls(p->simulate_stalls),
132      icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
133{
134    _status = Idle;
135
136    // @todo fix me and get the real cpu id & thread number!!!
137    ifetch_req = new Request();
138    ifetch_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
139    ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
140    ifetch_pkt->dataStatic(&inst);
141
142    data_read_req = new Request();
143    data_read_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
144    data_read_pkt = new Packet(data_read_req, Packet::ReadReq,
145                               Packet::Broadcast);
146    data_read_pkt->dataStatic(&dataReg);
147
148    data_write_req = new Request();
149    data_write_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
150    data_write_pkt = new Packet(data_write_req, Packet::WriteReq,
151                                Packet::Broadcast);
152}
153
154
155AtomicSimpleCPU::~AtomicSimpleCPU()
156{
157}
158
159void
160AtomicSimpleCPU::serialize(ostream &os)
161{
162    SimObject::State so_state = SimObject::getState();
163    SERIALIZE_ENUM(so_state);
164    nameOut(os, csprintf("%s.tickEvent", name()));
165    tickEvent.serialize(os);
166    BaseSimpleCPU::serialize(os);
167}
168
169void
170AtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
171{
172    SimObject::State so_state;
173    UNSERIALIZE_ENUM(so_state);
174    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
175    BaseSimpleCPU::unserialize(cp, section);
176}
177
178void
179AtomicSimpleCPU::resume()
180{
181    if (thread->status() == ThreadContext::Active) {
182        if (!tickEvent.scheduled())
183            tickEvent.schedule(curTick);
184    }
185}
186
187void
188AtomicSimpleCPU::resume()
189{
190    assert(system->getMemoryMode() == System::Atomic);
191    changeState(SimObject::Running);
192}
193
194void
195AtomicSimpleCPU::switchOut()
196{
197    assert(status() == Running || status() == Idle);
198    _status = SwitchedOut;
199
200    tickEvent.squash();
201}
202
203
204void
205AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
206{
207    BaseCPU::takeOverFrom(oldCPU);
208
209    assert(!tickEvent.scheduled());
210
211    // if any of this CPU's ThreadContexts are active, mark the CPU as
212    // running and schedule its tick event.
213    for (int i = 0; i < threadContexts.size(); ++i) {
214        ThreadContext *tc = threadContexts[i];
215        if (tc->status() == ThreadContext::Active && _status != Running) {
216            _status = Running;
217            tickEvent.schedule(curTick);
218            break;
219        }
220    }
221}
222
223
224void
225AtomicSimpleCPU::activateContext(int thread_num, int delay)
226{
227    assert(thread_num == 0);
228    assert(thread);
229
230    assert(_status == Idle);
231    assert(!tickEvent.scheduled());
232
233    notIdleFraction++;
234    tickEvent.schedule(curTick + cycles(delay));
235    _status = Running;
236}
237
238
239void
240AtomicSimpleCPU::suspendContext(int thread_num)
241{
242    assert(thread_num == 0);
243    assert(thread);
244
245    assert(_status == Running);
246
247    // tick event may not be scheduled if this gets called from inside
248    // an instruction's execution, e.g. "quiesce"
249    if (tickEvent.scheduled())
250        tickEvent.deschedule();
251
252    notIdleFraction--;
253    _status = Idle;
254}
255
256
257template <class T>
258Fault
259AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
260{
261    data_read_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
262
263    if (traceData) {
264        traceData->setAddr(addr);
265    }
266
267    // translate to physical address
268    Fault fault = thread->translateDataReadReq(data_read_req);
269
270    // Now do the access.
271    if (fault == NoFault) {
272        data_read_pkt->reinitFromRequest();
273
274        dcache_latency = dcachePort.sendAtomic(data_read_pkt);
275        dcache_access = true;
276
277        assert(data_read_pkt->result == Packet::Success);
278        data = data_read_pkt->get<T>();
279
280    }
281
282    // This will need a new way to tell if it has a dcache attached.
283    if (data_read_req->getFlags() & UNCACHEABLE)
284        recordEvent("Uncached Read");
285
286    return fault;
287}
288
289#ifndef DOXYGEN_SHOULD_SKIP_THIS
290
291template
292Fault
293AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
294
295template
296Fault
297AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
298
299template
300Fault
301AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
302
303template
304Fault
305AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
306
307#endif //DOXYGEN_SHOULD_SKIP_THIS
308
309template<>
310Fault
311AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
312{
313    return read(addr, *(uint64_t*)&data, flags);
314}
315
316template<>
317Fault
318AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
319{
320    return read(addr, *(uint32_t*)&data, flags);
321}
322
323
324template<>
325Fault
326AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
327{
328    return read(addr, (uint32_t&)data, flags);
329}
330
331
332template <class T>
333Fault
334AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
335{
336    data_write_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
337
338    if (traceData) {
339        traceData->setAddr(addr);
340    }
341
342    // translate to physical address
343    Fault fault = thread->translateDataWriteReq(data_write_req);
344
345    // Now do the access.
346    if (fault == NoFault) {
347        data = htog(data);
348        data_write_pkt->reinitFromRequest();
349        data_write_pkt->dataStatic(&data);
350
351        dcache_latency = dcachePort.sendAtomic(data_write_pkt);
352        dcache_access = true;
353
354        assert(data_write_pkt->result == Packet::Success);
355
356        if (res && data_write_req->getFlags() & LOCKED) {
357            *res = data_write_req->getScResult();
358        }
359    }
360
361    // This will need a new way to tell if it's hooked up to a cache or not.
362    if (data_write_req->getFlags() & UNCACHEABLE)
363        recordEvent("Uncached Write");
364
365    // If the write needs to have a fault on the access, consider calling
366    // changeStatus() and changing it to "bad addr write" or something.
367    return fault;
368}
369
370
371#ifndef DOXYGEN_SHOULD_SKIP_THIS
372template
373Fault
374AtomicSimpleCPU::write(uint64_t data, Addr addr,
375                       unsigned flags, uint64_t *res);
376
377template
378Fault
379AtomicSimpleCPU::write(uint32_t data, Addr addr,
380                       unsigned flags, uint64_t *res);
381
382template
383Fault
384AtomicSimpleCPU::write(uint16_t data, Addr addr,
385                       unsigned flags, uint64_t *res);
386
387template
388Fault
389AtomicSimpleCPU::write(uint8_t data, Addr addr,
390                       unsigned flags, uint64_t *res);
391
392#endif //DOXYGEN_SHOULD_SKIP_THIS
393
394template<>
395Fault
396AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
397{
398    return write(*(uint64_t*)&data, addr, flags, res);
399}
400
401template<>
402Fault
403AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
404{
405    return write(*(uint32_t*)&data, addr, flags, res);
406}
407
408
409template<>
410Fault
411AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
412{
413    return write((uint32_t)data, addr, flags, res);
414}
415
416
417void
418AtomicSimpleCPU::tick()
419{
420    Tick latency = cycles(1); // instruction takes one cycle by default
421
422    for (int i = 0; i < width; ++i) {
423        numCycles++;
424
425        checkForInterrupts();
426
427        Fault fault = setupFetchRequest(ifetch_req);
428
429        if (fault == NoFault) {
430            ifetch_pkt->reinitFromRequest();
431
432            Tick icache_latency = icachePort.sendAtomic(ifetch_pkt);
433            // ifetch_req is initialized to read the instruction directly
434            // into the CPU object's inst field.
435
436            dcache_access = false; // assume no dcache access
437            preExecute();
438            fault = curStaticInst->execute(this, traceData);
439            postExecute();
440
441            if (simulate_stalls) {
442                Tick icache_stall = icache_latency - cycles(1);
443                Tick dcache_stall =
444                    dcache_access ? dcache_latency - cycles(1) : 0;
445                Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
446                if (cycles(stall_cycles) < (icache_stall + dcache_stall))
447                    latency += cycles(stall_cycles+1);
448                else
449                    latency += cycles(stall_cycles);
450            }
451
452        }
453
454        advancePC(fault);
455    }
456
457    if (_status != Idle)
458        tickEvent.schedule(curTick + latency);
459}
460
461
462////////////////////////////////////////////////////////////////////////
463//
464//  AtomicSimpleCPU Simulation Object
465//
466BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
467
468    Param<Counter> max_insts_any_thread;
469    Param<Counter> max_insts_all_threads;
470    Param<Counter> max_loads_any_thread;
471    Param<Counter> max_loads_all_threads;
472    SimObjectParam<MemObject *> mem;
473    SimObjectParam<System *> system;
474
475#if FULL_SYSTEM
476    SimObjectParam<AlphaITB *> itb;
477    SimObjectParam<AlphaDTB *> dtb;
478    Param<int> cpu_id;
479    Param<Tick> profile;
480#else
481    SimObjectParam<Process *> workload;
482#endif // FULL_SYSTEM
483
484    Param<int> clock;
485
486    Param<bool> defer_registration;
487    Param<int> width;
488    Param<bool> function_trace;
489    Param<Tick> function_trace_start;
490    Param<bool> simulate_stalls;
491
492END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
493
494BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
495
496    INIT_PARAM(max_insts_any_thread,
497               "terminate when any thread reaches this inst count"),
498    INIT_PARAM(max_insts_all_threads,
499               "terminate when all threads have reached this inst count"),
500    INIT_PARAM(max_loads_any_thread,
501               "terminate when any thread reaches this load count"),
502    INIT_PARAM(max_loads_all_threads,
503               "terminate when all threads have reached this load count"),
504    INIT_PARAM(mem, "memory"),
505    INIT_PARAM(system, "system object"),
506
507#if FULL_SYSTEM
508    INIT_PARAM(itb, "Instruction TLB"),
509    INIT_PARAM(dtb, "Data TLB"),
510    INIT_PARAM(cpu_id, "processor ID"),
511    INIT_PARAM(profile, ""),
512#else
513    INIT_PARAM(workload, "processes to run"),
514#endif // FULL_SYSTEM
515
516    INIT_PARAM(clock, "clock speed"),
517    INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
518    INIT_PARAM(width, "cpu width"),
519    INIT_PARAM(function_trace, "Enable function trace"),
520    INIT_PARAM(function_trace_start, "Cycle to start function trace"),
521    INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
522
523END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
524
525
526CREATE_SIM_OBJECT(AtomicSimpleCPU)
527{
528    AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
529    params->name = getInstanceName();
530    params->numberOfThreads = 1;
531    params->max_insts_any_thread = max_insts_any_thread;
532    params->max_insts_all_threads = max_insts_all_threads;
533    params->max_loads_any_thread = max_loads_any_thread;
534    params->max_loads_all_threads = max_loads_all_threads;
535    params->deferRegistration = defer_registration;
536    params->clock = clock;
537    params->functionTrace = function_trace;
538    params->functionTraceStart = function_trace_start;
539    params->width = width;
540    params->simulate_stalls = simulate_stalls;
541    params->mem = mem;
542    params->system = system;
543
544#if FULL_SYSTEM
545    params->itb = itb;
546    params->dtb = dtb;
547    params->cpu_id = cpu_id;
548    params->profile = profile;
549#else
550    params->process = workload;
551#endif
552
553    AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
554    return cpu;
555}
556
557REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU)
558
559