atomic.cc revision 2798:751e9170247e
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 */ 30 31#include "arch/utility.hh" 32#include "cpu/exetrace.hh" 33#include "cpu/simple/atomic.hh" 34#include "mem/packet_impl.hh" 35#include "sim/builder.hh" 36 37using namespace std; 38using namespace TheISA; 39 40AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 41 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) 42{ 43} 44 45 46void 47AtomicSimpleCPU::TickEvent::process() 48{ 49 cpu->tick(); 50} 51 52const char * 53AtomicSimpleCPU::TickEvent::description() 54{ 55 return "AtomicSimpleCPU tick event"; 56} 57 58 59void 60AtomicSimpleCPU::init() 61{ 62 //Create Memory Ports (conect them up) 63 Port *mem_dport = mem->getPort(""); 64 dcachePort.setPeer(mem_dport); 65 mem_dport->setPeer(&dcachePort); 66 67 Port *mem_iport = mem->getPort(""); 68 icachePort.setPeer(mem_iport); 69 mem_iport->setPeer(&icachePort); 70 71 BaseCPU::init(); 72#if FULL_SYSTEM 73 for (int i = 0; i < threadContexts.size(); ++i) { 74 ThreadContext *tc = threadContexts[i]; 75 76 // initialize CPU, including PC 77 TheISA::initCPU(tc, tc->readCpuId()); 78 } 79#endif 80} 81 82bool 83AtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt) 84{ 85 panic("AtomicSimpleCPU doesn't expect recvAtomic callback!"); 86 return true; 87} 88 89Tick 90AtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt) 91{ 92 panic("AtomicSimpleCPU doesn't expect recvAtomic callback!"); 93 return curTick; 94} 95 96void 97AtomicSimpleCPU::CpuPort::recvFunctional(Packet *pkt) 98{ 99 panic("AtomicSimpleCPU doesn't expect recvFunctional callback!"); 100} 101 102void 103AtomicSimpleCPU::CpuPort::recvStatusChange(Status status) 104{ 105 if (status == RangeChange) 106 return; 107 108 panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!"); 109} 110 111void 112AtomicSimpleCPU::CpuPort::recvRetry() 113{ 114 panic("AtomicSimpleCPU doesn't expect recvRetry callback!"); 115} 116 117 118AtomicSimpleCPU::AtomicSimpleCPU(Params *p) 119 : BaseSimpleCPU(p), tickEvent(this), 120 width(p->width), simulate_stalls(p->simulate_stalls), 121 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this) 122{ 123 _status = Idle; 124 125 // @todo fix me and get the real cpu id & thread number!!! 126 ifetch_req = new Request(); 127 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast); 128 ifetch_pkt->dataStatic(&inst); 129 130 data_read_req = new Request(); 131 data_read_pkt = new Packet(data_read_req, Packet::ReadReq, 132 Packet::Broadcast); 133 data_read_pkt->dataStatic(&dataReg); 134 135 data_write_req = new Request(); 136 data_write_pkt = new Packet(data_write_req, Packet::WriteReq, 137 Packet::Broadcast); 138} 139 140 141AtomicSimpleCPU::~AtomicSimpleCPU() 142{ 143} 144 145void 146AtomicSimpleCPU::serialize(ostream &os) 147{ 148 SERIALIZE_ENUM(_status); 149 BaseSimpleCPU::serialize(os); 150 nameOut(os, csprintf("%s.tickEvent", name())); 151 tickEvent.serialize(os); 152} 153 154void 155AtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 156{ 157 UNSERIALIZE_ENUM(_status); 158 BaseSimpleCPU::unserialize(cp, section); 159 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 160} 161 162void 163AtomicSimpleCPU::switchOut() 164{ 165 assert(status() == Running || status() == Idle); 166 _status = SwitchedOut; 167 168 tickEvent.squash(); 169} 170 171 172void 173AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 174{ 175 BaseCPU::takeOverFrom(oldCPU); 176 177 assert(!tickEvent.scheduled()); 178 179 // if any of this CPU's ThreadContexts are active, mark the CPU as 180 // running and schedule its tick event. 181 for (int i = 0; i < threadContexts.size(); ++i) { 182 ThreadContext *tc = threadContexts[i]; 183 if (tc->status() == ThreadContext::Active && _status != Running) { 184 _status = Running; 185 tickEvent.schedule(curTick); 186 break; 187 } 188 } 189} 190 191 192void 193AtomicSimpleCPU::activateContext(int thread_num, int delay) 194{ 195 assert(thread_num == 0); 196 assert(thread); 197 198 assert(_status == Idle); 199 assert(!tickEvent.scheduled()); 200 201 notIdleFraction++; 202 tickEvent.schedule(curTick + cycles(delay)); 203 _status = Running; 204} 205 206 207void 208AtomicSimpleCPU::suspendContext(int thread_num) 209{ 210 assert(thread_num == 0); 211 assert(thread); 212 213 assert(_status == Running); 214 215 // tick event may not be scheduled if this gets called from inside 216 // an instruction's execution, e.g. "quiesce" 217 if (tickEvent.scheduled()) 218 tickEvent.deschedule(); 219 220 notIdleFraction--; 221 _status = Idle; 222} 223 224 225template <class T> 226Fault 227AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) 228{ 229 data_read_req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 230 231 if (traceData) { 232 traceData->setAddr(addr); 233 } 234 235 // translate to physical address 236 Fault fault = thread->translateDataReadReq(data_read_req); 237 238 // Now do the access. 239 if (fault == NoFault) { 240 data_read_pkt->reinitFromRequest(); 241 242 dcache_latency = dcachePort.sendAtomic(data_read_pkt); 243 dcache_access = true; 244 245 assert(data_read_pkt->result == Packet::Success); 246 data = data_read_pkt->get<T>(); 247 248 } 249 250 // This will need a new way to tell if it has a dcache attached. 251 if (data_read_req->getFlags() & UNCACHEABLE) 252 recordEvent("Uncached Read"); 253 254 return fault; 255} 256 257#ifndef DOXYGEN_SHOULD_SKIP_THIS 258 259template 260Fault 261AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 262 263template 264Fault 265AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 266 267template 268Fault 269AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 270 271template 272Fault 273AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 274 275#endif //DOXYGEN_SHOULD_SKIP_THIS 276 277template<> 278Fault 279AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags) 280{ 281 return read(addr, *(uint64_t*)&data, flags); 282} 283 284template<> 285Fault 286AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags) 287{ 288 return read(addr, *(uint32_t*)&data, flags); 289} 290 291 292template<> 293Fault 294AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 295{ 296 return read(addr, (uint32_t&)data, flags); 297} 298 299 300template <class T> 301Fault 302AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 303{ 304 data_write_req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 305 306 if (traceData) { 307 traceData->setAddr(addr); 308 } 309 310 // translate to physical address 311 Fault fault = thread->translateDataWriteReq(data_write_req); 312 313 // Now do the access. 314 if (fault == NoFault) { 315 data = htog(data); 316 data_write_pkt->reinitFromRequest(); 317 data_write_pkt->dataStatic(&data); 318 319 dcache_latency = dcachePort.sendAtomic(data_write_pkt); 320 dcache_access = true; 321 322 assert(data_write_pkt->result == Packet::Success); 323 324 if (res && data_write_req->getFlags() & LOCKED) { 325 *res = data_write_req->getScResult(); 326 } 327 } 328 329 // This will need a new way to tell if it's hooked up to a cache or not. 330 if (data_write_req->getFlags() & UNCACHEABLE) 331 recordEvent("Uncached Write"); 332 333 // If the write needs to have a fault on the access, consider calling 334 // changeStatus() and changing it to "bad addr write" or something. 335 return fault; 336} 337 338 339#ifndef DOXYGEN_SHOULD_SKIP_THIS 340template 341Fault 342AtomicSimpleCPU::write(uint64_t data, Addr addr, 343 unsigned flags, uint64_t *res); 344 345template 346Fault 347AtomicSimpleCPU::write(uint32_t data, Addr addr, 348 unsigned flags, uint64_t *res); 349 350template 351Fault 352AtomicSimpleCPU::write(uint16_t data, Addr addr, 353 unsigned flags, uint64_t *res); 354 355template 356Fault 357AtomicSimpleCPU::write(uint8_t data, Addr addr, 358 unsigned flags, uint64_t *res); 359 360#endif //DOXYGEN_SHOULD_SKIP_THIS 361 362template<> 363Fault 364AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 365{ 366 return write(*(uint64_t*)&data, addr, flags, res); 367} 368 369template<> 370Fault 371AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 372{ 373 return write(*(uint32_t*)&data, addr, flags, res); 374} 375 376 377template<> 378Fault 379AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 380{ 381 return write((uint32_t)data, addr, flags, res); 382} 383 384 385void 386AtomicSimpleCPU::tick() 387{ 388 Tick latency = cycles(1); // instruction takes one cycle by default 389 390 for (int i = 0; i < width; ++i) { 391 numCycles++; 392 393 checkForInterrupts(); 394 395 Fault fault = setupFetchRequest(ifetch_req); 396 397 if (fault == NoFault) { 398 ifetch_pkt->reinitFromRequest(); 399 400 Tick icache_latency = icachePort.sendAtomic(ifetch_pkt); 401 // ifetch_req is initialized to read the instruction directly 402 // into the CPU object's inst field. 403 404 dcache_access = false; // assume no dcache access 405 preExecute(); 406 fault = curStaticInst->execute(this, traceData); 407 postExecute(); 408 409 if (simulate_stalls) { 410 // This calculation assumes that the icache and dcache 411 // access latencies are always a multiple of the CPU's 412 // cycle time. If not, the next tick event may get 413 // scheduled at a non-integer multiple of the CPU 414 // cycle time. 415 Tick icache_stall = icache_latency - cycles(1); 416 Tick dcache_stall = 417 dcache_access ? dcache_latency - cycles(1) : 0; 418 latency += icache_stall + dcache_stall; 419 } 420 421 } 422 423 advancePC(fault); 424 } 425 426 if (_status != Idle) 427 tickEvent.schedule(curTick + latency); 428} 429 430 431//////////////////////////////////////////////////////////////////////// 432// 433// AtomicSimpleCPU Simulation Object 434// 435BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 436 437 Param<Counter> max_insts_any_thread; 438 Param<Counter> max_insts_all_threads; 439 Param<Counter> max_loads_any_thread; 440 Param<Counter> max_loads_all_threads; 441 SimObjectParam<MemObject *> mem; 442 443#if FULL_SYSTEM 444 SimObjectParam<AlphaITB *> itb; 445 SimObjectParam<AlphaDTB *> dtb; 446 SimObjectParam<System *> system; 447 Param<int> cpu_id; 448 Param<Tick> profile; 449#else 450 SimObjectParam<Process *> workload; 451#endif // FULL_SYSTEM 452 453 Param<int> clock; 454 455 Param<bool> defer_registration; 456 Param<int> width; 457 Param<bool> function_trace; 458 Param<Tick> function_trace_start; 459 Param<bool> simulate_stalls; 460 461END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 462 463BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 464 465 INIT_PARAM(max_insts_any_thread, 466 "terminate when any thread reaches this inst count"), 467 INIT_PARAM(max_insts_all_threads, 468 "terminate when all threads have reached this inst count"), 469 INIT_PARAM(max_loads_any_thread, 470 "terminate when any thread reaches this load count"), 471 INIT_PARAM(max_loads_all_threads, 472 "terminate when all threads have reached this load count"), 473 INIT_PARAM(mem, "memory"), 474 475#if FULL_SYSTEM 476 INIT_PARAM(itb, "Instruction TLB"), 477 INIT_PARAM(dtb, "Data TLB"), 478 INIT_PARAM(system, "system object"), 479 INIT_PARAM(cpu_id, "processor ID"), 480 INIT_PARAM(profile, ""), 481#else 482 INIT_PARAM(workload, "processes to run"), 483#endif // FULL_SYSTEM 484 485 INIT_PARAM(clock, "clock speed"), 486 INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 487 INIT_PARAM(width, "cpu width"), 488 INIT_PARAM(function_trace, "Enable function trace"), 489 INIT_PARAM(function_trace_start, "Cycle to start function trace"), 490 INIT_PARAM(simulate_stalls, "Simulate cache stall cycles") 491 492END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU) 493 494 495CREATE_SIM_OBJECT(AtomicSimpleCPU) 496{ 497 AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params(); 498 params->name = getInstanceName(); 499 params->numberOfThreads = 1; 500 params->max_insts_any_thread = max_insts_any_thread; 501 params->max_insts_all_threads = max_insts_all_threads; 502 params->max_loads_any_thread = max_loads_any_thread; 503 params->max_loads_all_threads = max_loads_all_threads; 504 params->deferRegistration = defer_registration; 505 params->clock = clock; 506 params->functionTrace = function_trace; 507 params->functionTraceStart = function_trace_start; 508 params->width = width; 509 params->simulate_stalls = simulate_stalls; 510 params->mem = mem; 511 512#if FULL_SYSTEM 513 params->itb = itb; 514 params->dtb = dtb; 515 params->system = system; 516 params->cpu_id = cpu_id; 517 params->profile = profile; 518#else 519 params->process = workload; 520#endif 521 522 AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params); 523 return cpu; 524} 525 526REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU) 527 528