atomic.cc revision 11151
1/*
2 * Copyright 2014 Google, Inc.
3 * Copyright (c) 2012-2013,2015 ARM Limited
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2002-2005 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 */
43
44#include "arch/locked_mem.hh"
45#include "arch/mmapped_ipr.hh"
46#include "arch/utility.hh"
47#include "base/bigint.hh"
48#include "base/output.hh"
49#include "config/the_isa.hh"
50#include "cpu/simple/atomic.hh"
51#include "cpu/exetrace.hh"
52#include "debug/Drain.hh"
53#include "debug/ExecFaulting.hh"
54#include "debug/SimpleCPU.hh"
55#include "mem/packet.hh"
56#include "mem/packet_access.hh"
57#include "mem/physical.hh"
58#include "params/AtomicSimpleCPU.hh"
59#include "sim/faults.hh"
60#include "sim/system.hh"
61#include "sim/full_system.hh"
62
63using namespace std;
64using namespace TheISA;
65
66AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
67    : Event(CPU_Tick_Pri), cpu(c)
68{
69}
70
71
72void
73AtomicSimpleCPU::TickEvent::process()
74{
75    cpu->tick();
76}
77
78const char *
79AtomicSimpleCPU::TickEvent::description() const
80{
81    return "AtomicSimpleCPU tick";
82}
83
84void
85AtomicSimpleCPU::init()
86{
87    BaseSimpleCPU::init();
88
89    int cid = threadContexts[0]->contextId();
90    ifetch_req.setThreadContext(cid, 0);
91    data_read_req.setThreadContext(cid, 0);
92    data_write_req.setThreadContext(cid, 0);
93}
94
95AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
96    : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false),
97      simulate_data_stalls(p->simulate_data_stalls),
98      simulate_inst_stalls(p->simulate_inst_stalls),
99      icachePort(name() + ".icache_port", this),
100      dcachePort(name() + ".dcache_port", this),
101      fastmem(p->fastmem), dcache_access(false), dcache_latency(0),
102      ppCommit(nullptr)
103{
104    _status = Idle;
105}
106
107
108AtomicSimpleCPU::~AtomicSimpleCPU()
109{
110    if (tickEvent.scheduled()) {
111        deschedule(tickEvent);
112    }
113}
114
115DrainState
116AtomicSimpleCPU::drain()
117{
118    if (switchedOut())
119        return DrainState::Drained;
120
121    if (!isDrained()) {
122        DPRINTF(Drain, "Requesting drain.\n");
123        return DrainState::Draining;
124    } else {
125        if (tickEvent.scheduled())
126            deschedule(tickEvent);
127
128        activeThreads.clear();
129        DPRINTF(Drain, "Not executing microcode, no need to drain.\n");
130        return DrainState::Drained;
131    }
132}
133
134void
135AtomicSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender)
136{
137    DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(),
138            pkt->cmdString());
139
140    for (ThreadID tid = 0; tid < numThreads; tid++) {
141        if (tid != sender) {
142            if(getCpuAddrMonitor(tid)->doMonitor(pkt)) {
143                wakeup(tid);
144            }
145
146            TheISA::handleLockedSnoop(threadInfo[tid]->thread,
147                                      pkt, dcachePort.cacheBlockMask);
148        }
149    }
150}
151
152void
153AtomicSimpleCPU::drainResume()
154{
155    assert(!tickEvent.scheduled());
156    if (switchedOut())
157        return;
158
159    DPRINTF(SimpleCPU, "Resume\n");
160    verifyMemoryMode();
161
162    assert(!threadContexts.empty());
163
164    _status = BaseSimpleCPU::Idle;
165
166    for (ThreadID tid = 0; tid < numThreads; tid++) {
167        if (threadInfo[tid]->thread->status() == ThreadContext::Active) {
168            threadInfo[tid]->notIdleFraction = 1;
169            activeThreads.push_back(tid);
170            _status = BaseSimpleCPU::Running;
171
172            // Tick if any threads active
173            if (!tickEvent.scheduled()) {
174                schedule(tickEvent, nextCycle());
175            }
176        } else {
177            threadInfo[tid]->notIdleFraction = 0;
178        }
179    }
180}
181
182bool
183AtomicSimpleCPU::tryCompleteDrain()
184{
185    if (drainState() != DrainState::Draining)
186        return false;
187
188    DPRINTF(Drain, "tryCompleteDrain.\n");
189    if (!isDrained())
190        return false;
191
192    DPRINTF(Drain, "CPU done draining, processing drain event\n");
193    signalDrainDone();
194
195    return true;
196}
197
198
199void
200AtomicSimpleCPU::switchOut()
201{
202    BaseSimpleCPU::switchOut();
203
204    assert(!tickEvent.scheduled());
205    assert(_status == BaseSimpleCPU::Running || _status == Idle);
206    assert(isDrained());
207}
208
209
210void
211AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
212{
213    BaseSimpleCPU::takeOverFrom(oldCPU);
214
215    // The tick event should have been descheduled by drain()
216    assert(!tickEvent.scheduled());
217}
218
219void
220AtomicSimpleCPU::verifyMemoryMode() const
221{
222    if (!system->isAtomicMode()) {
223        fatal("The atomic CPU requires the memory system to be in "
224              "'atomic' mode.\n");
225    }
226}
227
228void
229AtomicSimpleCPU::activateContext(ThreadID thread_num)
230{
231    DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num);
232
233    assert(thread_num < numThreads);
234
235    threadInfo[thread_num]->notIdleFraction = 1;
236    Cycles delta = ticksToCycles(threadInfo[thread_num]->thread->lastActivate -
237                                 threadInfo[thread_num]->thread->lastSuspend);
238    numCycles += delta;
239    ppCycles->notify(delta);
240
241    if (!tickEvent.scheduled()) {
242        //Make sure ticks are still on multiples of cycles
243        schedule(tickEvent, clockEdge(Cycles(0)));
244    }
245    _status = BaseSimpleCPU::Running;
246    if (std::find(activeThreads.begin(), activeThreads.end(), thread_num)
247        == activeThreads.end()) {
248        activeThreads.push_back(thread_num);
249    }
250}
251
252
253void
254AtomicSimpleCPU::suspendContext(ThreadID thread_num)
255{
256    DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
257
258    assert(thread_num < numThreads);
259    activeThreads.remove(thread_num);
260
261    if (_status == Idle)
262        return;
263
264    assert(_status == BaseSimpleCPU::Running);
265
266    threadInfo[thread_num]->notIdleFraction = 0;
267
268    if (activeThreads.empty()) {
269        _status = Idle;
270
271        if (tickEvent.scheduled()) {
272            deschedule(tickEvent);
273        }
274    }
275
276}
277
278
279Tick
280AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt)
281{
282    DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(),
283            pkt->cmdString());
284
285    // X86 ISA: Snooping an invalidation for monitor/mwait
286    AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner);
287
288    for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
289        if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
290            cpu->wakeup(tid);
291        }
292    }
293
294    // if snoop invalidates, release any associated locks
295    if (pkt->isInvalidate()) {
296        DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n",
297                pkt->getAddr());
298        for (auto &t_info : cpu->threadInfo) {
299            TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask);
300        }
301    }
302
303    return 0;
304}
305
306void
307AtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt)
308{
309    DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(),
310            pkt->cmdString());
311
312    // X86 ISA: Snooping an invalidation for monitor/mwait
313    AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner);
314    for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
315        if(cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
316            cpu->wakeup(tid);
317        }
318    }
319
320    // if snoop invalidates, release any associated locks
321    if (pkt->isInvalidate()) {
322        DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n",
323                pkt->getAddr());
324        for (auto &t_info : cpu->threadInfo) {
325            TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask);
326        }
327    }
328}
329
330Fault
331AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
332                         unsigned size, unsigned flags)
333{
334    SimpleExecContext& t_info = *threadInfo[curThread];
335    SimpleThread* thread = t_info.thread;
336
337    // use the CPU's statically allocated read request and packet objects
338    Request *req = &data_read_req;
339
340    if (traceData)
341        traceData->setMem(addr, size, flags);
342
343    //The size of the data we're trying to read.
344    int fullSize = size;
345
346    //The address of the second part of this access if it needs to be split
347    //across a cache line boundary.
348    Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
349
350    if (secondAddr > addr)
351        size = secondAddr - addr;
352
353    dcache_latency = 0;
354
355    req->taskId(taskId());
356    while (1) {
357        req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr());
358
359        // translate to physical address
360        Fault fault = thread->dtb->translateAtomic(req, thread->getTC(),
361                                                          BaseTLB::Read);
362
363        // Now do the access.
364        if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
365            Packet pkt(req, Packet::makeReadCmd(req));
366            pkt.dataStatic(data);
367
368            if (req->isMmappedIpr())
369                dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
370            else {
371                if (fastmem && system->isMemAddr(pkt.getAddr()))
372                    system->getPhysMem().access(&pkt);
373                else
374                    dcache_latency += dcachePort.sendAtomic(&pkt);
375            }
376            dcache_access = true;
377
378            assert(!pkt.isError());
379
380            if (req->isLLSC()) {
381                TheISA::handleLockedRead(thread, req);
382            }
383        }
384
385        //If there's a fault, return it
386        if (fault != NoFault) {
387            if (req->isPrefetch()) {
388                return NoFault;
389            } else {
390                return fault;
391            }
392        }
393
394        //If we don't need to access a second cache line, stop now.
395        if (secondAddr <= addr)
396        {
397            if (req->isLockedRMW() && fault == NoFault) {
398                assert(!locked);
399                locked = true;
400            }
401
402            return fault;
403        }
404
405        /*
406         * Set up for accessing the second cache line.
407         */
408
409        //Move the pointer we're reading into to the correct location.
410        data += size;
411        //Adjust the size to get the remaining bytes.
412        size = addr + fullSize - secondAddr;
413        //And access the right address.
414        addr = secondAddr;
415    }
416}
417
418
419Fault
420AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size,
421                          Addr addr, unsigned flags, uint64_t *res)
422{
423    SimpleExecContext& t_info = *threadInfo[curThread];
424    SimpleThread* thread = t_info.thread;
425    static uint8_t zero_array[64] = {};
426
427    if (data == NULL) {
428        assert(size <= 64);
429        assert(flags & Request::CACHE_BLOCK_ZERO);
430        // This must be a cache block cleaning request
431        data = zero_array;
432    }
433
434    // use the CPU's statically allocated write request and packet objects
435    Request *req = &data_write_req;
436
437    if (traceData)
438        traceData->setMem(addr, size, flags);
439
440    //The size of the data we're trying to read.
441    int fullSize = size;
442
443    //The address of the second part of this access if it needs to be split
444    //across a cache line boundary.
445    Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
446
447    if(secondAddr > addr)
448        size = secondAddr - addr;
449
450    dcache_latency = 0;
451
452    req->taskId(taskId());
453    while(1) {
454        req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr());
455
456        // translate to physical address
457        Fault fault = thread->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Write);
458
459        // Now do the access.
460        if (fault == NoFault) {
461            MemCmd cmd = MemCmd::WriteReq; // default
462            bool do_access = true;  // flag to suppress cache access
463
464            if (req->isLLSC()) {
465                cmd = MemCmd::StoreCondReq;
466                do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask);
467            } else if (req->isSwap()) {
468                cmd = MemCmd::SwapReq;
469                if (req->isCondSwap()) {
470                    assert(res);
471                    req->setExtraData(*res);
472                }
473            }
474
475            if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) {
476                Packet pkt = Packet(req, cmd);
477                pkt.dataStatic(data);
478
479                if (req->isMmappedIpr()) {
480                    dcache_latency +=
481                        TheISA::handleIprWrite(thread->getTC(), &pkt);
482                } else {
483                    if (fastmem && system->isMemAddr(pkt.getAddr()))
484                        system->getPhysMem().access(&pkt);
485                    else
486                        dcache_latency += dcachePort.sendAtomic(&pkt);
487
488                    // Notify other threads on this CPU of write
489                    threadSnoop(&pkt, curThread);
490                }
491                dcache_access = true;
492                assert(!pkt.isError());
493
494                if (req->isSwap()) {
495                    assert(res);
496                    memcpy(res, pkt.getConstPtr<uint8_t>(), fullSize);
497                }
498            }
499
500            if (res && !req->isSwap()) {
501                *res = req->getExtraData();
502            }
503        }
504
505        //If there's a fault or we don't need to access a second cache line,
506        //stop now.
507        if (fault != NoFault || secondAddr <= addr)
508        {
509            if (req->isLockedRMW() && fault == NoFault) {
510                assert(locked);
511                locked = false;
512            }
513
514
515            if (fault != NoFault && req->isPrefetch()) {
516                return NoFault;
517            } else {
518                return fault;
519            }
520        }
521
522        /*
523         * Set up for accessing the second cache line.
524         */
525
526        //Move the pointer we're reading into to the correct location.
527        data += size;
528        //Adjust the size to get the remaining bytes.
529        size = addr + fullSize - secondAddr;
530        //And access the right address.
531        addr = secondAddr;
532    }
533}
534
535
536void
537AtomicSimpleCPU::tick()
538{
539    DPRINTF(SimpleCPU, "Tick\n");
540
541    // Change thread if multi-threaded
542    swapActiveThread();
543
544    // Set memroy request ids to current thread
545    if (numThreads > 1) {
546        ContextID cid = threadContexts[curThread]->contextId();
547
548        ifetch_req.setThreadContext(cid, curThread);
549        data_read_req.setThreadContext(cid, curThread);
550        data_write_req.setThreadContext(cid, curThread);
551    }
552
553    SimpleExecContext& t_info = *threadInfo[curThread];
554    SimpleThread* thread = t_info.thread;
555
556    Tick latency = 0;
557
558    for (int i = 0; i < width || locked; ++i) {
559        numCycles++;
560        ppCycles->notify(1);
561
562        if (!curStaticInst || !curStaticInst->isDelayedCommit()) {
563            checkForInterrupts();
564            checkPcEventQueue();
565        }
566
567        // We must have just got suspended by a PC event
568        if (_status == Idle) {
569            tryCompleteDrain();
570            return;
571        }
572
573        Fault fault = NoFault;
574
575        TheISA::PCState pcState = thread->pcState();
576
577        bool needToFetch = !isRomMicroPC(pcState.microPC()) &&
578                           !curMacroStaticInst;
579        if (needToFetch) {
580            ifetch_req.taskId(taskId());
581            setupFetchRequest(&ifetch_req);
582            fault = thread->itb->translateAtomic(&ifetch_req, thread->getTC(),
583                                                 BaseTLB::Execute);
584        }
585
586        if (fault == NoFault) {
587            Tick icache_latency = 0;
588            bool icache_access = false;
589            dcache_access = false; // assume no dcache access
590
591            if (needToFetch) {
592                // This is commented out because the decoder would act like
593                // a tiny cache otherwise. It wouldn't be flushed when needed
594                // like the I cache. It should be flushed, and when that works
595                // this code should be uncommented.
596                //Fetch more instruction memory if necessary
597                //if(decoder.needMoreBytes())
598                //{
599                    icache_access = true;
600                    Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq);
601                    ifetch_pkt.dataStatic(&inst);
602
603                    if (fastmem && system->isMemAddr(ifetch_pkt.getAddr()))
604                        system->getPhysMem().access(&ifetch_pkt);
605                    else
606                        icache_latency = icachePort.sendAtomic(&ifetch_pkt);
607
608                    assert(!ifetch_pkt.isError());
609
610                    // ifetch_req is initialized to read the instruction directly
611                    // into the CPU object's inst field.
612                //}
613            }
614
615            preExecute();
616
617            if (curStaticInst) {
618                fault = curStaticInst->execute(&t_info, traceData);
619
620                // keep an instruction count
621                if (fault == NoFault) {
622                    countInst();
623                    ppCommit->notify(std::make_pair(thread, curStaticInst));
624                }
625                else if (traceData && !DTRACE(ExecFaulting)) {
626                    delete traceData;
627                    traceData = NULL;
628                }
629
630                postExecute();
631            }
632
633            // @todo remove me after debugging with legion done
634            if (curStaticInst && (!curStaticInst->isMicroop() ||
635                        curStaticInst->isFirstMicroop()))
636                instCnt++;
637
638            Tick stall_ticks = 0;
639            if (simulate_inst_stalls && icache_access)
640                stall_ticks += icache_latency;
641
642            if (simulate_data_stalls && dcache_access)
643                stall_ticks += dcache_latency;
644
645            if (stall_ticks) {
646                // the atomic cpu does its accounting in ticks, so
647                // keep counting in ticks but round to the clock
648                // period
649                latency += divCeil(stall_ticks, clockPeriod()) *
650                    clockPeriod();
651            }
652
653        }
654        if(fault != NoFault || !t_info.stayAtPC)
655            advancePC(fault);
656    }
657
658    if (tryCompleteDrain())
659        return;
660
661    // instruction takes at least one cycle
662    if (latency < clockPeriod())
663        latency = clockPeriod();
664
665    if (_status != Idle)
666        reschedule(tickEvent, curTick() + latency, true);
667}
668
669void
670AtomicSimpleCPU::regProbePoints()
671{
672    BaseCPU::regProbePoints();
673
674    ppCommit = new ProbePointArg<pair<SimpleThread*, const StaticInstPtr>>
675                                (getProbeManager(), "Commit");
676}
677
678void
679AtomicSimpleCPU::printAddr(Addr a)
680{
681    dcachePort.printAddr(a);
682}
683
684////////////////////////////////////////////////////////////////////////
685//
686//  AtomicSimpleCPU Simulation Object
687//
688AtomicSimpleCPU *
689AtomicSimpleCPUParams::create()
690{
691    return new AtomicSimpleCPU(this);
692}
693