atomic.cc revision 10596
1/* 2 * Copyright 2014 Google, Inc. 3 * Copyright (c) 2012-2013 ARM Limited 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2002-2005 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 */ 43 44#include "arch/locked_mem.hh" 45#include "arch/mmapped_ipr.hh" 46#include "arch/utility.hh" 47#include "base/bigint.hh" 48#include "base/output.hh" 49#include "config/the_isa.hh" 50#include "cpu/simple/atomic.hh" 51#include "cpu/exetrace.hh" 52#include "debug/Drain.hh" 53#include "debug/ExecFaulting.hh" 54#include "debug/SimpleCPU.hh" 55#include "mem/packet.hh" 56#include "mem/packet_access.hh" 57#include "mem/physical.hh" 58#include "params/AtomicSimpleCPU.hh" 59#include "sim/faults.hh" 60#include "sim/system.hh" 61#include "sim/full_system.hh" 62 63using namespace std; 64using namespace TheISA; 65 66AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 67 : Event(CPU_Tick_Pri), cpu(c) 68{ 69} 70 71 72void 73AtomicSimpleCPU::TickEvent::process() 74{ 75 cpu->tick(); 76} 77 78const char * 79AtomicSimpleCPU::TickEvent::description() const 80{ 81 return "AtomicSimpleCPU tick"; 82} 83 84void 85AtomicSimpleCPU::init() 86{ 87 BaseCPU::init(); 88 89 // Initialise the ThreadContext's memory proxies 90 tcBase()->initMemProxies(tcBase()); 91 92 if (FullSystem && !params()->switched_out) { 93 ThreadID size = threadContexts.size(); 94 for (ThreadID i = 0; i < size; ++i) { 95 ThreadContext *tc = threadContexts[i]; 96 // initialize CPU, including PC 97 TheISA::initCPU(tc, tc->contextId()); 98 } 99 } 100 101 // Atomic doesn't do MT right now, so contextId == threadId 102 ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT 103 data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too 104 data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too 105} 106 107AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) 108 : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false), 109 simulate_data_stalls(p->simulate_data_stalls), 110 simulate_inst_stalls(p->simulate_inst_stalls), 111 drain_manager(NULL), 112 icachePort(name() + ".icache_port", this), 113 dcachePort(name() + ".dcache_port", this), 114 fastmem(p->fastmem), dcache_access(false), dcache_latency(0), 115 ppCommit(nullptr) 116{ 117 _status = Idle; 118} 119 120 121AtomicSimpleCPU::~AtomicSimpleCPU() 122{ 123 if (tickEvent.scheduled()) { 124 deschedule(tickEvent); 125 } 126} 127 128unsigned int 129AtomicSimpleCPU::drain(DrainManager *dm) 130{ 131 assert(!drain_manager); 132 if (switchedOut()) 133 return 0; 134 135 if (!isDrained()) { 136 DPRINTF(Drain, "Requesting drain: %s\n", pcState()); 137 drain_manager = dm; 138 return 1; 139 } else { 140 if (tickEvent.scheduled()) 141 deschedule(tickEvent); 142 143 DPRINTF(Drain, "Not executing microcode, no need to drain.\n"); 144 return 0; 145 } 146} 147 148void 149AtomicSimpleCPU::drainResume() 150{ 151 assert(!tickEvent.scheduled()); 152 assert(!drain_manager); 153 if (switchedOut()) 154 return; 155 156 DPRINTF(SimpleCPU, "Resume\n"); 157 verifyMemoryMode(); 158 159 assert(!threadContexts.empty()); 160 if (threadContexts.size() > 1) 161 fatal("The atomic CPU only supports one thread.\n"); 162 163 if (thread->status() == ThreadContext::Active) { 164 schedule(tickEvent, nextCycle()); 165 _status = BaseSimpleCPU::Running; 166 notIdleFraction = 1; 167 } else { 168 _status = BaseSimpleCPU::Idle; 169 notIdleFraction = 0; 170 } 171 172 system->totalNumInsts = 0; 173} 174 175bool 176AtomicSimpleCPU::tryCompleteDrain() 177{ 178 if (!drain_manager) 179 return false; 180 181 DPRINTF(Drain, "tryCompleteDrain: %s\n", pcState()); 182 if (!isDrained()) 183 return false; 184 185 DPRINTF(Drain, "CPU done draining, processing drain event\n"); 186 drain_manager->signalDrainDone(); 187 drain_manager = NULL; 188 189 return true; 190} 191 192 193void 194AtomicSimpleCPU::switchOut() 195{ 196 BaseSimpleCPU::switchOut(); 197 198 assert(!tickEvent.scheduled()); 199 assert(_status == BaseSimpleCPU::Running || _status == Idle); 200 assert(isDrained()); 201} 202 203 204void 205AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 206{ 207 BaseSimpleCPU::takeOverFrom(oldCPU); 208 209 // The tick event should have been descheduled by drain() 210 assert(!tickEvent.scheduled()); 211 212 ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT 213 data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too 214 data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too 215} 216 217void 218AtomicSimpleCPU::verifyMemoryMode() const 219{ 220 if (!system->isAtomicMode()) { 221 fatal("The atomic CPU requires the memory system to be in " 222 "'atomic' mode.\n"); 223 } 224} 225 226void 227AtomicSimpleCPU::activateContext(ThreadID thread_num) 228{ 229 DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 230 231 assert(thread_num == 0); 232 assert(thread); 233 234 assert(_status == Idle); 235 assert(!tickEvent.scheduled()); 236 237 notIdleFraction = 1; 238 Cycles delta = ticksToCycles(thread->lastActivate - thread->lastSuspend); 239 numCycles += delta; 240 ppCycles->notify(delta); 241 242 //Make sure ticks are still on multiples of cycles 243 schedule(tickEvent, clockEdge(Cycles(0))); 244 _status = BaseSimpleCPU::Running; 245} 246 247 248void 249AtomicSimpleCPU::suspendContext(ThreadID thread_num) 250{ 251 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 252 253 assert(thread_num == 0); 254 assert(thread); 255 256 if (_status == Idle) 257 return; 258 259 assert(_status == BaseSimpleCPU::Running); 260 261 // tick event may not be scheduled if this gets called from inside 262 // an instruction's execution, e.g. "quiesce" 263 if (tickEvent.scheduled()) 264 deschedule(tickEvent); 265 266 notIdleFraction = 0; 267 _status = Idle; 268} 269 270 271Tick 272AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt) 273{ 274 DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 275 pkt->cmdString()); 276 277 // X86 ISA: Snooping an invalidation for monitor/mwait 278 AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner); 279 if(cpu->getAddrMonitor()->doMonitor(pkt)) { 280 cpu->wakeup(); 281 } 282 283 // if snoop invalidates, release any associated locks 284 if (pkt->isInvalidate()) { 285 DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 286 pkt->getAddr()); 287 TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask); 288 } 289 290 return 0; 291} 292 293void 294AtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt) 295{ 296 DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 297 pkt->cmdString()); 298 299 // X86 ISA: Snooping an invalidation for monitor/mwait 300 AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner); 301 if(cpu->getAddrMonitor()->doMonitor(pkt)) { 302 cpu->wakeup(); 303 } 304 305 // if snoop invalidates, release any associated locks 306 if (pkt->isInvalidate()) { 307 DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 308 pkt->getAddr()); 309 TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask); 310 } 311} 312 313Fault 314AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, 315 unsigned size, unsigned flags) 316{ 317 // use the CPU's statically allocated read request and packet objects 318 Request *req = &data_read_req; 319 320 if (traceData) { 321 traceData->setAddr(addr); 322 } 323 324 //The size of the data we're trying to read. 325 int fullSize = size; 326 327 //The address of the second part of this access if it needs to be split 328 //across a cache line boundary. 329 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 330 331 if (secondAddr > addr) 332 size = secondAddr - addr; 333 334 dcache_latency = 0; 335 336 req->taskId(taskId()); 337 while (1) { 338 req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 339 340 // translate to physical address 341 Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read); 342 343 // Now do the access. 344 if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { 345 Packet pkt(req, MemCmd::ReadReq); 346 pkt.refineCommand(); 347 pkt.dataStatic(data); 348 349 if (req->isMmappedIpr()) 350 dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt); 351 else { 352 if (fastmem && system->isMemAddr(pkt.getAddr())) 353 system->getPhysMem().access(&pkt); 354 else 355 dcache_latency += dcachePort.sendAtomic(&pkt); 356 } 357 dcache_access = true; 358 359 assert(!pkt.isError()); 360 361 if (req->isLLSC()) { 362 TheISA::handleLockedRead(thread, req); 363 } 364 } 365 366 //If there's a fault, return it 367 if (fault != NoFault) { 368 if (req->isPrefetch()) { 369 return NoFault; 370 } else { 371 return fault; 372 } 373 } 374 375 //If we don't need to access a second cache line, stop now. 376 if (secondAddr <= addr) 377 { 378 if (req->isLocked() && fault == NoFault) { 379 assert(!locked); 380 locked = true; 381 } 382 return fault; 383 } 384 385 /* 386 * Set up for accessing the second cache line. 387 */ 388 389 //Move the pointer we're reading into to the correct location. 390 data += size; 391 //Adjust the size to get the remaining bytes. 392 size = addr + fullSize - secondAddr; 393 //And access the right address. 394 addr = secondAddr; 395 } 396} 397 398 399Fault 400AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, 401 Addr addr, unsigned flags, uint64_t *res) 402{ 403 404 static uint8_t zero_array[64] = {}; 405 406 if (data == NULL) { 407 assert(size <= 64); 408 assert(flags & Request::CACHE_BLOCK_ZERO); 409 // This must be a cache block cleaning request 410 data = zero_array; 411 } 412 413 // use the CPU's statically allocated write request and packet objects 414 Request *req = &data_write_req; 415 416 if (traceData) { 417 traceData->setAddr(addr); 418 } 419 420 //The size of the data we're trying to read. 421 int fullSize = size; 422 423 //The address of the second part of this access if it needs to be split 424 //across a cache line boundary. 425 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 426 427 if(secondAddr > addr) 428 size = secondAddr - addr; 429 430 dcache_latency = 0; 431 432 req->taskId(taskId()); 433 while(1) { 434 req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 435 436 // translate to physical address 437 Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write); 438 439 // Now do the access. 440 if (fault == NoFault) { 441 MemCmd cmd = MemCmd::WriteReq; // default 442 bool do_access = true; // flag to suppress cache access 443 444 if (req->isLLSC()) { 445 cmd = MemCmd::StoreCondReq; 446 do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 447 } else if (req->isSwap()) { 448 cmd = MemCmd::SwapReq; 449 if (req->isCondSwap()) { 450 assert(res); 451 req->setExtraData(*res); 452 } 453 } 454 455 if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) { 456 Packet pkt = Packet(req, cmd); 457 pkt.dataStatic(data); 458 459 if (req->isMmappedIpr()) { 460 dcache_latency += 461 TheISA::handleIprWrite(thread->getTC(), &pkt); 462 } else { 463 if (fastmem && system->isMemAddr(pkt.getAddr())) 464 system->getPhysMem().access(&pkt); 465 else 466 dcache_latency += dcachePort.sendAtomic(&pkt); 467 } 468 dcache_access = true; 469 assert(!pkt.isError()); 470 471 if (req->isSwap()) { 472 assert(res); 473 memcpy(res, pkt.getConstPtr<uint8_t>(), fullSize); 474 } 475 } 476 477 if (res && !req->isSwap()) { 478 *res = req->getExtraData(); 479 } 480 } 481 482 //If there's a fault or we don't need to access a second cache line, 483 //stop now. 484 if (fault != NoFault || secondAddr <= addr) 485 { 486 if (req->isLocked() && fault == NoFault) { 487 assert(locked); 488 locked = false; 489 } 490 if (fault != NoFault && req->isPrefetch()) { 491 return NoFault; 492 } else { 493 return fault; 494 } 495 } 496 497 /* 498 * Set up for accessing the second cache line. 499 */ 500 501 //Move the pointer we're reading into to the correct location. 502 data += size; 503 //Adjust the size to get the remaining bytes. 504 size = addr + fullSize - secondAddr; 505 //And access the right address. 506 addr = secondAddr; 507 } 508} 509 510 511void 512AtomicSimpleCPU::tick() 513{ 514 DPRINTF(SimpleCPU, "Tick\n"); 515 516 Tick latency = 0; 517 518 for (int i = 0; i < width || locked; ++i) { 519 numCycles++; 520 ppCycles->notify(1); 521 522 if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 523 checkForInterrupts(); 524 checkPcEventQueue(); 525 } 526 527 // We must have just got suspended by a PC event 528 if (_status == Idle) { 529 tryCompleteDrain(); 530 return; 531 } 532 533 Fault fault = NoFault; 534 535 TheISA::PCState pcState = thread->pcState(); 536 537 bool needToFetch = !isRomMicroPC(pcState.microPC()) && 538 !curMacroStaticInst; 539 if (needToFetch) { 540 ifetch_req.taskId(taskId()); 541 setupFetchRequest(&ifetch_req); 542 fault = thread->itb->translateAtomic(&ifetch_req, tc, 543 BaseTLB::Execute); 544 } 545 546 if (fault == NoFault) { 547 Tick icache_latency = 0; 548 bool icache_access = false; 549 dcache_access = false; // assume no dcache access 550 551 if (needToFetch) { 552 // This is commented out because the decoder would act like 553 // a tiny cache otherwise. It wouldn't be flushed when needed 554 // like the I cache. It should be flushed, and when that works 555 // this code should be uncommented. 556 //Fetch more instruction memory if necessary 557 //if(decoder.needMoreBytes()) 558 //{ 559 icache_access = true; 560 Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq); 561 ifetch_pkt.dataStatic(&inst); 562 563 if (fastmem && system->isMemAddr(ifetch_pkt.getAddr())) 564 system->getPhysMem().access(&ifetch_pkt); 565 else 566 icache_latency = icachePort.sendAtomic(&ifetch_pkt); 567 568 assert(!ifetch_pkt.isError()); 569 570 // ifetch_req is initialized to read the instruction directly 571 // into the CPU object's inst field. 572 //} 573 } 574 575 preExecute(); 576 577 if (curStaticInst) { 578 fault = curStaticInst->execute(this, traceData); 579 580 // keep an instruction count 581 if (fault == NoFault) { 582 countInst(); 583 if (!curStaticInst->isMicroop() || 584 curStaticInst->isLastMicroop()) { 585 ppCommit->notify(std::make_pair(thread, curStaticInst)); 586 } 587 } 588 else if (traceData && !DTRACE(ExecFaulting)) { 589 delete traceData; 590 traceData = NULL; 591 } 592 593 postExecute(); 594 } 595 596 // @todo remove me after debugging with legion done 597 if (curStaticInst && (!curStaticInst->isMicroop() || 598 curStaticInst->isFirstMicroop())) 599 instCnt++; 600 601 Tick stall_ticks = 0; 602 if (simulate_inst_stalls && icache_access) 603 stall_ticks += icache_latency; 604 605 if (simulate_data_stalls && dcache_access) 606 stall_ticks += dcache_latency; 607 608 if (stall_ticks) { 609 // the atomic cpu does its accounting in ticks, so 610 // keep counting in ticks but round to the clock 611 // period 612 latency += divCeil(stall_ticks, clockPeriod()) * 613 clockPeriod(); 614 } 615 616 } 617 if(fault != NoFault || !stayAtPC) 618 advancePC(fault); 619 } 620 621 if (tryCompleteDrain()) 622 return; 623 624 // instruction takes at least one cycle 625 if (latency < clockPeriod()) 626 latency = clockPeriod(); 627 628 if (_status != Idle) 629 schedule(tickEvent, curTick() + latency); 630} 631 632void 633AtomicSimpleCPU::regProbePoints() 634{ 635 BaseCPU::regProbePoints(); 636 637 ppCommit = new ProbePointArg<pair<SimpleThread*, const StaticInstPtr>> 638 (getProbeManager(), "Commit"); 639} 640 641void 642AtomicSimpleCPU::printAddr(Addr a) 643{ 644 dcachePort.printAddr(a); 645} 646 647//////////////////////////////////////////////////////////////////////// 648// 649// AtomicSimpleCPU Simulation Object 650// 651AtomicSimpleCPU * 652AtomicSimpleCPUParams::create() 653{ 654 numThreads = 1; 655 if (!FullSystem && workload.size() != 1) 656 panic("only one workload allowed"); 657 return new AtomicSimpleCPU(this); 658} 659